Characterization of Spiral Planar Inductors Built on Printed Circuit Boards

Monica Zolog Dan Pitica and Ovidiu Pop

,

Applied Electronics Department, Technical University of Cluj-Napoca, Romania

Abstract. The purpose of this paper is to propose an electrical model for spiral planar inductors on PCBs and estimate the electrical parameters ofthis model according to the technological parameters. In order to evaluate the accuracy of the model, several inductors on PCB were designed and the measurements were compared to the theoretical results. The obtained electrical model was validated by Pspice simulation. The design of an electrical circuit consists of several stages among which a very useful one is the simulation. This process considerably reduces the time required to complete a project as it helps the designer estimate the behavior of the circuit before actually building it. In the case of circuits that use inductors built on the PCB the simulation stage cannot be fulfilled due to the fact that simulators' libraries don't contain models for this type of inductors. These inductors are special components that require an appropriate simulation model that takes into account the parasitic elements that appear in the case of such a design. If these parameters are known (using some theoretical or experimental methods), then it is possible to integrate the corresponding model in the tested circuit and analyze the effect of this component over the rest of the circuit. The advantages of such inductors over the usual ones become from the manufacturing process that provides high-quality components, the performances of the systems being strongly influenced by the performance of its
components.

1. INTRODUCTION
In the last years, the interest for on-board passive components has increased tremendously. While there are several options for capacitors and most of these implementations are easy to model, considerable

2. THEORETICAL BACKGROUND
Square spirals are popular because of the ease of their layout. However, other polygonal spirals have also been used in circuit design. Some designers prefer polygons with more than four sides to improve performance. Among these, hexagonal and octagonal inductors are used widely. Fig. 1(a)-(d) show the layout for square, hexagonal, octagonal, and circular inductors, respectively. For a given shape, an inductor is completely specified by the number of turns n, the turn width w, the turn spacing s, and any one of the following: the outer diameter dcI,, the inner diameter djn, the average diameter davg=0. 5(d0,,+d1n), or the fill ratio, defined as A =(doutdin)/(do+din). Starting from the existing models for embedded inductors [1]-[3], we propose an electrical model for spiral inductors on printed circuit boards. The electrical model is presented in Figure 2. While the inductance was computed using the formulas given in

effort was needed for the design and modeling of inductor implementations, of which the only practical options are bond wires and planar spiral geometries. Although bond wires permit a high quality factor (Q) to be achieved, with typical Q's in the 20-50 range, their inductance values are constrained and can be rather sensitive to production fluctuations [2]. On the other hand, planar spiral inductors have limited Q's, but have inductances that are well-defined over a broad range of process variations. Thus, planar spiral inductors have become essential elements of communication circuit blocks such as voltage controlled oscillators (VCO's), low-noise amplifiers (LNA's), mixers, and intermediate frequency filters (IFF's).
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a)

b)
Fig. 1. On-board inductors

c)
2. An expression based on approximation given in [1]:

dc d)
current

sheet

LS
Fig. 2. Electrical model of the planar spiral inductor

[Lof2ndavg

C1

Al+c4 /A2) .
~jfI -+ C3

Ac4'

(2)

[1] and [2], for the resistance and the capacitance we considered the approach from [4].

For determining the inductance of the discrete planar spiral inductors, several expressions were used:
1. A modified Wheeler formula given in [2] states that the inductance can be calculated as:

where: - p0 - is the permeability of the vacuum,p0= 4n1 10-7 [N-A-2] - n, davg,, A - have the same significance as mentioned above - the coefficients C1, C2, C3 ,C4 are layout dependent (See Table 2.) c2 c4 cl c3 Shape
1.27 1.09 1.07
1

2.07 2.23 2.29 2.46

0.18 0
0 0

0.13 0.17 0.19 0.2

Square

Lmw

Klo 1+K2 -A

avg

(1)

where: - p0 - is the permeability of the vacuum, p0= 4nt 10-7 [N A-2] - n, davg, A - have the same significance as mentioned above - K1, K2- are coefficients that depend on the layout (See Table 1.) K1 K2 Shape
2.34
2.33 2.25
2.75 3.82 3.55

Hexagonal Octagonal Circle

Tab. 2. Coefficients for current sheet expression

3. An expression based on a data fitting technique, which yielded the expression [2]:

Lmon = fldal ~out

mon

Wa2

da3
-

avg

a4

a5

(3)

Square

Hexagonal Octagonal

where: - n, w, s, davg,, dout as mentioned above

have the same significance

- /, ai- are layout dependent coefficients (See Table 3.)

Tab. 1. Coefficients for modified Wheeler expression

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The results obtained by applying these formulas are not identical, but the difference in the inductance doesn't exceed 10%.

Fig. 3. Two rectangular conductors are located distance d apart on the top of a circuit board with thickness h and relative dielectric constant -r

The series resistance is calculated using the following expression [3]:

3 1.62E-03 1.28E-03 1.33E-03

The capacitance per unit length is given approximately by:

ocl

o2

o3
2.4

o4
1.78

o5
-0.03

Shape
Square Hexagona l

-1.21 -0.147 -1.24 -0.174 -1.21 -0.163

C I

nr(edf)WO [F/m]
In 1 7;d-w)~+I t+
27.8

2.47
2.43

1.77

-0.049
-0.049

1.75

Octagonal

Tab. 3. Coefficients for data fitted monomial expression

In
where:

n(d w) + I [pF/m]
w+

er (eff)
t

(5)

pI/
w.8. 1-e S

(4)

where: p - metal resistivity at dc [Q&m] 1 - overall length of the spiral w - line width

o - vacuum permittivity, o =8.8541878176 x 10-12 F/m 8r(e/5- relative electric permittivity is the result of placing the conductors in an inhomogeneous media (in the case of the conductor lands on printed circuit boards - the air and the dielectric). Its value is computed as a function of the relative permittivity of the substrate:

a -metal skin depth,

t- metal thickness

8=

2 71; -H f

P
-

L o Mr-

Er(ef/) -1 for d<h

r(ef

+1

for

d h

(6)

The capacitance Cs is computed starting from the approach in [4]. The capacitance value between horizontal, rectangular conductors is important because this configuration closely approximates conductor lands on printed circuit boards such as those shown in Figure 3.

h - the height of the insulator We can consider the unit length to be very small, so that the two conductors that represent adjacent turns can be seen as parallel conductors. The length of the spiral is then computed and multiplied with the capacitance per unit length.

3. RESULTS
The model needed to be validated by simulated as well as by measured data. For this, inductors having different geometric parameters (width of the conductor, spacing between adjacent conductors, number of turns) were designed. The influence of the inductor's geometry was also analyzed (square spiral, hexagonal, octagonal and circular). The model was verified using a simulation tool (PSpice) and the results were compared with the measured data.

-a

-1 ,

insulator

E;

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As an example, we present a round planar spiral that was made, having the following geometrical parameters: width of the conductor w= 0.2 mm, spacing between the turns s=0.2 mm, number of turns n= 17, internal diameter din= 1.55 mm (Figure 5). For this design, the value computed for the inductance using (2) is 1.93 pfH, while the measured one is 2.2 pfH (the measurement was performed using an LRC bridge).

s= -davg Ls 2
n

cl 1
.

I~n A4*2 I+3 A

2 +C
c

take into account the tolerance of the metal thickness (1.75 ptm) as well as the one of the conductor width, the computed resistance is 2.8 Q. The electric Ohm resistivity of electroless Cu depositions on dielectric substrates is a function of their thicknesses too. As the dimensions of interconnects shrink, the confinement effects associated with a very small grain size lead to a significant increase in the resistivity of the metal. Substantial deviations (up to 10-20 times) from the standard resistivity were observed in [5].

4. t.10-7 .172 8630 1 (l( 2.46 +0.2.O.822

2
=

P./= 0.2 10-3 8 -I-0.482 RS 1= 0.2 .10-3.1 8. 106 2.3 Q s-wt 1.72p1
=

(8)

Y 0.82

1.93 [,uHl]

(7)

RS =Pw= W *t

1.72-10- .0.46 0.18.10-3* 16.2510 6-6

(9)

The resistance was computed to be 2.3 Q and measured 3.3 Q (this was expected because the conductor width is actually smaller than 0.2 mm due to technological reasons). The type of copper clad sheet used was FR4 with metal thickness t 18 ptm, metal resistivity for copper p= 1.72 10-8 [Qm]. If we

Figure 4 illustrates the increase of the resistance with frequency (the effect of metal skin depth). When computing the capacitance, we have to take into account that the width of the insulator is h= 1.5mm and er=4.1. We consider er,/ 1 using (6.1). By applying (5) we obtain CGl= 19 pF/m.

Rs vs. f
70

60
50
u

E 40
0 un

30
20 10
-

oW A Th 11 XS11

||

|z
1.E+04

s re

1.E+00

1.E+01

1.E+02

1.E+03

1.E+05 f [Hz]

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

Fig. 4. Rs(f)

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278 a

(eff )

w+t 27.8.1 3 0 K1 [pF/m] = 19 [pF/m] =f~

200 + 18

(10)

(0

fo=-29-LC

(12)

The length of the spiral was computed using the following formula:

/= Z

(R2 -R)2
w+s

n(78552 775 2)048m

200 + 200

(11)

The impedance of the component is compared with the impedance of the ideal inductor in Figure 7. If we take a closer look to these results (Figure8), we observe that the impedance of the proposed model exceeds 10% of the ideal inductor impedance in the following intervals: 1kHz-445kHz (model impedance > ideal impedance; the series resistance has a 1 0.7MHz-49MHz dominant (model effect); impedance > ideal impedance); and at frequencies higher than 51.6 MHz (model impedance < ideal impedance; the parasitic capacitance is dominant). The component can be used as an inductor in the range of frequencies 445kHz-1 0.7MHz (Figure8).

Fig. 5. Round planar inductor

In order to verify the model, the configuration in Figure 6 was simulated in Pspice. The parasitic capacitance is then 9.12 pF and it is very difficult to be measured because it is too small.
inductor model
R1I LS RS

Fig.7. The component impedance and the ideal inductor impedance for Ls=1.93 pfH, Cs=9.12 pF, RS=2.8 Q.

~~~~~~C
\

k |

| |

t| 1 | | P | P

|Impedance of the

model

-~~~~~~~~~~~~~~~~~~~~~~~~~~~1 --ed -nc of -h -o-dl- -;< ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~-:-:-0

Cdeito fro th .i..pe.dan..ce. .~~~~~~~~~~~~~h ida .ind....uc .\.tor.. ....

.---------

Fig.6. The circuit used to analyze the inductor. RI is the resistance of the signal generator (150 Q). Ls, Rs, Cs represent the parameters of the planar inductor.

~~~~~~~~~~~~~~~~~~~~~~~~~---0--r--T---

---

------------r--

---r--T--l----- ---|--

-- ----0----0----l--l-- - Ofte ido

The effect of the parasitic elements was analyzed by comparison with an ideal inductor. In the simulation we considered Ls= 1.93 fiH, RS=2.8Q and Cs=9.12 pF. The resonance frequency is foz3 8 MHz.

Fig.8. The range in which the component can be used as inductor (it doesn't exceed 10% of the ideal impedance

value)

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4. CONCLUSIONS AND FUTURE WORK

A physical model for planar spiral inductors on PCB is presented. Parasitic elements are considered and analyzed. The inductor model shows good agreement with measured and published data. Simple inductors on a single layer PCB were designed. In the future we plan to analyze how PGS patterned ground shield - (beneath of insulator layer) improves the performance of inductors. In order to obtain higher values for the inductance while keeping the occupied area as small as possible, we'll try to design an inductor on a two-layer PCB. In this case a supplementary parasitic capacitance Cp (see Figure 2) appears between the two spirals. The worst case is the one presented in figure 10 a, because the overlap area of the turns is maximum. The minimum parasitic capacitance between the two layers is expected to be obtained for the configuration in figure 10 b. As one can observe, the overlap area between the turns from the two layers is significantly reduced by shifting the spiral from one of the sides.
/ /
4 ~~~~~~~~~~insulator

Fig.9. Square inductor with PGS

-copper
-(
-

/~ PGS

copper

____________ Wb)

Fig.10. Inductor on a two-layer PCB a) worst case; b) most favorable case

REFERENCES
[1] Charles S. Walker, "Capacitance, Inductance and Crosstalk Analysis", Artech House, 1990 [2] Goran Stojanovic, Ljiljana Zivanov and Mirjana Damnjanovic, "Optimal Design of Circular Inductors", Elec. Energ. Vol. 18, No. 1, April 2005 [3] Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, and Thomas H. Lee, "Simple Accurate Expressions for Planar Spiral Inductances", IEEE Journal of Solid-state circuits, Vol. 34, No. 10, October 1999 [4] C. Patrick Yue, Changsup Ryu, Jack Lau, Thomas H. Lee, and S. Simon Wong, "A physical model for planar spiral inductors on silicon" [5] M. Radoeva, B. Radoev, "Ohm resistivity of electroless copper layers as a function of their thicknesses", Journal of Materials Science, Volume 30, Number 9 /May, 1995 [6] Sylvain Maitrejean, Roland Gers, Thierry Mourier, Alain Toffoli, Gerard Passemard, "Cu Resistivity in Narrow lines: Dedicated Experiments for Model Optimization", Material Research Society

4,--- insulator

-<<copper

a)

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