JK, T, and D Flip-Flops

Dept. of CSIE, Fu Jen Catholic University CAD Laboratory (SF-640) 2010/5

JK Flip-Flop with Synchronous Reset

Input
J, K, Clock, and Reset (Active Low)

Output
Q and Q
J 0 0 J K >clk Q Q
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Function Table
positive-edge triggered
Reset

K 0 1 0 1

Qn Q 0 1 Q
2

1 1

Verilog Code for JK Flip-Flop (Behavioral Modeling)(1/3)

module JK-FF-B(); // behavioral style always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset, active low Q <= 1b0; else Q <= (J & ~Q)|(~K & Q); // characteristic equation end // always assign Qbar = ~Q; endmodule

2011/5/2

Verilog Code for JK Flip-Flop (Behavioral Modeling)(2/3)

always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset, active low Q <= 1b0; else if (J == 0 && K == 0) // No change Q <= Q; else if (J == 0 && K == 1) // Clear Q <= 0; else if (J == 1 && K == 0) // Set Q <= 1; else if (J == 1 && K == 1) // Complement Q <= Qbar; end // always assign Qbar = ~Q;
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Verilog Code for JK Flip-Flop (Behavioral Modeling)(3/3)

always @(posedge Clock) begin // positive-edge triggered if (!Reset) // synchronous reset, active low Q <= 1b0; else begin case ({J, K}) 2b00: Q <= Q; // No change 2b01: Q <= 1b0; // Clear 2b10: Q <= 1b1; // Set 2b11: Q <= Qbar; // Complement endcase end // end // always assign Qbar = ~Q; 2011/5/2

Verilog Code for JK Flip-Flop (Dataflow Modeling)

module JK-FF-D(); // dataflow style wire Qn; // the next state Qn always @(posedge Clock) begin if (!Reset) // synchronous reset, active low Q <= 1b0; else Q <= Qn; // assign the next state end // always assign Qn = J & ~Q | ~K & Q; // characteristic equation of JK FF assign Qbar = ~Q; endmodule
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T Flip-Flop with Asynchronous Preset

Input
T, Clock, and Preset (Active High)

Output
Q and Q
T 0 1 T >clk Q Q
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Function Table
negative-edge triggered
Preset

Qn Q Q

Verilog Code for T Flip-Flop (Behavioral Modeling)(1/3)

module T-FF-B(T, Preset, Clock, Q, Qbar); // behavioral style always @(negedge Clock or posedge Preset) begin //negative-edge triggered if (Preset) // asynchronous preset, active high Q <= 1b1; else Q <= ( T & ~Q ) | ( ~T & Q) // characteristic equation // Q <= T ^ Q; end // always assign Qbar = ~Q; endmodule
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Verilog Code for T Flip-Flop (Behavioral Modeling)(2/3)

always @(negedge Clock or posedge Preset) begin //negative-edge triggered if (Preset) // asynchronous preset, active high Q <= 1b1; else if ( T == 0) // No change Q <= Q; else if ( T == 1) // Complement Q <= Qbar; end // always assign Qbar = ~Q;
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Verilog Code for T Flip-Flop (Behavioral Modeling)(3/3)

always @(negedge Clock or posedge Preset) begin // positive-edge triggered if (Preset) // asynchronous preset, active high Q <= 1b1; else begin case (T) 1b0: Q <= Q; // No change 1b1: Q <= Qbar; // Complement endcase end // else end // always assign Qbar = ~Q;
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Verilog Code for T Flip-Flop (Dataflow Modeling)

module T-FF-D(T, Prest, Clock, Q, Qbar); wire Qn; // the next state Qn always @(negedge Clock or posedge Preset) // negative-edge triggered if (Preset) Q <= 1b1; else Q <= Qn; end // always assign Qn = T Q ; // characteristic equation of T flip-flop assign Qbar = ~Q; endmodule // assign the next state // asynchronous preset , active high // dataflow style

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D Flip-Flop with Synchronous Reset and Preset

Input
D, Clock, Reset and Preset (both Active Low)

Output
Q and Q
Reset Preset D 0 1 D >clk Reset Q Q 1 1 X 0 1 1 X X 0 1 Qn Qn 0 1 0 1 1 0 1 0

Function Table
positive-edge triggered
Preset

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Verilog Code for D Flip-Flop (Behavioral Modeling)

Exercised

by students

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Verilog Code for D Flip-Flop (Dataflow Modeling)

Exercised

by students

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14

Functional Simulation of Flip-Flops

Exercised by students. Compare the simulation results for each type of flip-flops modeled by behavioral and dataflow modeling.

Add a XOR gate which connects the outputs of two flip-flops (e.x. T-FF-B and T-FF-D). (See Next Slide)
It should be 0 for all input values of T and Preset.

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Checking the Output Difference of Two Flip-Flops

Logic schematic for checking the equivalence of two T flip-flops. The other types of flip-flops can be checked in the same way.
Preset T Q Behavioral >clk Q T F

Clock

Q Dataflow >clk Q
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