Sheet

1 of 18

L.C oscillator Tutorial
J P Silver

E-mail: john@rfic.co.uk

1 ABSTRACT
This tutorial describes the operation of a basic L.C
oscillator as used in RFIC circuits etc. The pertinent
design parameters are given together with their rele-
vant equations to allow basic hand calculations be-
fore simulation is attempted. The initial design con-
sists of a fixed frequency oscillator that is further
developed into a voltage controlled oscillator (VCO),
by the use of MOS devices configured as varactors.
Finally a worked example is given to highlight the
design steps required and CAD simulations are also
described.
2 INTRODUCTION
L.C oscillators are probably the most common type of
oscillator used in RFIC design. They can be designed for
a fixed frequency and variable frequency operation (with
the use of a varactor). The performance of the oscillator
is determined by the Quality factor of the L-C resonator.
Usually, a spiral inductor is used in the resonator and
these have quite low Qs of around 3-5 at 2.5GHz. If a
low-phase noise design is required the inductor can be
made off-chip. The inductor can be either resonated
with the device drain capacitance or by adding a shunt
capacitor (on chip or off).

3 OSCILLATOR DESIGN
PHASE NOISE[1].
For a discussion on phase noise read the Phase Noise
Tutorial.

But in summary Leesons equation is given below:-
1
Q 2f
+ 1
2P
FkT
= ) ( L
2
L m avs
(
(

|
.
|

\
|
+
|
|
.
|

\
|
+
fm
fc f
fm
fc
f
o
m
Usually the phase noise is specified in dBc/Hz ie :-

L = 10Log
FkT
2P
1+
2f Q
dBc / Hz
10
avs
m L
( ) f
fc
fm
f fc
fm
m
o
+
|
\

|
.
|
|
+
|
\

|
.
|

(
(

2
1
The Leeson equation identifies the most significant
causes of phase noise in oscillators, in particular the key
parameter is the loaded Q of the resonator. We know that
typically in CMOS the loaded Q of a spiral inductor is in
the range 3-5. Therefore, if a tighter phase noise specifi-
cation is required then the inductor will need to be off-
chip.
3.1 L-C OCILLATOR OPERATION
The circuit of the L-C oscillator is shown in Figure 1.
M2
L2
Vcc
M1
L1
M3
Itail
C1
Vout1
Vout2
Cross-Coupling
Vbias
Figure 1 Schematic diagram of the cross-coupled
L-C MOS oscillator. M3 sets the currents through
each arm of the differential oscillator, and M1 & M2
provide the negative impedance. The inductors L1 &
L2 may be off-chip (depending on the phase noise
requirement) and the resonating capacitors may be
the drain capacitances of the devices themselves.
Each arm of the oscillator has a L-C tank circuit that
determines the frequency of oscillation and form the
drain loads. Frequency dependant signals at the drains
are then cross-coupled to the other devices gate, which
Resonator Q
Phase perturbation
Flicker effect
Sheet
2 of 18

creates a negative impedance of value 1/gm at the drain
terminals.

Generally then:
( )
( )
f.L . 2
Vt - Vgs
I
I get to Rearrange
Q
f.L . 2
I
Vt - Vgs
Therefore,
Vt) - (Vgs
I
gm Where
Q
f.L . 2
gm
1
: n oscillatio For
Q
f.L . 2
inductor of R Series
D
D
D
D
U
U

=
>
=
>
=
To ensure reliable startup, L-C oscillators are designed
to have a startup safety factor of at least 2 ie

U
Q
f.L . 2
p
gm
2
R = >
3.2 VARIABLE FREQUENCY OSCILLATOR
(VCO)
From the previous section we have seen how cross-
connecting the two transistors gives a negative imped-
ance of 1/gm. We also know that this value has to ex-
ceed the losses of the resonator in order for the circuit to
oscillate.

For this tutorial we shall design an example Vco with the
following specification:

Parameter Specification Units
Centre Frequency 2.5 GHz
Tuning Bandwidth 500 MHz
Ko >100 MHz/V
Phase noise (10KHz offset) > 70 dBc/Hz
Supply 2.5 V
Power consumption <100 mW
First of all we need to determine the minimum loaded Q
of the resonator to achieve the required phase noise per-
formance. The values of the circuit/resonator can be fed
into Leesons equation or the ADS simulation of Figure
2 run. The resulting phase noise prediction of this simu-
lation is shown in Figure 3 and shows that if we use a
resonator with a minimum loaded Q of 5 then we should
achieve our phase noise goal.
VCO_OL
This simulates the
open-loop phase noise of
the VCO
PhaseNoiseMod
MOD2
QL=5
NF=10 dB
Fcorner=100 kHz
Rout=50 Ohm
Fnom=fcentre
Noi se
Mod
Phase
VAR
VAR3
fcentre=2500MHz
Eqn
Var
HarmonicBalance
HB1
NoiseNode[1]="PNoise_OL"
NLNoiseStop=1 MHz
NLNoiseStart=100 Hz
NLNoiseMode=yes
Order[1]=7
Freq[1]=fcentre
HARMONIC BALANCE
MeasEqn
meas1
PNoise_OLout=real(PNoise_OL[0])
VCO_OLout=VCO_OL[2]
Eqn
Meas
PNoise_OL
PM_DemodTuned
DEMOD2
Sensitivity=180/pi
Fnom=fcentre
Rout=50 Ohm
P_1Tone
PORT1
Freq=fcentre
P=dbmtow(10)
Z=50 Ohm
Num=1
Figure 2 ADS simulation to predict phase noise of an
oscillator. Here we have entered the Q of the resonator
of 5 (3-5 being the typical Q of a on-chip spiral induc-
tor). We have made assumptions of the noise figure
(10dB), output power (0dBm) and output impedance (50
ohms).

EqnPhaseNoise=10*log(0.5*VCO_phasenoise..PNoise_OL.noise**2)
m2
indep(m2)=
plot_vs(PhaseNoise, noisefreq)=-78.492
1.000E4
1E3 1E4 1E5 1E2 1E6
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-180
0
noisefreq, Hz
PhaseNoise
m2
Phase noise prediction assumimg loaded Q of 5 @ 2500MHz
Figure 3 Phase noise prediction of the L-C oscillator with a
resonator Q of 5, resulting in a phase noise of 78dBc/Hz at
an offset of 10KHz.
Sheet
3 of 18

However, varactors with a high tuning constant (Ko
(MHz/V) will generate a lot of modulation noise and
may well dominate the phase noise generated by the de-
vice and resonator.

The loaded Q of the resonator, will be determined by the
loaded Q of the inductor and the loaded Q of the
MOSFET varactor (variable capacitor). Each component
can be represented by an ideal reactance with a parallel
resistance representing the loss of the component.

Typical Q values for an on-chip spiral inductor at
2.5GHz is 3 to 5. Therefore, if we wish to use an induc-
tor with a higher Q, we have to consider off-chip induc-
tors. Off-chip inductors are commonly formed using
bond-wires and for completeness of this tutorial design
notes on bond wire inductors will be given.

3.2.1 Bond wires as inductors [2]

Larger inductances can be realised with bond-wires that
have Quality (Q) factors an order of magnitude higher
than on-chip spiral inductors.

Note that low Q spiral inductors can still be used for low
phase noise applications or for providing bias to the
varactor(s).

The inductance of a bond wire is given by:

|
|
.
|

\
|
|
.
|

\
|
= 75 . 0
2
2
.
L
o
r
l
Ln

l
Where r = radius of wire - typically 0.025mm (1mil)
uo = 4 10
-7
(permeability of free-space).

As we go higher in frequency the skin effect becomes
more important and increases the losses of the inductor:

(m) Length
(m) wire of radius r
7
4.47x10 (S/m) ty Conductivi
m, in depth skin Where
2
1
2
R
=
=
= =
=
= =
l

.
f.
r .. r.
l
o
We can now calculate the unloaded Q of the inductor
thus:

f
r
l
Ln
R
L
o
. . . 75 . 0
2
2r
.
Q t
e
|
|
.
|

\
|
|
.
|

\
|
= =
The graph of Figure 4 shows the inductance of a 1mil
diameter gold bond wire for varying lengths.

Inductance vs Bond Wire Length
0.000
2.000
4.000
6.000
8.000
10.000
12.000
14.000
16.000
18.000
0 5 10 15
Length (mm)
I
n
d
u
c
t
a
n
c
e
(
n
H
)
Figure 4 Bond wire inductace (nH) vs Bond wire
length (mm) for a gold 1mil diameter bond wire.

If for example we have a 2mm gold bond wire (of diame-
ter 1mil) then we will have an inductance of 2nH .

The associated Q of 2mm bond wire will be around 80 at
a frequency of 2.5GHz a considerable improvement on
an on-chip inductor with a typical Q of between 3 & 5
at 2.5GHz. However, for our example we will assume an
inductor Q of 5 can be realized on-chip.

3.3 FREQUENCY CONTROL [3,4]
Using bond wires instead of on-chip inductors allows the
design of low phase noise oscillators but makes the fab-
rication more difficult as it is difficult to precisely set the
length of the bond wire. Also for use in Phase Locked
Loop (PLL) applications it is necessary to have variable
frequency. To make the fixed frequency oscillator into a
variable frequency oscillator (VCO) we add/incorporate
into the resonator a electronically controlled capacitor
known as a varactor.

In MOS technology we can realise a varactor by con-
necting a FET as a diode and applying a reverse bias to it
as shown in Figure 5.
Sheet
4 of 18

Vg
Vcontrol
Bulk
connected to
D&S
Vgs
Figure 5 Implementation of a varactor by con-
necting together the source, drain and bulk of a
MOS Fet (forming a diode) and applying a re-
verse bias across it.

There are two common connections of the MOS fet as a
diode:

(1) B-S-D connected together, with voltage applied
across the gate and B-S-D connection. If we plot capaci-
tance vs (Vcontrol-Vg = Vgs) then we get the response
shown in Figure 6. To simulate the varactor to deter-
mine the capacitance vs voltage characteristics, the ADS
simulation of the varactor is shown in Figure 12.
The disadvantage of this varactor is that the control volt-
age needs to be kept below weak inversion in order to
keep the capacitance reducing with increased control
voltage.

(2) In the second varactor, the voltage is applied across
the gate and bulk only (S & D unconnected) this is
known as an accumulation varactor and produces the
tuning characteristic shown in Figure 7.
The characteristic is more predictable in that the capaci-
tance always falls with increasing control voltage.

Note however, a normal varactors capacitance increases
with increased reverse bias, therefore, it will be impor-
tant to check the phasing of the PLL loop that the VCO
is being used in, otherwise the Vco will go to an end stop
and never lock up!!

Vgs
Cox
Accumulation
Strong
Inversion
Depletion
Weak
Inversion
Moderate
Inversion
C
mos

Figure 6 Capacitance variation of a P-mos ca-
pacitor with the bulk, source and drain connected
together as per Figure 5. Voltage is applied across
the gate and B-S-D connection.
Vgs
Cox
C
mos

Figure 7 Capacitance variation of a P-mos
capacitor with voltage applied across the gate
and Bulk connection (The source & drain are
unconnected).
Sheet
5 of 18

3.4 VARACTOR DESIGN EQUATIONS [5]
For this design we will be using the Accumulation
mode varactor, where the source and drain terminals are
unconnected and bias is applied across the gate and bulk
only.

We first need to determine the maximim capacitance of
the varactor shown as Cox in Figure 6 & Figure 7, fol-
lowed by the minimum capacitance (that will allow the
tuning bandwidth to be calculated) and the unloaded Q.

The value of Cox or C
MAX
is determined by the geometry
of the varactor:

fingers gate of Number N
& process) 14TB CMOS HP (For ) (96 m E 6 . 9 Tox
F/m 10 84542 . 8 Where
N .
ox
T
.W.L 3.9.
C or Cox
O
9
12
MAX
=
A =
=
=

x
o

The minimum value of the varactor is approximately

given by:

process) 14TB CMOS For F/m 9E (
e capacitanc drain gate C Where
.W C C
11 -
gdo
gdo MIN
=
=
~
To determine the maximum and minimum capacitance
for a range or W/L ratios it is easiest to use simulation.
The ADS schematic of Figure 12, shows an S-parameter
simulation, measuring Zin. On the resulting simulation
run the following equation has been used to determine
the capacitance in pF.

freq) * ) (Imag(Zin1 * PI * 1E12/(-2 C=
Using Table 1 we can select a size of varactor that is
going to resonate with the 2nH on-chip spiral inductor
at 2.5GHz with its middle value capacitance using:

2pF
2E
.2.5E 2.
1
L
.f 2.
1
C
9 -
2
9
2
=
|
.
|

\
|
=
|
.
|

\
|
=

Depending on the configuration two varactors are used
end to end across a single inductor (see Figure 13) (And
we need to use 2 times C resonating as capacitors in se-
ries!) or a varactor is connected to each of the two load
inductors (see Figure 14).

For this tutorial we will be simulating both design op-
tions.

W
(um)
L
(um)
Cmax
(pF)
Cnom
(pF)
Cmin
(pF)
50 0.6 0.071 0.0775 0.013
100 0.6 0.141 0.0835 0.026
150 0.6 0.211 0.125 0.039
200 0.6 0.282 0.167 0.052
250 0.6 0.352 0.208 0.065
300 0.6 0.423 0.25 0.078
350 0.6 0.493 0.29 0.090
400 0.6 0.564 0.33 0.103
450 0.6 0.634 0.375 0.116
500 0.6 0.705 0.430 0.129
550 0.6 0.775 0.459 0.142
600 0.6 0.846 0.50 0.154
650 0.6 0.916 0.54 0.167
700 0.6 0.986 0.583 0.180
750 0.6 1.057 0.625 0.193
800 0.6 1.127 0.667 0.206
850 0.6 1.198 0.709 0.219
900 0.6 1.268 0.749 0.231
950 0.6 1.339 0.792 0.244
1000 0.6 1.409 0.833 0.257
Table 1 Cmax & Cmin for an Accumulation
varactor (Using the HP 14B process) with various
W/L ratios. Note that we can increase the capaci-
tance by increasing the number of gate fingers in
parallel. So to give us a varactor with a nominal
capacitance of 4pF (ie two capacitors in parallel to
give 2pF) we could use a gate width of 500um with
10 fingers = 4.3pF.
Note that the parasitic capacitances of the 1/gm devices
will increase the minimum capacitance of the varactor
reducing the tuning range. This can only be evaluated
once the 1/gm device sizes are known.

The simulation of a P-type accumulation varactor
(Where the voltage is applied across the gate and bulk
only (S & D unconnected) with the dimensions of
W=600, L=0.6 and N=5, is shown in Figure 8 with the
resulting capacitance (pF) vs control voltage characteris-
tic shown in Figure 9.

Sheet
6 of 18

VAR
VAR3
L=0.6
W=500
Vcontrl=2.5
Eqn
Var
MM9_PMOS
MOSFET4
_M=1
Width=W um
Length=L um DC_Feed
DC_Feed1
DC_Feed
DC_Feed2
VAR
VAR2
Vcc=2.5
Fc=2500
Eqn
Var
V_DC
SRC2
Vdc=Vcontrl V
V_DC
SRC1
Vdc=Vcc V
Term
Term1
Z=50 Ohm
Num=1
S_Param
SP1
Center=Fc MHz
S-PARAMETERS
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
BSIM3_Model
cmosp
Xl=-1e-7
Xw=0
Noic=1.4e-12
Noib=2.4e3
Noia=9.9e18
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pv ag=14.4617331
Pscbe2=3.078664e-9
Pscbe1=6.898588e10
Pdiblcb=-0.0209265
Pdiblc2=9.858521e-3
Pdiblc1=1.300053e-5
Drout=7.988149e-4
Dsub=0.3593017
Etab=8.604543e-3
Eta0=0.111002
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nf actor=0.8428454
Vof f =-0.0939754
B1=5e-6
B0=4.703171e-6
A1=0
Pags=0.09532
Ags=0.2633783
Wketa=8.895347e-3
Lketa=-9.580923e-3
Keta=4.690296e-3
Vsat=1.57686e5
Prwb=-0.0733682
Prwg=-4.742166e-3
Prdsw=128.4338259
Rdsw=2.552456e3
Delta=0.01
Uc=-5.80218e-11
Ub=9.033053e-19
Ua=1.447557e-9
Dv t2=-0.061438
Dv t1=0.5624229
Dv t0=3.8366128
Nlx=1.867036e-7
W0=1e-5
K3b=-5
K3=96.6543548
Pk2=3.340684e-3
K2=0.0200888
K1=0.3913281
Pv th0=1.949468e-3
Vth0=-0.8017536
U0=183.1171264
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=9.587665e-9
Dwg=-1.585994e-8
Xpart=0.5
Cgbo=2e-9
Cgdo=2.56e-10
Cgso=2.56e-10
Pbswg=0.8
Mjswg=0.1912128
Cjswg=4.256e-11
Pbsw=0.8
Pb=0.914212
Mjsw=0.1842521
Cjsw=2.002874e-10
Mj=0.4683602
Cj=9.196812e-4
Tox=1.01e-8
Wwl=0
Wwn=1
Wln=1
Wl=0
Wint=2.151118e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=5.519082e-8
Js=0
Rsh=2.2
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
PMOS=y es
ParamSweep
Sweep1
Step=0.01
Stop=5
Start=0
SimInstanceName[6]=
SimInstanceName[5]=
SimInstanceName[4]=
SimInstanceName[3]=
SimInstanceName[2]=
SimInstanceName[1]="SP1"
SweepVar="Vcontrl"
PARAMETER SWEEP
DC_Block
DC_Block1
DC_Block
DC_Block2
Figure 8 ADS simulation to determine the variation in capacitance of a P-type Accumulation varactor diode
(Where the voltage is applied across the gate and bulk only (S & D unconnected) with the dimensions of
W=600, L=0.6 and N=5. The input impedance is measured by adding the Zin parameter box, to allow calcu-
lation of the capacitance at 2.5GHz. The resulting plot of results is shown in Figure 10.

Sheet
7 of 18

m1
i ndep(m1)=
pl ot_vs(C, Vsg)=0.705
freq=2.500500GHz
-1.620
m2
i ndep(m2)=
pl ot_vs(C, Vsg)=0.129
freq=2.500500GHz
1.850
-2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 -2.6 2.6
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.10
0.75
Vsg
C
m1
m2
Eqn C=1E12/(-2*PI*(i mag(Zi n1))*freq) P-MOS Accumulation Varactor diode
C (pF)
Eqn Vsg=2.5-Vcontrl

Figure 9 Resulting simulation plot of the ADS schematic (P-type Accumulation type varactor diode) shown
in Figure 8. The equation C converts the imaginary input impedance (Zin) to capacitance pF

Sheet
8 of 18

Finally, we need to calculate the unloaded Q of the
varactor by using the following approximate expression:

( )
Vs / m 13.6E ) .1E 136.(1E Vs / m to convert
process) CMOS14TB (For
/ Vs cm 1.36E mobility bulk Zero MUZ
ox MUZ.C' Kp
: by given factor gain Kp
ox.L P.C'
) VT - 12.Kp.(Vgs
Q
VT Vgs
L
W
.Kp.
ox.W.L P.C'
12
Q
2 3 - 2 - 2 - 2
2 2
2 mos
mos
= =
= =
=
=
=
=
process) 14TB CMOS HP (For ) (96 m E 6 . 9 Tox
F/m 10 84542 . 8 Where
F/m 3.59E
E 6 . 9
. 10 84542 . 8 3.9x
ox C'
ox
T
. 3.9.
or ox C'
O
9
12
2 3 -
9
12
A =
=
= =
= =

x
o

x
o

2 -3 -3
uA/V 8 4 .3.59E 13.6E Kp = =
( )
( )
35
0.6E . E 59 . 3 . .2.5E 2
(1.25) . 48E . 12
Qmos then
1.25V
2
Vdd
VT - Vgs that assume we If
2
6 - 3 9
6 -
~
=
= =

Note: To maximize the Q of the varactor we need to

keep L as short as possible!

3.5 RESONATOR Q & BANDWIDTH
The overall unloaded Q of the resonator will depend on
the loaded Qs of the inductor and varactor. However, if
we minimize the varactor gate length and use on chip
inductors the overall Q will be dominated by the Q of the
inductor:

actor IND res
Q Q Q
var
1 1 1
+ =
4.4
35
1
5
1 1
~ + =
res
Q
The ADS schematic of Figure 11 simulates the loaded Q
of the resonator (ie P-type varactor diode and on-chip
inductor). The resulting simulation plot with loaded Q
calculation is shown in Figure 10, showing a similar
loaded Q to the hand calculation.

For this initial design the varactor is connected directly
across the inductor giving the largest tuning range. This
however, may not always be required, as the ko
(MHz/V) will be very large. Ko is one of the variables in
PLL loop calculations and will give a large open loop
gain, which may be undesirable and prove difficult to
stabilize the loop. In addition, with such a sensitive VCO
comes the problem of noise on the varactor control line
will modulating on the VCO RF output.

An additional design will be given in this tutorial that
shows how the tuning bandwidth can be reduced, so
lowering Ko.
3.6 AMPLIFIER GM CALCULATION
In order to determine the minimum cross-coupled ampli-
fier negative GM we need to find the loss of the resona-
tor. For this we take the inductance and calculate Req:

O = =
=
38 1 .2E .2.5E 4.4.2 R
example our for and .fo.L Q.2 R
9 - 9
eq
eq

Therefore, the minimum Gm required for oscillation is:

D P) or (n
P N
eq
I .
L
W
2. GM
(10/7) ie 1.43 be now will margin up - start The
10mS. GM make margin some us give To
ary VCO compliment for - GM GM GM Where
7mS GM
R
1
GM
|
.
|

\
|
=
=
+ =
> >
K Where

Thus we can re-arrange to give the minimum W/L ratio
required to give oscillator:

D
2
2.K.I
gm
L
W
=
Sheet
9 of 18

We would obviously increase this ratio to give us margin
allowing for lower Q in the resonator (reducing Req) and
so ensure reliable startup and operation over tempera-
ture.

To calculate the gate widths we first have to decide on a
drain current, for this example set I
D
to 5mA.
m1
freq=
dB(S(1,1))=-5.152
2.512GHz
1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 5.0
-5
-4
-3
-2
-1
-6
0
freq, GHz
d
B
(
S
(
1
,
1
)
)
m1
m3
freq=
Qext=4.995
2.512GHz
1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 5.0
1
2
3
4
0
5
freq, GHz
Q
e
x
t
m3
Eqn Qext=real(Zin1)/(2*pi*freq*2.2e-9)

Figure 10 Frequency response of the resonator
circuit shown in Figure 11. The equation has been
added to determine the loaded Q of the circuit
resulting in a loaded Q of 4.99 compared to the
hand calculation value of 4.44.

3.6.1 N devices:

35 W 58
.5E 2.171E
) 0E 1 (
L
W
A/V.s 171.7E E 645 . 3 . 471E MUZn.Cox Kp
F/m 3.645E
9.6E
3.97x8.85E
Tox
o 3.97.
Cox
m 471E ) .1E 471(1E m to convert
471cm MUZn ox; MUZ.C' Kp
3 - -6 -
2 3
6 - 3 4 -
2 3 -
9
12
2 4 - 2 - 2 - 2
2
= = =
= = =
= = =
= =
= =

3.6.2 P devices:

120 W 200
.5E 2.49E
) E 5 0 1 (
L
W
A/V.s 49e 645 . 3 . 136e MUZn.Cox Kp
F/m 3.645e
9.6e
3.97x8.85e
Tox
o 3.97.
Cox
136cm MUZp ox; MUZ.C' Kp
3 - -6 -
2 3
6 - 3 4 -
2 3 -
9
12
2
= = =
= = =
= = =
= =

Estimation of phase noise performance

( )
[ ]
carrier from offset Frequency
resonator. the of resistance series equivalent Effective Reff
resonator. across amplitude voltage Peak V
.
oscillator of resistance Negative
resonator of resistance parallel Equivalent

factor safety Startup A
Where
2
. A 1 k.T.Reff.

A
2
2
Radial
V

L
A
o
= A
=
=
=
=
|
.
|

\
|
A
+
= A
From our example A ~ 138/(1/10E
-3
) = 1.38.

O = = =

7.15
4 . 4
.2E E 5 . 2 . 2 . . 2
Reff
9 9

Q
L Fo
res

( )
[ ]
( ) ( )[ ]
dBc/Hz 6 . 84
) E 44 . 3 log( 10 dB in get To
E 44 . 3
2
5 . 2
E 10
E 5 . 2
. 38 . 1 1 . 7.15 .293. 1.38E
2
. A 1 k.T.Reff.

9
9
2
3
9
23 -
2
2
=
=
=
|
|
.
|

\
|
+
|
|
.
|

\
|
A
+
= A

A
o
V

L
Sheet
10 of 18

BSIM3_Model
cmosp
Xl=-1e-7
Xw=0
Noic=1.4e-12
Noib=2.4e3
Noia=9.9e18
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pv ag=14.4617331
Pscbe2=3.078664e-9
Pscbe1=6.898588e10
Pdiblcb=-0.0209265
Pdiblc2=9.858521e-3
Pdiblc1=1.300053e-5
Drout=7.988149e-4
Dsub=0.3593017
Etab=8.604543e-3
Eta0=0.111002
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nf actor=0.8428454
Vof f =-0.0939754
B1=5e-6
B0=4.703171e-6
A1=0
Pags=0.09532
Ags=0.2633783
Wketa=8.895347e-3
Lketa=-9.580923e-3
Keta=4.690296e-3
Vsat=1.57686e5
Prwb=-0.0733682
Prwg=-4.742166e-3
Prdsw=128.4338259
Rdsw=2.552456e3
Delta=0.01
Uc=-5.80218e-11
Ub=9.033053e-19
Ua=1.447557e-9
Dv t2=-0.061438
Dv t1=0.5624229
Dv t0=3.8366128
Nlx=1.867036e-7
W0=1e-5
K3b=-5
K3=96.6543548
Pk2=3.340684e-3
K2=0.0200888
K1=0.3913281
Pv th0=1.949468e-3
Vth0=-0.8017536
U0=183.1171264
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=9.587665e-9
Dwg=-1.585994e-8
Xpart=0.5
Cgbo=2e-9
Cgdo=2.56e-10
Cgso=2.56e-10
Pbswg=0.8
Mjswg=0.1912128
Cjswg=4.256e-11
Pbsw=0.8
Pb=0.914212
Mjsw=0.1842521
Cjsw=2.002874e-10
Mj=0.4683602
Cj=9.196812e-4
Tox=1.01e-8
Wwl=0
Wwn=1
Wln=1
Wl=0
Wint=2.151118e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=5.519082e-8
Js=0
Rsh=2.2
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
PMOS=y es
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
S_Param
SP1
CalcGroupDelay =y es
Step=8 MHz
Stop=5 GHz
Start=1 GHz
S-PARAMETERS
VAR
VAR1
Bond_Wire=2.2
Vcontrol=1.3
Eqn
Var
MM9_PMOS
MOSFET4
_M=5
Width=500 um
Length=0.6 um
INDQ
L4
Rdc=0.0 Ohm
Mode=proportional to f req
F=2.5 GHz
Q=5
L=Bond_Wire nH
Term
Term1
Z=50 Ohm
Num=1
R
R2
R=1 kOhm
MM9_PMOS
MOSFET9
_M=5
Width=500 um
Length=0.6 um
V_DC
VDD2
Vdc=Vcontrol
Figure 11 ADS simulation to determine the loaded Q of the resonator circuit. The input impedance is meas-
ured by adding the Zin parameter box. The resulting plot of results is shown in Figure 10.
Sheet
11 of 18

DC_Feed
DC_Feed2
VAR
VAR2
Vcc=2.5
Fc=2500
Eqn
Var
V_DC
SRC2
Vdc=Vcontrl V
V_DC
SRC1
Vdc=Vcc V
Term
Term1
Z=50 Ohm
Num=1
S_Param
SP1
Center=Fc MHz
S-PARAMETERS
VAR
VAR3
L=50
W=10
Vcontrl=2.5
Eqn
Var
MM9_PMOS
MOSFET4
Width=W um
Length=L um DC_Feed
DC_Feed1
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
BSIM3_Model
cmosp
Xl=-1e-7
Xw=0
Noic=1.4e-12
Noib=2.4e3
Noia=9.9e18
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pv ag=14.4617331
Pscbe2=3.078664e-9
Pscbe1=6.898588e10
Pdiblcb=-0.0209265
Pdiblc2=9.858521e-3
Pdiblc1=1.300053e-5
Drout=7.988149e-4
Dsub=0.3593017
Etab=8.604543e-3
Eta0=0.111002
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nf actor=0.8428454
Vof f =-0.0939754
B1=5e-6
B0=4.703171e-6
A1=0
Pags=0.09532
Ags=0.2633783
Wketa=8.895347e-3
Lketa=-9.580923e-3
Keta=4.690296e-3
Vsat=1.57686e5
Prwb=-0.0733682
Prwg=-4.742166e-3
Prdsw=128.4338259
Rdsw=2.552456e3
Delta=0.01
Uc=-5.80218e-11
Ub=9.033053e-19
Ua=1.447557e-9
Dv t2=-0.061438
Dv t1=0.5624229
Dv t0=3.8366128
Nlx=1.867036e-7
W0=1e-5
K3b=-5
K3=96.6543548
Pk2=3.340684e-3
K2=0.0200888
K1=0.3913281
Pv th0=1.949468e-3
Vth0=-0.8017536
U0=183.1171264
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=9.587665e-9
Dwg=-1.585994e-8
Xpart=0.5
Cgbo=2e-9
Cgdo=2.56e-10
Cgso=2.56e-10
Pbswg=0.8
Mjswg=0.1912128
Cjswg=4.256e-11
Pbsw=0.8
Pb=0.914212
Mjsw=0.1842521
Cjsw=2.002874e-10
Mj=0.4683602
Cj=9.196812e-4
Tox=1.01e-8
Wwl=0
Wwn=1
Wln=1
Wl=0
Wint=2.151118e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=5.519082e-8
Js=0
Rsh=2.2
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
PMOS=y es
ParamSweep
Sweep1
Step=0.01
Stop=5
Start=0
SimInstanceName[6]=
SimInstanceName[5]=
SimInstanceName[4]=
SimInstanceName[3]=
SimInstanceName[2]=
SimInstanceName[1]="SP1"
SweepVar="Vcontrl"
PARAMETER SWEEP
DC_Block
DC_Block1
DC_Block
DC_Block2
Figure 12 ADS simulation for determining the tuning characteristics of a P-type MOS varactor. In this simu-
lation the bulk, source and drain are connected together to produce the response predicted in Figure 6. The
S-parameter simulation contains a Zin block and we use the imaginary term of this to determine the capaci-
tance of the varactor while sweeping the applied gate-source voltage (Vcontrl).
Sheet
12 of 18

VDD
vout2
VSS
BSIM3_Model
cmosn
Xl=-1e-7
Xw=0
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ub1=-7.61e-18
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pvag=0.1945781
Pscbe2=5e-10
Pscbe1=2.541131e10
Pdiblcb=-0.5
Pdiblc2=9.723614e-4
Pdiblc1=2.091364e-3
Pclm=0.7319137
Drout=0.0428851
Dsub=0.751089
Etab=2.603903e-3
Eta0=0.1178659
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nfactor=1.2410485
Voff=-0.0850186
B1=5e-6
B0=1.648829e-6
Pags=0.0968
Ags=0.1450882
Wketa=-5.792854e-3
Lketa=-0.0143698
Keta=3.997018e-3
A0=0.9059229
Vsat=1.174604e5
Prwb=-0.0586598
Prwg=0.0182608
Prdsw=-33.9337286
Rdsw=1.28604e3
Delta=0.01
Uc=1.831708e-11
Ub=1.582544e-18
Ua=1e-12
Dvt2=-0.1427458
Dvt1=0.9107896
Dvt0=6.5803089
Nlx=5.28517e-8
W0=1e-5
K3b=1.252205
K3=68.279056
Pk2=9.631217e-3
K2=-0.0316751
K1=0.825917
Pvth0=8.691731e-3
Vth0=0.6701079
U0=433.6065339
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=1.238214e-8
Dwg=-7.483283e-9
Xpart=0.5
Cgbo=2e-9
Cgdo=2.79e-10
Cgso=2.79e-10
Pbswg=0.99
Mjswg=0.1
Cjswg=2.2346e-10
Pbsw=0.99
Pb=0.99
Mjsw=0.1
Cjsw=4.437149e-10
Mj=0.7549569
Cj=5.067009e-4
Tox=1.01e-8
Tnom=27
Wwl=0
Wwn=1
Ww=0
Wln=1
Wl=0
Wint=2.277646e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=1.097132e-7
Js=0
Rsh=2.8
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
NMOS=yes
BSIM3_Model
cmosp
Xl=-1e-7
Xw=0
Noic=1.4e-12
Noib=2.4e3
Noia=9.9e18
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pvag=14.4617331
Pscbe2=3.078664e-9
Pscbe1=6.898588e10
Pdiblcb=-0.0209265
Pdiblc2=9.858521e-3
Pdiblc1=1.300053e-5
Drout=7.988149e-4
Dsub=0.3593017
Etab=8.604543e-3
Eta0=0.111002
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nfactor=0.8428454
Voff=-0.0939754
B1=5e-6
B0=4.703171e-6
A1=0
Pags=0.09532
Ags=0.2633783
Wketa=8.895347e-3
Lketa=-9.580923e-3
Keta=4.690296e-3
Vsat=1.57686e5
Prwb=-0.0733682
Prwg=-4.742166e-3
Prdsw=128.4338259
Rdsw=2.552456e3
Delta=0.01
Uc=-5.80218e-11
Ub=9.033053e-19
Ua=1.447557e-9
Dvt2=-0.061438
Dvt1=0.5624229
Dvt0=3.8366128
Nlx=1.867036e-7
W0=1e-5
K3b=-5
K3=96.6543548
Pk2=3.340684e-3
K2=0.0200888
K1=0.3913281
Pvth0=1.949468e-3
Vth0=-0.8017536
U0=183.1171264
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=9.587665e-9
Dwg=-1.585994e-8
Xpart=0.5
Cgbo=2e-9
Cgdo=2.56e-10
Cgso=2.56e-10
Pbswg=0.8
Mjswg=0.1912128
Cjswg=4.256e-11
Pbsw=0.8
Pb=0.914212
Mjsw=0.1842521
Cjsw=2.002874e-10
Mj=0.4683602
Cj=9.196812e-4
Tox=1.01e-8
Wwl=0
Wwn=1
Wln=1
Wl=0
Wint=2.151118e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=5.519082e-8
Js=0
Rsh=2.2
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
PMOS=yes
HarmonicBalance
HB2
ConvMode=Basic (Fast)
NoiseConMode=yes
Noisecon[1]="NC1"
EquationName[1]=
OscPortName="oscport1"
OscMode=yes
UseKrylov=no
FundOversample=4
Order[1]=5
Freq[1]=2.5 GHz
HARMONIC BALANCE
NoiseCon
NC1
NoiseNode[1]=vout2
PhaseNoise=Phase noise spectrum
CarrierIndex[1]=1
NLNoiseDec=1
NLNoiseStop=1 MHz
NLNoiseStart=10 Hz
HB NOISE CONTROLLER
VDD
MM9_PMOS
MOSFET11
Width=Wum
Length=L um
Model=cmosp
VAR
VAR2
L=1
VDD=1.5
Vcontrol=1.5
W=100
Eqn
Var
I_DC
SRC2
Idc=3.5 mA
INDQ
L4
Rdc=0.0 Ohm
Mode=proportional to freq
F=2.5 GHz
Q=80
L=2 nH
MM9_PMOS
MOSFET4
Width=500 um
Length=3 um
Model=cmosp
MM9_PMOS
MOSFET9
Width=500 um
Length=3 um
Model=cmosp
OscPort
oscport1
MaxLoopGainStep=
FundIndex=1
Steps=50
NumOctaves=4
Z=1.1 Ohm
V=
INDQ
L2
Rdc=0.0 Ohm
Mode=proportional to freq
F=2.5 GHz
Q=5
L=2.0 nH
VSS
MOSFET_NMOS
MOSFET8
Width=Wum
Length=L um
Model=cmosn
VSS
MOSFET_NMOS
MOSFET7
Width=Wum
Length=L um
Model=cmosn
VDD
MM9_PMOS
MOSFET10
Width=Wum
Length=L um
Model=cmosp
DC
DC1
DC
VSS
MOSFET_NMOS
MOSFET12
Width=Wum
Length=L um
Model=cmosn
I_Probe
IDS
V_DC
VDD
Vdc=VDD
V_DC
VDD2
Vdc=Vcontrol
VSS
MOSFET_NMOS
MOSFET13
Width=Wum
Length=L um
Model=cmosn
V_DC
VDD1
Vdc=-VDD
Figure 13 ADS simulation of the basic L-C oscillator option 1 using harmonic balance. The OscPort is
used by the harmonic balance simulator, to inject a signal into the circuit to determine the frequency of op-
eration etc. The fundamental oscillating frequency is entered into the harmonic balance simulator and
Oscmode is checked.
Sheet
13 of 18

VSS
VDD
v out2
V_DC
VDD2
Vdc=Vcontrol
BSIM3_Model
cmosn
Xl=-1e-7
Xw=0
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ub1=-7.61e-18
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pv ag=0.1945781
Pscbe2=5e-10
Pscbe1=2.541131e10
Pdiblcb=-0.5
Pdiblc2=9.723614e-4
Pdiblc1=2.091364e-3
Pclm=0.7319137
Drout=0.0428851
Dsub=0.751089
Etab=2.603903e-3
Eta0=0.1178659
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nf actor=1.2410485
Vof f =-0.0850186
B1=5e-6
B0=1.648829e-6
Pags=0.0968
Ags=0.1450882
Wketa=-5.792854e-3
Lketa=-0.0143698
Keta=3.997018e-3
A0=0.9059229
Vsat=1.174604e5
Prwb=-0.0586598
Prwg=0.0182608
Prdsw=-33.9337286
Rdsw=1.28604e3
Delta=0.01
Uc=1.831708e-11
Ub=1.582544e-18
Ua=1e-12
Dv t2=-0.1427458
Dv t1=0.9107896
Dv t0=6.5803089
Nlx=5.28517e-8
W0=1e-5
K3b=1.252205
K3=68.279056
Pk2=9.631217e-3
K2=-0.0316751
K1=0.825917
Pv th0=8.691731e-3
Vth0=0.6701079
U0=433.6065339
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=1.238214e-8
Dwg=-7.483283e-9
Xpart=0.5
Cgbo=2e-9
Cgdo=2.79e-10
Cgso=2.79e-10
Pbswg=0.99
Mjswg=0.1
Cjswg=2.2346e-10
Pbsw=0.99
Pb=0.99
Mjsw=0.1
Cjsw=4.437149e-10
Mj=0.7549569
Cj=5.067009e-4
Tox=1.01e-8
Tnom=27
Wwl=0
Wwn=1
Ww=0
Wln=1
Wl=0
Wint=2.277646e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=1.097132e-7
Js=0
Rsh=2.8
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
NMOS=y es
BSIM3_Model
cmosp
Xl=-1e-7
Xw=0
Noic=1.4e-12
Noib=2.4e3
Noia=9.9e18
Em=4.1e7
Kt2=0.022
Kt1=-0.11
Uc1=-5.6e-11
Ua1=4.31e-9
At=3.3e4
Ute=-1.5
Pv ag=14.4617331
Pscbe2=3.078664e-9
Pscbe1=6.898588e10
Pdiblcb=-0.0209265
Pdiblc2=9.858521e-3
Pdiblc1=1.300053e-5
Drout=7.988149e-4
Dsub=0.3593017
Etab=8.604543e-3
Eta0=0.111002
Cit=0
Cdscd=0
Cdscb=0
Cdsc=2.4e-4
Nf actor=0.8428454
Vof f =-0.0939754
B1=5e-6
B0=4.703171e-6
A1=0
Pags=0.09532
Ags=0.2633783
Wketa=8.895347e-3
Lketa=-9.580923e-3
Keta=4.690296e-3
Vsat=1.57686e5
Prwb=-0.0733682
Prwg=-4.742166e-3
Prdsw=128.4338259
Rdsw=2.552456e3
Delta=0.01
Uc=-5.80218e-11
Ub=9.033053e-19
Ua=1.447557e-9
Dv t2=-0.061438
Dv t1=0.5624229
Dv t0=3.8366128
Nlx=1.867036e-7
W0=1e-5
K3b=-5
K3=96.6543548
Pk2=3.340684e-3
K2=0.0200888
K1=0.3913281
Pvth0=1.949468e-3
Vth0=-0.8017536
U0=183.1171264
Xj=1.5e-7
Vbm=-3.0
Nch=1.7e17
Dwb=9.587665e-9
Dwg=-1.585994e-8
Xpart=0.5
Cgbo=2e-9
Cgdo=2.56e-10
Cgso=2.56e-10
Pbswg=0.8
Mjswg=0.1912128
Cjswg=4.256e-11
Pbsw=0.8
Pb=0.914212
Mjsw=0.1842521
Cjsw=2.002874e-10
Mj=0.4683602
Cj=9.196812e-4
Tox=1.01e-8
Wwl=0
Wwn=1
Wln=1
Wl=0
Wint=2.151118e-7
Lwl=0
Lwn=1
Lw=0
Lln=1
Ll=0
Lint=5.519082e-8
Js=0
Rsh=2.2
Capmod=2
Mobmod=1
Version=3.1
Idsmod=8
PMOS=y es
HarmonicBalance
HB2
Conv Mode=Basic (Fast)
NoiseConMode=yes
Noisecon[1]="NC1"
EquationName[1]=
OscPortName="oscport1"
OscMode=y es
UseKry lov =no
FundOv ersample=4
Order[1]=5
Freq[1]=2.5 GHz
HARMONIC BALANCE
VSS
MOSFET_NMOS
MOSFET11
Width=W um
Length=L um
Model=cmosn
NoiseCon
NC1
NoiseNode[1]=v out2
PhaseNoise=Phase noise spectrum
CarrierIndex[1]=1
NLNoiseDec=1
NLNoiseStop=1 MHz
NLNoiseStart=10 Hz
HB NOISE CONTROLLER
INDQ
L4
Rdc=0.0 Ohm
Mode=proportional to f req
F=2500.0 MHz
Q=80
L=2.0 nH
VSS
MOSFET_NMOS
MOSFET8
Width=W um
Length=L um
Model=cmosn
VSS
MOSFET_NMOS
MOSFET7
Width=W um
Length=L um
Model=cmosn
INDQ
L3
Rdc=0.0 Ohm
Mode=proportional to f req
F=2500.0 MHz
Q=5
L=2.0 nH
INDQ
L5
Rdc=0.0 Ohm
Mode=proportional to f req
F=2500.0 MHz
Q=80
L=2.0 nH
VSS
MOSFET_NMOS
MOSFET10
Width=W um
Length=L um
Model=cmosn
VAR
VAR2
L=0.6
VDD=1.5
Vcontrol=1
W=40
Eqn
Var
MM9_PMOS
MOSFET4
Width=700 um
Length=2.4 um
MM9_PMOS
MOSFET9
Width=700 um
Length=2.4 um
V_DC
VDD
Vdc=VDD
I_Probe
IDS
DC
DC1
DC
I_DC
SRC2
Idc=1100 uA
OscPort
oscport1
MaxLoopGainStep=
FundIndex=1
Steps=10
NumOctav es=2
Z=1.1 Ohm
V=
V_DC
VDD1
Vdc=-VDD
Figure 14 ADS simulation of the basic L-C oscillator option 1 using harmonic balance. The OscPort is
used by the harmonic balance simulator, to inject a signal into the circuit to determine the frequency of op-
eration etc. The fundamental oscillating frequency is entered into the harmonic balance simulator and
Oscmode is checked.
Sheet
14 of 18

m1
harmindex=
dBm(HB.vout2)=10.982
1
1 2 3 4 0 5
-30
-20
-10
0
10
-40
20
harmi ndex
d
B
m
(
H
B
.
v
o
u
t
2
)
m1
harmi ndex
0
1
2
3
4
5
HB.freq
0.0000 Hz
2.531GHz
5.062GHz
7.593GHz
10.12GHz
12.65GHz
100 200 300 400 500 600 700 0 800
-0.5
0.0
0.5
1.0
1.5
-1.0
2.0
ti me, psec
t
s
(
H
B
.
v
o
u
t
2
)
,
V
m2
noisefreq=
pnfm=-75.67 dBc
10.00kHz
1E2 1E3 1E4 1E5 1E1 1E6
-100
-80
-60
-40
-20
-120
0
noi sefreq, Hz
p
n
f
m
,
d
B
c
m2
DC.IDS.i
9.859mA

Figure 15 Resulting plots from the ADS simulation shown in Figure 13. Here the control voltage has been set
to center the VCO on ~ 2.5GHz.
Sheet
15 of 18

m1
harmindex=
dBm(HB.vout2)=5.293
1
1 2 3 4 0 5
-40
-20
0
-60
20
harmi ndex
d
B
m
(
H
B
.
v
o
u
t
2
)
m1
harmi ndex
0
1
2
3
4
5
HB.freq
0.0000 Hz
2.072GHz
4.145GHz
6.217GHz
8.289GHz
10.36GHz
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 1.0
0.4
0.6
0.8
1.0
1.2
1.4
0.2
1.6
ti me, nsec
t
s
(
H
B
.
v
o
u
t
2
)
,
V
m2
noisefreq=
pnfm=-86.32 dBc
10.00kHz
1E2 1E3 1E4 1E5 1E1 1E6
-120
-100
-80
-60
-40
-140
-20
noi sefreq, Hz
p
n
f
m
,
d
B
c
m2
DC.IDS.i
9.859mA

Figure 16 Resulting plots from the ADS simulation shown in Figure 13. Here the control voltage has been set
to 2.5V giving a resulting oscillating frequency of ~ 2.07GHz.
m1
harmindex=
dBm(HB.vout2)=15.327
1
1 2 3 4 0 5
-20
-10
0
10
-30
20
harmi ndex
d
B
m
(
H
B
.
v
o
u
t
2
)
m1
harmi ndex
0
1
2
3
4
5
HB.freq
0.0000 Hz
3.471GHz
6.942GHz
10.41GHz
13.88GHz
17.35GHz
100 200 300 400 500 0 600
-1
0
1
2
-2
3
ti me, psec
t
s
(
H
B
.
v
o
u
t
2
)
,
V
m2
noisefreq=
pnfm=-75.39 dBc
10.00kHz
1E2 1E3 1E4 1E5 1E1 1E6
-100
-80
-60
-40
-20
-120
0
noi sefreq, Hz
p
n
f
m
,
d
B
c
m2
DC.IDS.i
9.859mA

Figure 17 Resulting plots from the ADS simulation shown in Figure 13. Here the control voltage has been set
to 0V giving a resulting oscillating frequency of ~ 3.47GHz.
Sheet
16 of 18

3.7 REDUCING TUNING BANDWIDTH
The previous VCO was designed for maximum band-
width, by directly connecting the varactor to the induc-
tor. If we wish to have a VCO operating over a narrower
bandwidth then we need to swap one of the varactors
with a small value capacitor, such that the varactor ca-
pacitance swing is less dominant. The circuit arrange-
ment for the resonator is shown in Figure 18. The easiest
way to determine the value of the coupling capacitor is to
generate a spreadsheet and enter values of Varactor cou-
pling capacitor as shown in
Table 2 Prediction of VCO tuning bandwidth with the
addition of a coupling capacitor Cc in series with a sin-
gle MOS varactor. In order to achieve a % bandwidth of
~ 10% , the required value of Cc is 0.5pF (This will also
give us some margin). Note the addition of the resonator
coupling capacitor Cc will alter these values slightly and
some adjustments may need to be made to the resonator
to adjust the center frequency back to 2.5GHz.

INDQ
L4
Rdc=0.0 Ohm
Mode=proportional to freq
F=2.5 GHz
Q=5
L=6 nH
V_DC
VDD1
Vdc=Vcontrol
R
R1
R=1 kOhm
C
C1
C=0.5 pF
MM9_PMOS
MOSFET9
_M=Fingers
Width=Wv um
Length=L um
Model=cmosp
Figure 18 Circuit segment of the L-C Vco showing
the modified resonator section. One of the varac-
tors has been replaced with a small value capaci-
tor to dampen the varactor capacitance swing
and thus reducing the VCO tuning bandwith.
Values for the varactor are _M=5, Wv=500 &
L=0.6 giving a predicted capacitance variation of
1.279pF to 4.613pF.
If we re-adjust L to be 5.5nH and Cc set to 0.6pF the
new maximum and minimum VCO frequencies will be
2401MHz and 2657MHz. This will give a center fre-
quency of 2529MHz and a % tuning bandwidth of
10.2%. This value may well need to be increased to al-
low for temperature effects etc.

Table 2 Prediction of VCO tuning bandwidth
with the addition of a coupling capacitor Cc in
series with a single MOS varactor. In order to
achieve a % bandwidth of ~ 10% , the required
value of Cc is 0.5pF
The plots of the narrow bandwidth Vco with Vcontrol set
to 0V and 2.5V are shown in Figure 19 & Figure 20
Cc
pF Max C Min C Min Freq Max Freq
(MHz) (MHz) (MHz/V) (%)
0.1 0.09787821 0.092748 4644 4771 50.68 2.69
0.15 0.14527609 0.134255 3812 3965 61.35 3.94
0.2 0.19168918 0.172955 3318 3494 70.04 5.14
0.25 0.23714785 0.209124 2983 3177 77.45 6.29
0.3 0.28168125 0.243002 2737 2947 83.93 7.38
0.35 0.32531735 0.2748 2547 2772 89.70 8.43
0.4 0.36808298 0.304705 2395 2632 94.92 9.44
0.45 0.41000395 0.33288 2269 2518 99.67 10.41
0.5 0.45110503 0.359472 2163 2423 104.03 11.34
0.55 0.49141003 0.384609 2073 2343 108.06 12.24
0.6 0.53094188 0.408409 1994 2273 111.81 13.10
0.65 0.56972259 0.430975 1925 2213 115.30 13.93
0.7 0.60777339 0.4524 1864 2160 118.58 14.73
0.75 0.64511467 0.47277 1809 2113 121.66 15.51
0.8 0.68176612 0.49216 1760 2071 124.56 16.26
0.95 0.78776739 0.54511 1637 1968 132.36 18.36
0.9 0.75307455 0.52827 1674 1999 129.89 17.68
0.95 0.78776739 0.54511 1637 1968 132.36 18.36
1 0.82184215 0.561211 1603 1939 134.70 19.01
Varactor
Network
Tuning Range
Sheet
17 of 18

m1
harmindex=
dBm(HB.vout1)=16.570
1
1 2 3 4 0 5
-30
-20
-10
0
10
-40
20
harmi ndex
d
B
m
(
H
B
.
v
o
u
t
1
)
m1
harmi ndex
0
1
2
3
4
5
HB.freq
0.0000 Hz
2.657GHz
5.314GHz
7.972GHz
10.63GHz
13.29GHz
100 200 300 400 500 600 700 0 800
-2
-1
0
1
2
-3
3
ti me, psec
t
s
(
H
B
.
v
o
u
t
1
)
,
V
m2
noisefreq=
pnfm=-85.04 dBc
10.00kHz
1E2 1E3 1E4 1E5 1E1 1E6
-120
-100
-80
-60
-40
-140
-20
noi sefreq, Hz
p
n
f
m
,
d
B
c
m2
DC.IDS.i
9.859mA
Narrow bandwidth L-C VCO with Vcontrol set to 0V

Figure 19 Prediction of the narrow band L-C VCO performance at a Vcontrol set to 0V.
m1
harmindex=
dBm(HB.vout1)=15.839
1
1 2 3 4 0 5
-20
-10
0
10
-30
20
harmi ndex
d
B
m
(
H
B
.
v
o
u
t
1
)
m1
harmi ndex
0
1
2
3
4
5
HB.freq
0.0000 Hz
2.401GHz
4.801GHz
7.202GHz
9.602GHz
12.00GHz
100 200 300 400 500 600 700 800 0 900
-1
0
1
2
-2
3
ti me, psec
t
s
(
H
B
.
v
o
u
t
1
)
,
V
m2
noisefreq=
pnfm=-89.58 dBc
10.00kHz
1E2 1E3 1E4 1E5 1E1 1E6
-120
-100
-80
-60
-40
-140
-20
noi sefreq, Hz
p
n
f
m
,
d
B
c
m2
DC.IDS.i
9.859mA
Narrow bandwidth L-C VCO with Vcontrol set to 2.5V

Figure 20 Prediction of the narrow band L-C VCO performance at a Vcontrol set to 2.5V.

Sheet
18 of 18

4 CONCLUSION
This tutorial described the small signal operation of a L-
C oscillator. The relevant design theory was given to-
gether with several worked examples, both fixed fre-
quency and voltage controlled versions.
Harmonic balance ADS simulations were given to simu-
late the circuits, using the hand calculations derived in
the examples to predict, output frequency (and harmon-
ics), output power and phase noise performance.

It was shown that in order to achieve good phase noise
performance the use of low Q on-chip inductors was to
be avoided, opting instead for high Q bond-wire induc-
tors off-chip.

The first VCO was designed for maximum tuning range
by connecting a pair of varactors directly across the in-
ductor. The resulting tuning bandwidth was 55% (ie 2.07
to 3.47GHz), centred on 2.5GHz.

The step by step design of this Vco showed how to de-
sign the resonator and calculate its loaded Q (and hence
determine the VCO phase noise) and its RF loss. With
the knowledge of the loss of the resonator, the gms of
the reflection amplifier devices could be determined to
ensure reliable oscillation (with some margin).

The predicted performance of the wide-band oscillator is
shown in Table 3.

Parameter Predicted
Result
Units
Frequency band-
width
2.07 3.47 GHz
Phase Noise > 75 dBc/Hz @
10KHz
Tuning Bandwidth 55 %
O/P Power >5 dBm
Power Consumption ~ 100 mW
2
nd
Harmonic >10 dBc
Ko ~500 MHz/V
Table 3 Predicted performance of the wide-
band L-C VCO.
The second VCO example was designed to have a
greatly reduced bandwidth (~10%), thus lowering Ko to
around 100MHz/V, giving a tuning range of 2.401GHz
to 2.667GHz centred on 2.532GHz.

The predicted performance of the narrow-band oscillator
is shown in Table 4. In both cases the harmonic content
is quite high and so a buffer stage with a tuned output
will be required to improve this to a more acceptable
20dc or so.

Parameter Predicted
Result
Units
Frequency band-
width
2.401 2.667 GHz
Phase Noise > 83 dBc/Hz @
10KHz
Tuning Bandwidth 10.5 %
O/P Power >15 dBm
Power Consumption ~ 100 mW
2
nd
Harmonic >10 dBc
Ko ~100 MHz/V
Table 4 Predicted performance of the narrow-
band L-C VCO.
5 REFERENCES
[1] Oscillator Design and Simulation, Randall W Rhea,
1995, Noble Publishing, ISBN 1-884932-30-4, p111-
131.

[2] Thomas Lee, The Design of CMOS Radio-
Frequency Integrated circuits, Cambridge University
Press, second edition 2004, ISBN 0-521-835389-9,
p145.

[3] P Andreani & S Mattisson, A 1.8GHz CMOS VCO
Tuned by an Accumulation-Mode MOS Varactor. Com-
petence Center for Circuit Design, Dept of Applied Elec-
tronics, Lund University, Sweden. In Proceedings of
ISCAS 2000, Vol. 1, pp. 315-318, May 2000.

[4] W.Wong, P.Hui, Z.chen, K.Lau, P.Chan, P.Ko, A
Wide Tuning Range Gated Varactor, IEEE Journal of
Solid-State Circuits, Vol. 35, No 5, May 2000.

[5] R. Jacob Baker, H Li, D Boyce, CMOS Circuit De-
sign, Layout and Simulation, Wiley Interscience, 2004,
ISBN 0-471-70055-X.