Designing a Central Processor Unit: The Controller: State Sequencing and Output Logic
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32 f4 f3 select SHIFTER
MPX PC c10
A c7
f2 f1 f0 select A
c13
Controller
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31
24 23
20 19
Opcode
Rdest
Address
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E1 F3
F2
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D2 = C Q2 Q1 + C Q1 Q0 D1 = C Q1 + C Q2 Q0 + Q2 Q1 Q0 D0 = Q2 Q1 Q0 + Q2 Q1 Q0 + C Q2 Q1 Q0
DOC 112: Computer Hardware Lecture 18 Slide 14
Further simplification
We can use the EOR simplification rule: D0 = Q2 Q1 Q0 + Q2 Q1 Q0 + C Q2 Q1 Q0 D0 = Q2 (Q1Q0) + C Q2 Q1 Q0 But, since we have already decoded the states, we will not bother with this
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Further simplification
Instead we can simplify the equations using the decoded states: D2 = CQ2Q1 + CQ1Q0 D1 = CQ1 + CQ2Q0 + F1 D0 = F1 + F2 + CE3
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Start Up
We did not check whether the circuit will be safe at start up, but it is. We will need to add extra hardware to make the processor do something particular at start up, (and maybe also on a signal from a reset button), so the design will be safe in any case.
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Clock Gates
The clock gate signals c0 to c8 determine which register is loaded at each cycle. The MAR will use this typical gating circuit:
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Opcode
Rdest
Rscr
Unused
The register to be clocked is recorded in the IR bits 20-22.The condition for any register (Rdest) to receive a clock edge is: CRdest = E4+ E3(LOAD+ADD+INC+DEC+COMP) + E2(ASL + MOVE + CALL+CALLINDIRECT) + E1CLEAR It cannot be simplified further
DOC 112: Computer Hardware Lecture 18 Slide 25
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The control bits are defined by equations: f4 = ASR+ROR f3 = ASL+ROR 00 is the default function
DOC 112: Computer Hardware Lecture 18 Slide 27
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The PC selector
Last but not least we can get the conditions for the PC selector from the register transfer tables: s3 = F1 + E1(CALL+CALLINDIRECT)
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Improvements
All instructions are 32 bit, but mostly the bottom 16 bits are empty. This means that we are wasting memory space and doing many more fetch cycles than we need. We could pack up the instructions on byte boundaries and introduce some multiplexing hardware to load the IR correctly.
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Other functionality
A circuit to test if the result (or internal bus) was zero would enable us to provide a SKIP_EQUAL instruction. (The software department would be very keen to have this). This would require a 32 bit OR gate and a single bit register.
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More Multiplexers
Additional multiplexers could help us to reduce the instruction cycles of many instructions. For instance a multiplexer to select the input to B independently of A would reduce many three cycle instructions to two cycles.
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In the meantime
Have a great christmas!
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