LIST OF EXPERIMENTS PULSE AND DIGITAL CIRCUITS LAB

1. LINEAR WAVE SHAOING 2. NON LINEAR WAVE SHAPING CLIPPERS 3. NON LINEAR WAVE SHAPING CLAMPERS 4. TRANSISTOR AS A SWITCH 5. STUDY OF LOGIC GATES &SOME APPLICATIONS 6. STUDY OF FLIP FLOPS &SOME APPLICATIONS 7. SAMPLING GATES 8. ASTABLE MULTIVIBRATOR 9. MONOSTABLE MULTIVIBRATOR 10. BISTABLE MULTI VIBRATOR 11. SCHMITT TRIGGER 12. UJT RELAXATION OSCILLATOR

1.LINEAR WAVE SHAPING

Aim : Design a RC LPF and HPF at various time constants and verify the responses for Square wave input (choose C = 0.1Qf, Vi = 4 VP-P, f = 10 K Hz). CRO Signal Generator Bread board Capacitor (0.1Qf) Resistors (100;, 1K;, 10 K;) Connecting wires.

Apparatus: 1. 2. 3. 4. 5. 6.

Circuit Diagram: HPF:

Design / Calculations: a) RC = T Given T = 1/10KHz

= 0.1 mSec

R = 0.1x 10-3 / 0.1Qf = 1 Kohms V1 = V / (1 + e-T/2RC) = 2.49 V V ! 1.51V V1| ! T 1  e 2 RC V V | %tilt ! 1 1 V 2 = (2.49 1.51)/2

= 49%)

T1 = T2 = T/2 b) RC >> T Choose RC = 10T = 1 mSec 10 3 R= ! 10 K; 0.1x10  6 The O/P waveform will be identical to I/P

T1 = T2 = T/2 c) RC << T RC = 0.1 T R= 0.1x10 4 ! 100; 0.1x10 6

LPF:

a) RC = T C = 0.1Qf, R = 1K; V T 2 RC  1 e ! 0.49V 2 V2 ! T e 2 RC  1 V1 = -0.49 V

b) RC >> T R = 10 K;, C = 0.1 Qf

V T 2 RC  1 e ! 0.05V 2 V2 ! T e 2 RC  1

V1= 0.05v

c) RC << T R = 100;, C = 0.1 Qf

Note: Low Pass Filter allows the DC component of I/P signal and High Pass Filter block the DC component of I/P Signal. Procedure: 1. 2. 3. 4. Connect the circuit as shown in figure (LPF / HPF) Apply the Square wave input to this circuit (Vi = 4 VP-P, f = 10KHz) Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T Verify the values with theoretical calculations

Precautions: Use two CRO probes and observe I/P & O/P waveforms simultaneously by putting CRO on DC modes.

Result: LPF and HPF are designed at various time constants and the responses for square wave input is observed & hence plotted.

Questions: 1. When HP-RC circuit is used as Differentiator? 2. Draw the responses of HPF to step, pulse, ramp inputs? 3. Draw the responses of LPF to step, pulse, ramp inputs? 4. Define % tilt and rise time? 5. When LP-RC circuit is used as integrator? 6. Why noise immunity is more in integrator than differentiator? 7. Why HPF blocks the DC signal? 8. Define 1db? 9. What is meant by linear wave shaping? 10. Write the formula for rise time tr?

2.NON-LINEAR WAVE SHAPING CIRCUITS CLIPPERS

Aim: To study the clipping circuits using diodes. To observe the transfer characteristics of all the clipping circuits in CRO. Apparatus: Signal Generator. Bread board Connecting patch cards. CRO DC power supply (dual) Resistors (1 K;, 10K;) Diodes (1N4007) Theory: Clipping circuits basically limit the amplitude of the input signal either below or above certain voltage level. They are referred to as Voltage limiters, Amplitude selectors or Slicers. A clipping circuit is one, in which a small section of input waveform is missing or cut or truncated at the out put section. Clipping circuits are classified based on the position of Diode. 1.Series Diode Clipper 2.Shunt Diode Clipper Procedure: Connect the circuit as shown in fig.1 In each case apply 10 VP-P, 1KHz Sine wave I/P using a signal generator. O/P is taken across the load RL. Observe the O/P waveform on the CRO and compare with I/P waveform. Sketch the I/P as well as O/P waveforms and mark the numerical values. Note the changes in the O/P due to variations in the reference voltage VR = 2V, 3V.. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode. Repeat the above steps for all the circuit. Precautions: Set the CRO O/P channel in DC mode always. Observe the waveform simultaneously by keeping common ground. See that there is no DC component in the I/P. To find transfer characteristics apply input to the X-Channel, O/P to Y-Channel, adjust the dot at the center of the screen when CRO is in X-Y mode. Both the channels must be in ground, then remove ground and plot the transfer characteristics.

Circuit Diagram

Input&Output Wave Forms

Circuit diagram

O/P Wave Forms

Circuit Diagram

O/P Wave Forms

Circuit Diagrams

Transfer Characteristics

Result: Different types of clipping circuits have been studied and observed the responses for various combinations of VR and clipping diodes.

Questions: Define clipping circuit? What are the different types of clippers? What is a break region? Which kind of a clipper is called a slicer circuit? What are the disadvantages of the shunt clipper? What are the disadvantages of the series clipper? What is piecewise linear mode of a diode?

3. NON-LINEAR WAVE SHAPING CIRCUITS CLAMPERS

Aim: To study the clamping circuits using diodes and capacitors. Apparatus: 1. 2. 3. 4. 5. 6. 7. 8. Theory: Clamping circuits add a DC level to an AC signal. A clamper is also refer to as DC restorer or DC re-inserter. The Clampers which clamp the given waveform either above or below the reference level, which are known as positive or negative clamping respectively. Signal Generator. Bread board Connecting patch cards. CRO DC power supply (dual) Resistors ( 100 K; ) Diodes (1N4007) Capacitor (0.1Qf)

Procedure: 1. Connect the circuit as shown in fig.1. 2. Apply a Sine wave of 10VP-P, 1KHz at the input terminals with the help of Signal Generator. 3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark the values with VR = 2 V, 3V 4. O/P is taken across the load RL. 5. Repeat the above steps for all clamping circuits as shown. 6. Waveforms are drawn assuming diode is ideal.

Circuit diagram

I/P & O/P Wave Forms Vi =5V t -5V 0.5V

C1 V1 0.1uF 1N4007GP R1 100kohm

V0 t

10V 7.07V_rms 1000Hz 0Deg

D1

V0 -9.5V

C1 V1 10V 7.07V_rms 1000Hz 0Deg 0.1uF 1N4007GP

D1

R1 100kohm

V0 9.5V V0 5V -0.5V t

C1 0.1uF 1N4007GP D1 R1 100kohm V2 2V

V0 t V0 -1.5V -6.5V -11.5V

10V 7.07V_rms 1000Hz 0Deg

V1

Circuit diagram

O/P Wave forms

Result: Different types of clamping circuits are studied and observed the response for different combinations of VR and diodes.

Questions:
1.What are the applications of clamping circuits? 2.What is the synchronized clamping? 3.Why is a clamper called a dc inserter? 4.What is clamping circuit theorem. How dose the modified clamping Circuit theorem differs from this? 5. Differentiate ve clamping circuit from +ve clamping circuits in the above circuits? 6. Describe the charging and discharging of a capacitor is each circuit? 7. What is the function of capacitor? 8. What are the effects of diode characteristics on the output of the Clamper?

4.TRANSISTOR AS A SWITCH
Aim: Design Transistor to act as a Switch and verify the operation. Choose VCC = 10V, ICmax = 10 mA, hfe = 50, VCESat = 0.2, Vin = 4Vp-p, VBESat = 0.6 V Apparatus: 1. 2. 3. 4. 5. 6. 7. Transistor (BC 107). Breadboard. CRO. Resistors (1K;, 8.2K;). DC power supply. Function Generator. Connecting patch cards.

Theory: When the I/P voltage Vi is negative or zero, transistor is cut-off and no current flows through Rc hence V0 $ VCC when I/P Voltage Vi jumps to positive voltage, transistor will be driven into saturation. Then V0 = Vcc ICRC $ VCESat Design procedure: When Q is ON RC = VCC  VCESat I C max

= (10-0.2) / 10 mA IB uICmax / hfe u 10mA / 50 IB u0.2 mA To keep transistor Ibmin = 0.2mA remain in ON,

= 1K;

IB

should

be

greater

than

Vin = IBRB + VBE Sat 2V = 0.2 mA RB + 0.6V RB = 7 K (choose practical values as 8.2 K)

Circuit diagram:

Procedure: 1. Connect the circuit as shown in figure. 2. Apply the Square wave 4 Vp-p frequency of 1 KHz 3. Observe the waveforms at Collector and Base and plot it. Precautions:

1. When you are measuring O/P waveform at collector and base, keep the CRO in DC mode. 2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2 or 0.5 position. 3. When you are applying the square wave see that there is no DC voltage in that. This can be checked by CRO in either AC or DC mode, there should not be any jumps/distortion in waveform on the screen. Expected waveforms:

Result: Transistor as a switch has been designed and O/P waveforms are observed. Questions: 1. 2. 3. 4. 5. 6. Differentiate between Diode and Transistor as a switch? Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors? Define ON time, OFF time of the transistor? In which regions Transistor acts as a switch? Explain phenomenon of latching in a Transistor switch? Define Rise time & fall time of a transistor switch?

5.STUDY OF LOGIC GATES&SOME APPLICATIONS

Aim: 1) Study of logic gates using ICs & discrete components. 2) Realization of basic gates using NAND & NOR gates (Universal gates). Apparatus: 1. Logic gates (IC) trainer kit. 2. Trainer kit for discrete circuit of gates 3. Connecting patch chords.

I. Verifying the logic gates using ICs: S.NO 1. GATE NAND IC 7400 SYMBOL INPUTS A B 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 0 1 1 1 0 A B 0 0 1 1 Fig (1) 1 0 1 0 1 0 1 0 1 0 1 OUTPUT C 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 0

A B A B

C= A B

2.

NOR IC 7402

C= A  B

3.

AND IC 7408

A B

C=AB

4.

OR IC 7432

A B

C=A+B

5. 6.

NOT IC 7404 EX-OR IC 7486

C= A

REALIZATION OF ALL GATES USING NOR GATE: NOT GATE C=DA

OR GATE

AND GATE A A
AB

NAND GATE

Fig (2.1)

REALIZATION USING NAND GATE:

NOT GATE: A DA

AND GATE: A B AB AB

OR GATE: A DA A+B B DB

NOR GATE: DA A+B A+B

DB

Fig (2.2)

REALIZATION OF BASIC EX-OR GATE USING NAND & NOR GATE: BASIC CONFIGURATION OF EX-OR GATE: A A AB

A B

C= AB  A B

AB

EX-OR USING ONLY NAND GATES: A DA A+B

C ! AB  A B B DB

A+B

EX-OR USING ONLY NOR GATES:

II.Verifying the logic gates using discrete components:

AND GATE: +V(5V) 4.7K; A B C IN4007 IN4007 IN4007

Y=A.B.C

OR GATE:

NOT GATE:

NAND GATE: +V(5V) 4.7K; A IN4007 B IN4007 C IN4007 4.7K; 2.2K; IN4007 IN4007 Y=A.B.C BC547

Procedure:

1. Connect the logic gates as shown in the figure1. 2. Feed the logic signals 0 or 1 from the logic input switches at the inputs A & B. 3. Monitor the output using logic output LED indicators. 4. Repeat step 1 to 3 for NOT, AND, OR & NOR operations. 5. Connect the logic gates as shown in figure 2.1 & 2.2 and repeat the steps 2 through 3. 6. Connect the logic gates as shown in figure 3 and repeat the steps 2 and 3 Verify the truth table for EX OR gate. 7. Implement the logic gates using discrete components (fig 4) and verify the truth tables.

Result: Verified the Truth Tables of all Logic Gates. .

Questions: 1. Why NAND & NOR gates are called universal gates? 2. Realize the EX OR gates using minimum number of NAND gates. 3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates. 4. Realize the given logic function using NAND and also using NOR gates. f ! A BC  A B C  AB C 5. Explain the operation of NAND gate when realized using discrete components. 6. In what regions does the transistor is operated such that it behaves like a Switch. 7. What are the logic low and High levels of TTL ICs and CMOS ICs. 8. Compare TTL logic family with CMOS family. 9. Which logic family is called fastest and which logic family is called low power dissipated. 10. Explain the operation of OR, NOR gates when realized using discrete Components 11. Why the transistor operates as NOT gate.

6.STUDY OF FLIP FLOPS&SOME APPLICATIONS

Aim: To Construct different types of Flip Flops and verify their truth tables. Apparatus: 1. Flip Flop experiment kit 2. Connecting Patch chords.

RS FLIP-FLOP BASIC VERSION: R Q

DQ S Fig (1.a)

TRUTH TABLE FOR RS FLIP FLOP:

Inputs R 0 0 1 1 S 0 1 0 1

Outputs Q Indeterminate 1 0 Q0 (Previous state)

RS FLIP-FLOP CLOCKED VERSION:

S Q CLK

DQ R SYMBOL: R FF CLK DQ S Q Fig (1.b)

TRUTH TABLE FOR CLOCKED RS FLIP FLOP:

Inputs R 0 0 1 1 S 0 1 0 1 CLK

Outputs Q Q0 1 0 Indeterminate state

IC 7476 M/S JK FLIP FLOP; 4 1 16 J

2 SD FF CP 7476 K CD 3 15 14

7 SD FF CP 7476 K CD J 8 Fig (1.c) TRUTH TABLE FOR JK-FLIP FLOP (IC 7476); -

9 6 12

11 10

SD Preset L H L H H H H H

CD Clear

K X X X L L H H X

Clock
H L L H H H H H X X X X X X L H L H X

OUTPUTS Q DQ H L L H H* H* Q0 DQ0 H L L H TOGGLE Q0 DQ0

*Unstable condition. It will not remain after Cn and Pn inputs return to their inactive (high) state

SYMBOL FOR JK FLIP FLOP:

J CLK K FF

Q DQ

SYMBOL FOR D-FLIP FLOP:

D CLK

FF

Q DQ

D-FLIP FLOP USING J-K M/S FLIP FLOP: 2

J CP

SD FF 7476

CLK

DQ CD

3 Fig (1.d)

TRUTH TABLE FOR D-FLIP FLOP (IC 7476): INPUTS Preset L H L H H H Clear H L L H H H L Clock X X X D X X X H L X OUTPUTS Q H L H H L Q0 DQ L H H L H DQ0

SYMBOL FOR T-FLIP FLOP: -

FF

Q DQ

T-FLIP FLOP USING JK FLIP FLOP: 2

T CLK

J CP K

SD FF 7476

DQ CD

3 Fig (1.e)

TRUTH TABLE FOR T-FLIP FLOP: -

INPUTS Preset L H L H H H Clear H L L H H H L Clock X X X T X X X H L X

OUTPUTS Q H L H H DQ L H H L

TOGGLE TOGGLE

Procedure: 1. Construct the RS flip flop as shown in figures 1.a & 1.b. 2. Feed the logic signals from the logic input switches observe the logic outputs on the logic level LED indicators. 3. Verify the corresponding truth tables. 4. Construct JK-flip flop (fig 1.c) and repeat step2 and 3. 5. Construct D Flip flop (fig 1. d) and repeat step 2 and 3. 6. Construct T- Flip flop (fig 1.e) and report step 2 and 3.

Result:

Different types of Flip flops (RS, Clocked RS, JK, D, T) are Constructed using IC 7476 and hence their truth tables are verified.

Questions: 1.Difference between latch and flip-flop. 2.List the applications of flip-flops. 3.Explain the operation of JK master slave flip-flop. 4.What is the difference between SR-flip flop and clocked SR-FF. 5.What is ment by level triggering and edge triggering in flip-flops. 6. Explain the difference between +ve edge and ve edge triggering. 7. Which type of edge triggering is used in IC 7476 J-K M/S Flip-flop? 8. Explain the preset and clear inputs of a flip-flop and why are these Called asynchronous inputs. 9. What is ment by toggle and where do the T-FFs are used. 10. Where do the D-FFs are used and why it is called a delay flip flop. 11. Explain the race around problem in JK-FF and how it is eliminated in master slave JK- FF.

7.SAMPLING GATES
Aim:To study the operation of sampling gates Pre Lab:1. Study the working of sampling gate. 2. Study the data sheet of Diode (1N4007). Apparatus:i) Power supply ii) CRO iii) Diodes iv) Resistors Design Equations:1. WhenVC =5v the four diodes conduct, the gate transmits. 2. when Vc = 0v diodes are cutoff and gate is closed against transmission. 3. The current provided by Vc is approximately Vc/ (RL+RC/2)

Circuit Diagram:-

Vc = 5v/0v D3 1K Rs Vs D4 1k D2 Rc -Vc = 5v/0v RL 1K Vo 1K Rc D1

Procedure:(1) Connect the circuit as shown in the Circuit Diagram. (2) Apply Vs(input) 4v p-p, 1KHz from the function generator to channel one of CRO. (3) Apply control voltage from RPS Vc, -Vc.

(4) When Vc =5v, -Vc=-5v, four diodes conduct input appears across output. (5) When Vc=0v, -Vc = 0v , four diodes are not conducting hence output is zero. (6) Observe the output waveform on channel 2 of CRO.

Output Waveforms:-

Output waveforms of Sampling Gate

Fig : Output waveforms of sampling gates

Result:The Operation of sampling Gate is studied and response is observed.

Reasoning Questions 1. Study the operation of Sampling circuit with 6 Diode Gate.

8.ASTABLE MULTIVIBRATOR
Aim :To design an Astable Multivibrator to generate a Square wave of 1KHz frequency. Choose C = 1nf, 10nf, 100nf. Apparatus : 1. 2. 3. 4. 5.

Regulated DC Power supply CRO, Resistors (1K;, 72K;, 724K;, 7.2K;) Capacitors (0.1nf, 10nf ,100nf) Transistors (BC 107)

1 no 1 no each 2 nos 3 nos 2 nos

Circuit diagram :

Theory: The astable circuit has two quasi-stable states. Without external triggering signal the astable configuration will make successive transitions from one quasi-stable state to the other. The astable circuit is an oscillator. It is also called as free running multivibrator and is used to generate Square Wave. Since it does not require triggering signal, fast switching is possible.

Design :

The period T is given by T = T1 + T2 = 0.69 (R1C1 + R2C2) For symmetrical circuit with R1 = R2 = R & C1 = C2 = C T = 1.38 RC 10-3 = 1.38 x 10-9 x R R R = 724K; (When c=1nf) ; = 10 3 ! 72.4 K; (when c=10nf) 1.38 x10 x10 9 (when c=100nf)

R = 7.24K;

Let VCC = 15V; hfe = 51 (for BC107) VBESat = 0.7V; VCESat = 0.3V Choose ICmax = 10mA, RC = (VCC VCESat) / ICmax = (15 0.3) / (10 x 10-3) = 1.47K; @ RC $ 1K;

Procedure: 1. Connect the circuit as shown in figure. 2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and plot them. Verify the frequencies theoretically.

Expected Waveforms:

Result : An Astable Multivibrator is designed, the waveforms are observed and verified the results theoretically.

Questions: 1. Is it possible to change time period of the waveform with out changing R & C? Support your answer? 2. Collector waveforms are observed with rounded edges. Explain? 3. Explain charging and discharging of capacitors in an Astable Multivibrator? 4. How can an Astable multivibrator be used as VCO? 5. Why do you get overshoots in the Base waveforms? 6. What are the applications of Astable Multivibrator? 7. How can Astable multivibrator be used as a voltage to frequency converter? 8. What is the formula for frequency of oscillations? 9. What are the other names of Astable multivibrator?

9. MONOSTABLE MULTIVIBRATOR Aim : To design a monostable multivibrator for the Pulse width of 0.03mSec. Apparatus: 1. Monostable Multivibrator trainer kit. 2. Function Generator. 3. CRO. 4. Multi-meter. 5. Connecting patch cards.

Circuit diagram :

Theory: The monostable circuit has one permanently stable and one quasi-stable state. In the monostable configuration, a triggering signal is required to induce a transition from the stable state to the quasi-stable state. The circuit remains in its quasi-stable for a time equal to RC time constant of the circuit. It returns from the quasi-stable state to its stable state without any external triggering pulse. It is also called as oneshot a single-cycle, a single step circuit or a univibrator.

Design : To design a monostable multivibrator for the Pulse width of 0.03mSec. Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10K;. T = X ln 2 T = 0.69 RC Choose C = 10nf 0.3 x 10-3Sec = 0.69 x R x 10 x 10-9 R = 43.47 K; V  VCESat RC = CC I C max RC = (15 0.2) / 15mA $ 1K; Minimum requirement of | VB1| e 0.1 1.185 VB1 = V BBR1 VCESat R2  R1  R2 R1  R2 for more margin, given VB1 =

-1.18 =

 15 R1  0.2 R2 ; given R1 = 10K R1  R 2 R2 = 100K

Procedure: 1. Switch ON the trainer kit and observe power indication. 2. Wire the circuit as shown in the circuit diagram. 3. Calculate the pulse width (T) of the Monostable O/P with the selected values of R & C on the CRO. See that CRO is in DC mode. 4. Select the triggering pulse such that the frequency is less than 1/T 5. Apply the triggering input to the circuit and to the CROs channel 1 . Connect the CRO channei-2 to the collector and base of the TransisterQ1&Q2.. 6. Adjust the triggering pulse frequency to get stable pulse on the CRO and now measure the pulse width and verify with the theoretical value. 7. Obtain waveforms at different points like VB1, VB2 , VC1 & VC2. 8. Repeat the experiment for different combinations of R & C (C = 1nf, 100nf). Calculate R for same value of T = 0.3 mSec.

Expected Waveforms:

Result : A collector coupled Monostable Multivinbrator is designed, the waveforms are observed and verified the results theoretically.

Questions:1. 2. 3. 4. 5. 6. 7. 8. What are applications of Monostable Multivibrator? Why is a Monostable Multivibrator called a gating circuit? Explain the waveform of VB1? Describe the operation of the capacitor C3 in the circuit? Why is the time period T also called Delay time? Justify, Why Monostable Multivibrator is called one-shot circuit? Why is the ve voltage given at the base of Q1 transistor. What is the no of quasi & stable states of Monostable Multivibrator

10.BISTABLE MULTIVIBRATOR
Aim: a) Design the Bi-stable Multivibrator circuit and verify the operation. b) Obtain the resolving time of Bi-stable Multivibrator and verify theoretically. Choose R1 = 10K;, C = 0.3Qf, VCE Sat = 0.2V, ICmax = 15mA, VCC = 15V, VBB = 15V, VB1 = -1.2V Apparatus: 6. Bi-stable Multivibrator trainer kit 7. Function Generator 8. CRO 9. Connecting patch chords.

Circuit diagram:

Theory: A Bistable circuit is one which can exist indefinitely in either of two stable states and which can be induced to make an abrupt transition from one state to the other by means of external excitation. The Bistable circuit is also called as Bistable multivibrator, Eccles jordon circuit, Trigger circuit, Scale-of-2 toggle circuit, FlipFlop & Binary. A bistable multivibratior is used in a many digital operations such as counting and the storing of binary information. It is also used in the generation and processing of pulse-type waveform. They can be used to control digital circuits and as frequency dividers . There are two outputs available which are complements of one another. i.e. when one output is high the other is low and vice versa . Design : VCC  VCESat I C max RC = (15 0.2) / 15mA $ 1K; RC = Choose RC = 1K;, -1.2 = fmax =  15 x10  0.2 R2 ; 10  R 2 VB1

V BBR1 VCESat R2  R1  R2 R1  R2

R2 =100K;

10  100 K R1  R2 ! 55KHz = 2 x0.3x10 6 x10 Kx100K 2CR1 R 2

Procedure: 1. Switch ON the system and observe for the power LED indication. 2. Apply two Square waves with same frequency or different frequency at terminals T1 & T2. You may observe symmetrical or Asymmetrical square waves respectively. Observe both I/P & O/P waveforms on CRO. 3. Set the I/P frequency at 500hz. 4. Until you get a 500Hz at the O/P, increase the trigger I/P amplitude, note down the I/P amplitude, this is the minimum pulse step required for trigger the bi-stable Multivibrator with the given circuit parameters. 5. Now slowly increase the frequency and at one particular frequency the circuit does not respond and the output disappears. Just lesser than this frequency, the circuit again responds, this is the maximum allowable frequency. 6. Sketch the O/P waveforms. Sample O/P waveforms are as shown in figure. Result: Bistable Multivibrator circuit is designed and output waveforms are observed.

Expected waveforms: Vt Trigger Input

V02(v)

VCC 0

VCE sat t

V01(v)

VCC

VCE sat 0

Questions: 1. What are the applications of a Bitable multivibrator? 2. Describe the operation of commutating capacitors? 3. Why is a Binary also called a flip-flop? 4. Mention the name of different kinds of triggering used in the circuit shown? 5. What are the disadvantages of direct coupled Binary? 6. How many types of unsymmetrical triggering are there? 7. What are catching diodes? 8. Which triggering is used in binary counting circuits?

11.SCHMITT TRIGGER
Aim:(a) (b) (c) Apparatus:(1) (2) (3) (4) (5) Circuit diagram Schmitt Trigger Circuit board Function Generator Multimeter C.R.O Connecting patch chords. To design the circuit of Schmitt trigger with UTP = 3V LTP = 1.5V ,Vcc = 15V ,Rs = 1k,Rc2 = 3k,R1 = 15k R2 = 4.7k To Obtain the UTP and LTP values Practically and verify it theoretically To obtain square wave from the sine wave.

Procedure:(1) (2) (3) (4) (5) (6) Switch ON the trainer Connect the circuit as shown in Fig. With Vi = 0V, measure the output voltage. Slowly increase the input voltage from 0V to maximum and observe the output for the transition. Obtain the voltage at which the LOW to HIGH transition is occurred and this is the UTP and now measure the input voltage. Now, slowly decrease the input voltage and observe for the HIGH to LOW transition at the output, the input voltage at this point is called the LTP. Apply a sine wave input to the circuit. Observe the input and output waveforms on CRO. Vary the input frequency and comment on the results obtained. Repeat the experiment with different R2. Verify the result theoretically.

(7) (8) (9) (10) (11)

Observations:With Re = 480ohms DC UTP = 2.9V LTP = 1.8V VH = UTP LTP Theoretical Calculations:V1 calculation: VBE2 = 0.6V for Si Vr1 = 0.5V (=VBE at cut in) VCC R2 ; V = RC1  R1  R2 VEN = (V - VBE2) * AC UTP = 3V LTP = 2V VH = UTP LTP

Rb =

R2 ( RC1  R1 ) RC1  R1  R2

VCC = 12V

Re (hFE  1) Rb  Re (hFE  1) (Accurate value)

V1 = VEN + Vr1

V1 = V - 0.1 v (approximate value) V2 calculation: a = R2 R1  R2 ; 1 ); hFE Re ' Rs / hFE (V - Vr2 ) a R  Re ' Re (V Vr2) aR  Re VBE = 0.6V Vr = 0.5V (approximately) R = RC1 ( R1  R2 ) ; RC1  R1  R2

Re = Re(1+

V2 = VBE1 +

(or) V2 = VBE1 +

Expected Waveforms:

Questions: 1. What are the applications of Schmitt Trigger? 2. Define hysteresis action? 3. Why is Schmitt Trigger called a squaring circuit? 4. What is UTP? 5. What is LTP? 6. What is the difference between a Binary and Schmitt Trigger?

12.UJT RELAXATION OSCILLATOR

Aim:
To verify the astable operation by using UJT. Pre Lab:1. Study the working of UJT as a relaxation oscillator. 2. Study the data sheet of 2N 2626 UJT. Apparatus:1) 2) 3) 4) 5) 6) 7) Theory:The unijunction transistor is a current controlled negative resistance device. Its V-I characteristics is a multi valued function of current. It is mostly used as a relaxation oscillator. It can be operated in astable, monostable and bistable configurations. The construction of the UJT is shown and it consists of high resistively n type silicon bar called the base B to which to ohmic constants B1 and B2 are attached at the opposite ends. A very thin aluminum wire called the emitter E is alloyed to the base to form a p-n rectifying junction. Because of this construction, the device was originally described as the double base diode but not it is commercially available as a unijunction as a unijunction transistor. The most useful features of UJT are its stable firing voltage VP, the low firing current, the stable negative resistance characteristics and the high pulse current capability. Procedure:1) Connect the circuit as per circuit diagram 2) Observe the wave form a. Across the capacitor b. AT B1 terminal of UJT c. At B2 terminal of UJT. Observation Table: X Theoretical Practical T1 3.15msec 2.5msec T2 42.6 sec 200 sec Bread Board Capacitor- 0.1 F Resistors 33k - 1No, 560 - 1No, 1k CRO CRO connecting probes DC Power Supply UJT 2N26L16

- 1No

Circuit Diagram:-

Calculations: VBB  VV VBB  VP V T2 = Rb1 C In P VV Post Lab:T1 = RC In 1. Draw the waveform for trigger input at base 2 of the UJT & the Out put sweep voltage wave form at emitter E.

Result:Hence the astable operation by using UJT is verified.