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Department of Electronics-Univ.

of Pavia

STMicroelectronics

GmC Filters Tutorial

Giacomino Bollati TPA R&D 12 May 2004

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 1

Department of Electronics-Univ. of Pavia

STMicroelectronics

Outline
Transfer function: biquad cascade MATLAB lter design GmC implementation MATLAB GmC biquad design GmC zeros realization Transistor level lter design: - biquad design - gm control design Filter characterization Second order effects

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 2

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transfer function: biquad cascade


For a given mask lter it is possible to nd several pole-zero constellations able to t the requirements. The rst step to design a lter is to choose the pole-zero constellation. Usually, it is possible to choose the pole-zero constellation taking it from a standard sets (Butterworth, Bessel, etc.). For each order of the lter (order = number of poles N) these sets give the pole values: N/2 couples of complex conjugated pole for even order lters, odd order lters have also a real pole. It is possible to satisfy each kind of lter mask through the cascade of rst and second order (biquad) structures. This approach compared to the ladder lters has the advantage that the lter is not a single big structure but the cascade of simple blocks.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

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Department of Electronics-Univ. of Pavia

STMicroelectronics

MATLAB lter design


Second order transfer function:
( s z1 ) ( s z2 ) 1+ms+ns G ( s ) = k -------------------------------------- = k ------------------------------------------2 ( s p1 ) ( s p2 ) 1+as+bs
2

The above function has 2 poles and 2 zeros. Standard lters (Butterworth, Bessel, etc.) dont have zeros (than m=n=0) and the transfer function can be rewritten in terms of o and Q:
k G ( s ) = ----------------------------------------2 s s 1 + --------------- + --------o Q o 2

The lter transfer function can be represented as the product of second order structures:
H ( s ) = G1 ( s ) G2 ( s ) Gn ( s )

A MATLAB model is useful to choose the best transfer function and to choose the sequence of the biquad cell in the cascade.
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 4

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC Implementation 1/5


Biquad:

Vin

+ gm1 -

+ gm2 -

+ gm3 -

+ gm4 +

Vout C1 C2

Transfer function:
gm1 ---------Vout gm4 ----------- = ------------------------------------------------------------------------------------Vin gm3 C 1 C1 C2 2 1 + s ------------------------- + s ------------------------gm2 gm4 gm2 gm4

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

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Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC Implementation 2/5


gm1 ---------gm4 k G ( s ) = -------------------------------------------------------------------------- = ------------------------------------------------------------------------------------2 gm3 C 1 C1 C2 s s 2 1 + -------------------------------- + ------------------------1 + s ------------------------- + s ------------------------( c o ) Q ( c o ) 2 gm2 gm4 gm2 gm4 From the above equation it is possible to describe the biquad parameters k, o and Q in terms of the gm and C parameters:
Q = gm2 gm4 C 2 ------------------------- -----2 C1 gm3

1 gm2 gm4 o = ------ ------------------------c C1 C2 gm1 k = ---------gm4

Design problem: 3 equations, 6 variables -> innite solutions.


Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 9

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC Implementation 3/5


Good design rules of thumb: 1- minimize the range of capacitor value used, 2- minimize the range of gm values used. Severe constraints on the mask lter forces the use of high order lters having wide ranges for the o and Q values increasing the ranges of gm and C. For a given mask it is important to nd the transfer function having: the lower order, and/or the minimum range of o and Q, and/or the minimum absolute values of the highest o and Q.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 10

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC Implementation 4/5


Golden parameter set of gm and C should be found through an iterative procedure. Given o, Q and k, it is possible to x some starting conditions, for example: C1=C2, gm2=gm4 Thus, from the expression for Q it is possible to nd gm3=gm4/Q, while from the expression for k it is possible to nd gm1=k*gm4 the expression for o gives the ratio (gm4/C1)/c. The absolute values of the parameters must be chosen according to 2 main constraints: 1- The higher the C values are the lower the noise lter will be (noise lter proportional to KT/C) 2- The higher the C values are the higher the gm values must be, hence, the higher the power consumption will be. C values should be as small as possible but sufcient to satisfy the noise requirements. Other requirements can force us to use capacitors bigger than the minimum required for noise. One of these requirements can be the transfer function accuracy. At this point a set of parameters has been found. The range of C values is the minimum (C1=C2) but gm4/gm3 has a range as wide as the Q value. It is possible to reduce this range increasing the C range.
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 11

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC Implementation 5/5


Example: 1=1.603, Q1=0.805; 2=1.430, Q2=0.522; fc=100MHz, k1=k2=1 BQD1 C1=C2, gm2=gm4, gm1=gm4, gm3=gm4/Q1 Lets choose C1=1pF, gm4 = 1*2**fc*C1 = 1mA/V, gm3=1.24mA/V BQD2 C1=C2, gm2=gm4, gm1=gm4, gm3=gm4/Q2 Lets choose C1=1pF, gm1=gm2=gm4=2*2**fc*C1=0.9mA/V, gm3=1.7mA/V gm3/gm4=1.89 BQD1 gm range is very good. BQD2 gm range can be reduced increasing C range. Lets redesign the cell. C2=0.7*C1, gm2=gm4, gm1=gm4, gm3=gm4/Q2 Lets choose C1=1.3pF, C2=0.91pF , gm1=gm2=gm4=2*2**fc*sqrt(C1*C2)=0.98mA/V gm3=gm4/Q2*sqrt(C2/C1)=1.57mA/V gm3/gm4=1.60
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 12

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC zeros realization 1/2


Biquad:

Vin

+ gm1 -

+ gm2 -

+ gm3 -

+ gm4 +

Ik
Vout C1 C2

Transfer function:

s C1 gm1 ---------- Vin Ik ------------------------gm4 gm2 gm4 Vout = ------------------------------------------------------------------------------------gm3 C 1 C1 C2 2 1 + s ------------------------- + s ------------------------gm2 gm4 gm2 gm4 GmC Filters Tutorial Page 14

Giacomino Bollati, 12 May 2004

Department of Electronics-Univ. of Pavia

STMicroelectronics

GmC zeros realization 2/2


Case 1: Ik = gmk*Vin
s C1 gm1 gmk gm1 gmk ------------------------- Vin ---------- 1 s C 1 ------------------------- Vin --------- gm4 gm2 gm1 gm4 gm2 gm4 Vout = ------------------------------------------------------------------------------------- = -------------------------------------------------------------------------------------gm3 C 1 C1 C2 gm3 C 1 2 2 C1 C2 ------------------------- + s ------------------------------------------------- + s ------------------------1+s 1+s gm2 gm4 gm2 gm4 gm2 gm4 gm2 gm4

Case 2: Ik = s*Ck
2 s C k C 1 gm1 ---------------------------- Vin ---------2 C1 Ck gm1 gm4 gm2 gm4 ---------- 1 s ------------------------- Vin gm4 gm2 gm1 Vout = ------------------------------------------------------------------------------------- = ------------------------------------------------------------------------------------gm3 C 1 gm3 C 1 2 C1 C2 2 C1 C2 1 + s ------------------------- + s ------------------------1 + s ------------------------- + s ------------------------gm2 gm4 gm2 gm4 gm2 gm4 gm2 gm4

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 15

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level, lter design: biquad design 1/7


CMOS transconductor: differential pair.

2*Ibias

W Iout Ibias gm = ---------- = Cox ---- ( V GS V TH ) = ------------------------------------------ = L Vin 2 ( V GS V TH )

W 2 Cox ---- Ibias L

Linearity of the stage is proportional to the voltage overdrive of the MOS Vod=(VGS-VTH). For a given gm, Ibias is proportional to the voltage overdrive of the MOS. Voltage overdrive should be chosen to be as small as possible but sufcient to achieve the required linearity.
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 16

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: biquad design 2/7


Gm scaling The 4 transconductors building a biquad have in general different gm values. Starting from a reference transconductor with given W1, L1 and Ibias1 it is possible to change the gm value in several ways. Lets suppose we want to achieve a gm2=k*gm1: It is possible: 1- Acting on Ibias only. Ibias2=k2*Ibias1. In this case Vod2=k*Vod1 2- Acting on the size only. W2/L2=k2*W1/L1. In this case Vod2=1/k*Vod1 3- Acting on the size and Ibias at the same time in order to keep Vod2=Vod1: Ibias2=k*Ibias1, W2/L2=k*W1/L1. Solution 3 is the preferred for several reasons: 1- MOS quadratic law is only an approximation valid only for small Vod in deep scaled technology. This makes it difcult to nd the exact value of W/L or Ibias to achieve the target gm. 2- Using the rst 2 methods Vod each transconductor has a different Vod, than it has different linearity.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 17

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: biquad design 3/7


Gm scaling
gm1 gm2

Wp1/Lp1

Wp1/Lp1 W1/L1 Ibias 2*Ibias W1/L1

Wp1/Lp1

Wp2/Lp1 W2/L1 W2/L1

Wp2/Lp1

Wn1/Ln1

Wn1/Ln1

Wn2/Ln1

If gm2 = k * gm1 than Wn2 = k * Wn1 W2 = k * W1 Wp2 = k * Wp1

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 18

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: biquad design 4/7


Common mode

Vin

+ gm1 -

+ gm2 -

+ gm3 -

+ gm4 +

Vout C1 C2

Transconductor output nodes need a loop to x the voltage common mode value. Theoretically 4 common mode loops are required (one for each transconductor). In a biquad (gm1, gm4) and (gm2, gm3) have the output nodes connected together, so, only 2 common mode loops are necessary.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

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Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: biquad design 5/7


Common mode
OPAMP

+ VREF

A possible common mode loop can be implemented sensing the output common mode voltage through 2 high value resistor and adjust the PMOS current in order to hold the proper common mode voltage. Common loop bandwidth doesnt need to be very high helping the stability of the loop.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 20

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: gm control design 6/7


The frequency accuracy of the lter is very poor if the transconductor is biased open loop: process, voltage supply and temperature spreads have a direct effect on the values of gm and/or C. Unless closed loop solutions are used the frequency cutoff variation can be as big as +/-50% making the lter useless for most of the applications. Almost every gmC lter has a gm control loop to adjust the gm values in order to improve the accuracy of the lter. According to the precision expected for the lter 2 main approaches are used: 1- Control the transconductor to match the gm value to an absolute reference (for example an external resistor). 2- Control the transconductor to match the gm value to the C value (the reference can be for example a switched capacitor resistor). With the rst approach the precision of the lter is comparable to the precision of the integrated capacitors used in the lter (5-10%). With the second approach the precision of the lter can further improve to few percent.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 21

Department of Electronics-Univ. of Pavia

STMicroelectronics

Transistor level lter design: gm control design 7/7

Iref

gm stage

Vref

to the lter

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 22

Department of Electronics-Univ. of Pavia

STMicroelectronics

Filter characterization
Eldo simulator allows a complete analysis of the lter. Frequency domain analysis: Small-signal frequency response: amplitude, phase, group delay and noise. Time domain analysis Transient simulations -> linearity. Eldo allows the implementation of ideal functions making easy the comparison between the transistor level implementation and the target function. The ideal function can be described in a text le included in the simulation through the following syntax: fnscellname input_node output_node numerator, denominator Numerator and denominator are described with similar syntax of matlab: p(x) = x^3 -2*x - 5 -> -5 -2 0 1 (note that the order of the coefcient is the opposite of MATLAB) Example: fnsbq1 in out1_ideal k1, 1 {1/(Q1*w1*wc)} {1/(w1*wc*w1*wc)} fnsbq2 out1_ideal out2_ideal k2, 1 {1/(Q2*w2*wc)} {1/(w2*wc*w2*wc)}
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 23

Department of Electronics-Univ. of Pavia

STMicroelectronics

Linearity
A single tone input applied to a real lter produces at the output a signal having a dominant tone at a frequency multiple of the input frequency having superimposed tones at frequencies integer multiple of the fundamental. Vin = a*sin(t) Vout = A*sin(t) + B*sin(2t) + C*sin(3t) + D*sin(4t) In differential circuit even harmonics are usually negligible respect to the even ones. A way to quantify mathematically the linearity is to introduce the Total Harmonic Distortion dened as:
THD = 20 log

Hi ------- H 1

Usually the dominant contributor to THD is the third harmonic.

Giacomino Bollati, 12 May 2004

GmC Filters Tutorial

Page 24

Department of Electronics-Univ. of Pavia

STMicroelectronics

Second Order effects


Finite output impedance Output resistance of the transconductor and of the PMOS current sources are not innite. The effect of these resistances can be taken into account as conductances in parallel to C1 and C2:
gm1 ---------gm4 G ( s ) = ----------------------------------------------------------------------------------------------------------------------------------------------------gm3 ( C 1 + G 1 s ) ( C 1 + G1 s ) ( C 2 + G2 s ) 2 1 + s ----------------------------------------------- + s -------------------------------------------------------------------gm2 gm4 gm2 gm4 gm1 ---------gm4 G ( s ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------gm3 C 1 + G 2 C 1 + G 1 C 2 C1 C2 G1 G2 2 1 + ------------------------- + s ------------------------------------------------------------------------- + s ------------------------gm2 gm4 gm2 gm4 gm2 gm4

DC gain decreases to gm1/gm4*1/(1+G1*G2/(gm2*gm4))). Q decreases to:


Q = C2 gm2 gm4 ---------------------------------------------------------- -----C 2 2 C 1 gm3 + G 2 + G 1 ------ C 1 GmC Filters Tutorial Page 26

Giacomino Bollati, 12 May 2004

Department of Electronics-Univ. of Pavia

STMicroelectronics

Second Order effects


Parasitic capacitances

CGDp CGDn

CDBp CDBn

CGSn

CGATE = CGSn + CGDn * ( 1 - Vd / Vg ) + Cmetal CDRAIN = CGDp + CDBp + CDBn + CDGn * ( 1 - Vg / Vd ) + Cmetal The Miller effect makes difcult the estimation of the term due to the nMOS Gate-Drain capacitance. Parasitic capacitances are constituted by junction caps (CDB), oxide caps (CGS, CGD) and metal caps: the main contributors are the oxide capacitances.
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 27

Department of Electronics-Univ. of Pavia

STMicroelectronics

Second Order effects reduction


Finite output resistance can be increased by cascoding the transconductors and/or the pMOS current generators. Usually cascodes improves also the parasitic capacitances because cascode transistors can be sized with L shorter than the transconductor and pMOS driver (in fact, cascode transistors dont affect transconductance precision and offset). Moreover, in cascoded transconductors gate-drain capacitance is not multiplied for Miller effect making easier the parasitic capacitance estimation of each node. High speed lters have small load capacitors and big transistors (fc is proportional to gm/C). Parasitic capacitance can be a signicant percentage of the total capacitance (30%-40%). Design procedure should add the constraint of having similar percentage of parasitic cap on each node: it is better to have 30% on each node than 30% on some nodes and 5% on other nodes. Parasitic caps are due to different contributions (oxide, junction, metal): it is better to have on each node similar percentage for each kind of capacitance (ex.: 20% oxide, 5% junction, 2% metal). The dominant parasitic capacitance is due to the oxide capacitances (CGS and CGD) of the transconductor devices. If the load capacitance is made by using gate oxide capacitance (polynwell capacitance) it is possible to consider oxide parasitic caps as part of the load capacitors because their dependence on process and temperature is the same of the load cap.
Giacomino Bollati, 12 May 2004 GmC Filters Tutorial Page 28

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