Praveer Saxena* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No.

10, Issue No. 1, 019 - 025

DESIGN OF 1-BIT FULL ADDER FOR LOW POWER APPLICATIONS

Praveer Saxena*
Department of ECE A.I. M.T. Greater Noida, India praveer82@gmail.com Department of ECE J. S. S. A. T. E. Noida, India dinesshc@gmail.com

Dinesh Chandra

Department of ECE J. S. S. A. T. E. Noida, India sampath_sams@yahoo.com

Sampath Kumar V

Keywords- adiabatic, energy recovery, low power, full adder.

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I. INTRODUCTION
ISSN: 2230-7818

Abstract An adder is an important element of all the arithmetic and logic units. The recent trends in VLSI are moving towards the need of the devices, which consume low power. The logic circuits based on adiabatic logic are potential candidates for low power applications. In this paper, we have designed a 1-bit full adder using several existing adiabatic logic styles: 1n1p split level pulse adiabatic logic, 1n1p quasi adiabatic logic, and Glitch free and cascadable adiabatic logic. The full adders are designed using 180nm technology parameters provided by predictive technology and simulated using HSPICE. The full adders designed are compared on the basis of transistor counts to implement the full adder, propagation delay and the average power consumed by them for different values of load capacitance and input frequency. The results are also compared with full adder designed with static CMOS. It is observed that, full adders designed with adiabatic logic styles consume very low power in comparison to full adder designed with static CMOS logic. It is observed that, saving in power comes at the expense of increased propagation delay. Under certain operating conditions, one of adiabatic designs of full adder achieves upto 89% power saving in comparison to the full adder designed with static CMOS logic.

II.

A. Conventional Charging The major factor of power dissipation in a conventional CMOS device is the dynamic power. It is the power, dissipated in charging and discharging the capacitive nodes within the circuit. To charge the node capacitance, CL from a dc supply of potential VDD, energy E = CLVDD2 is withdrawn from supply. Only half of this energy is temporarily stored in capacitor (CL). The remaining 0.5CLVDD2 is dissipated as heat in the on resistance of PMOS. When input becomes logic high, the NMOS turns on and energy stored on capacitor CL is discharged to the ground and dissipated as heat. Hence during a complete charge - discharge cycle, the energy E = CLVDD2 is withdrawn from power supply and is dissipated as heat. Half of this energy is dissipated during charging and half is dissipated during discharging. B. Adiabatic Charging In conventional CMOS logic, the potential across the switching device is high due to abrupt application of supply VDD. The energy dissipation during charging and discharging can be minimized to a great effect by ensuring that the potential across switching device is kept sufficiently small. Adiabatic charging may be achieved by charging the capacitor from a time varying source that starts at 0V. This time varying source rises towards V at a slow rate that ensures that potential across switching device is kept arbitrarily small. The adiabatic charging is shown in figure 1.

The energy saving is emerging as a major topic of research. The need of portability and at the same time multifunctionality requires the devices, which consume minimum power. The static CMOS has been a good choice due to its low power dissipation and small fabrication space. The logic circuits based on static CMOS still consumes significant amount of power. The main source of power dissipation in CMOS is dynamic power. Adiabatic logic is an excellent approach to reduce dynamic power. Adiabatic logic minimizes the energy dissipation by minimizing the dissipation across resistances of conducting MOSFETs and recovering the part of energy given to the output, back to the source. Different authors have given different adiabatic logic styles in their research work. [1], [5], [6], [7], [8], [9], [10].

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In this paper, we have designed the 1-bit full adder using 1n1p spilt level pulse adiabatic logic, 1n1p quasi adiabatic logic and Glitch free and cascadable adiabatic logic. The full adders designed with different adiabatic logic styles are compared on the basis of transistor count to implement them, the propagation delay and average power consumption with different values of load capacitance and input frequencies.
CONVENTIONAL AND ADIABATIC CHARGING

Figure 1. Adiabatic Charging

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In fact the energy dissipated across the resistance, R Ediss = I2RT = (RC/T) CVDD2 (1)

It has basically two drawbacks; (1) It is not suitable for pipelining, (2) Its driver is difficult to design [7]. B. 1n1p Quasi Adiabatic Logic The next adiabatic logic is 1n1p quasi adiabatic logic [7], [8]. Basically, it is similar to conventional CMOS except, it includes a sinusoidal power clock instead of dc power supply. By implementing 1n1p quasi adiabatic logic, it is possible to achieve quasi adiabatic operations with conventional static CMOS gates under one phase driving. If driver is varied sufficiently slowly, dissipation occurs only during charging and discharging of load capacitor [7]. The sources of power dissipation in 1N1P quasi adiabatic logic are threshold voltage of MOSFET and energy dissipated in NMOS and PMOS resistance while charging and discharging of load capacitance. The use of slowly varying power clocks ensures the small energy dissipation across the ON resistance of MOS devices. If threshold voltages of NMOS and PMOS are equal in magnitude, the minimum energy dissipated throughout a 0-1-0 cycle is CVt2 [7]. The schematic of an inverter using this logic family along with resulting waveforms after simulation is shown in figure 3.

From the above equation (1), we can see that if T >> RC, the energy dissipation during charging Ediss 0. Same is applicable during discharge process. In addition to this, in some adiabatic logics, the energy dissipation also occurs due to threshold voltage of MOSFET and diode cut-in voltage. The energy dissipation due to threshold voltage Vt is E = 0.5CVt2 (2)

The energy dissipation due to diode cut-in voltage Vd is E = CLVd Vs Where, Vs is the voltage swing. III. ADIABATIC LOGIC STYLES Several adiabatic logic styles have been reported by different authors in their research work. Different adiabatic logic styles contain different number of transistors and different number of power clocks. In this section we will study different adiabatic logic styles, which are derived from static CMOS, without large change: 1n1p split-level pulse adiabatic logic, 1n1p quasi adiabatic logic and Glitch free & cascadable adiabatic logic. (3)

IJ A
ISSN: 2230-7818

A. 1n1p Split-Level Pulse Adiabatic Logic The first adiabatic logic family that we are going to discuss is 1n1p split-level pulse adiabatic logic [5], [7], [9]. It comprises a conventional CMOS gate with two complimentary split-level pulse voltages. The peak voltage of each clock supplies VDD/2 to the gates. In this logic family, the dissipation occurs solely from a finite rate of change of driving voltage and can be decreased to any desired level [7].

The schematic of an inverter using 1N1P split-level pulse adiabatic logic along with waveforms obtained from simulation is shown in figure 2.

Figure 2. Schematic of 1n1p split Inverter and waveforms obtained from simulation .

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Figure 3. Schematic of 1n1p quasi Inverter and waveforms obtained from simulation.

The problem associated with it is, not suitability for pipelining. C. Glitch Free and Cascadable Adiabatic Logic The next adiabatic logic style is Glitch free and cascadable adiabatic logic [6]. It uses a single triangular waveform as power clock and employs rectifying diodes in charging path as well as discharging path, so that ripples does not occur and it becomes suitable for cascadable operations. We have used MOSFET as diode by shorting gate and drain of MOSFET together. The sources of power dissipation in GFCAL logic family are threshold voltage of MOSFET, diode cut-in voltage and dissipation in resistance offered by the pmos and nmos network while charging and discharging of load capacitance respectively. The use of slowly varying power clocks ensures the small energy dissipation across the ON resistance of MOS

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devices. The schematic of an inverter using this logic family and along with resulting waveforms after simulation is shown in figure 4.

Figure 6.Simulation result of full adder using 1n1p split-level pulse adiabatic logic.

Figure 4. Schematic of GFCAL Inverter and waveforms obtained from simulation.

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ISSN: 2230-7818

A. Design of 1-Bit Full Adder using 1n1p Split Level Pulse Adiabatic Logic The schematics to realize the Carry and Sum functions of a full adder are shown in figure 5.The waveforms resulting from simulation are shown in figure 6.

Figure 5. Schematics of Carry and Sum using 1n1p split level pulse adiabatic logic. Figure 8. Simulation result of full adder using 1n1p quasi.

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IV. DESIGN AND SIMULATION OF 1 BIT FULL ADDER In this section we have designed and simulated a 1-bit full adder using 1n1p split, 1n1p quasi, and GFCAL. The full adders are designed using 180nm technology parameters provided by predictive technology at 1.8V and simulated using HSPICE. The length and width of MOSFETs are as follows: L=180nm and W=720nm. The body terminal of NMOS and PMOS are connected to GROUND and VDD = 1.8V respectively. The operating temperature is selected to be 25C and frequencies for three inputs of full adder, A, B and C are 25MHZ, 12.5MHZ and 8.33MHZ respectively. The power clock frequency is chosen to be 100 MHZ.

B. Design of 1-Bit Full Adder using 1n1p Quasi Adiabatic Logic The schematics to realize the Carry and Sum functions of a full adder and the simulation results are shown in figure 7 and figure 8 respectively.

Figure 7. Schematics of Carry and Sum using 1n1p quasi adiabatic logic.

From the simulation results, we can observe the presence of ripples in the output waveforms.

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From the figure 8, we can observe that, we are getting ripples in the output when, the output is logic high. The output is ripple free when it is in logic low state, due to direct shorting of output node to ground when, the pull down network is conducting. C. Design of 1-Bit Full Adder using GFCAL The schematics to realize the Carry and Sum functions of a full adder are shown in figure 9. The waveforms resulting from simulation are shown in figure 10.

Figure 11. Schematics of Carry and Sum using Static CMOS.

Figure 9. Schematics of Carry and Sum using GFCAL.

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Figure 10. Simulation Result of full adder suing GFCAL.

We can observe from the simulation results, GFCAL based full adder does have significant propagation delay due to the use of single triangular power clock. In this case, the propagation delay depends on time period of power clock. D. Design of 1-Bit Full Adder using Static CMOS The schematics to realize the Carry and Sum functions of a full adder are shown in figure 11. The waveforms resulting from simulation are shown in figure 12.

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1n1p Split 1n1p Quasi GFCAL Static CMOS

Figure 12. Simulation Result of full adder suing Static CMOS.

V. COMPARITIVE ANALYSIS OF FULL ADDERS In this section, we have compared the full adders designed with 1n1p spilt, 1n1p quasi and GFCAL. These full adders are also compared with full adder designed with static CMOS. We have compared them on the basis of transistor counts to implement the full adder, propagation delay and variation in average power consumed by them for different values of load capacitance and input frequencies. A. Comparison on the basis of Transistor Counts The number of transistors used to implement the 1-bit full adder using 1n1p spilt, 1n1p quasi, GFCAL and static CMOS is shown in Table I.
Table I. The Transistor count to implement Full Adder Logic Family Used ransistor Count 28 28 32 28

ISSN: 2230-7818

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We know that, the 1n1p split-level pulse adiabatic logic and 1n1p quasi adiabatic logic are directly derived from static CMOS, the transistor count to implement the full adder using 1n1p split and 1n1p quasi are same as the required for static CMOS. The GFCAL includes two extra diodes to control the charge flow in schematic of carry and two extra diodes in schematic of sum. Table III. Variation of Average Power Consumption with Load Capacitance Load Capacitance CL ( fF) 10 30 50 70 90 110 130 150 170 190 Average Power Consumption in micro watts
1n1p Split 1n1p Quasi GFCAL Static CMOS

B. Comparison on the basis of Propagation Delay The circuits based on adiabatic logic offer excellent power saving in comparison to static CMOS. The drawbacks associated with the adiabatic logics are: decreased operating speed and increased fabrication space. In this section, we have compared the propagation delay exhibit by full adders designed with different logic families to compute the output Carry. Here we have kept power clock frequency to be at 100 MHZ, CL at 10femto farad and input frequencies are kept at 25MHZ, 12.5MHZ and 8.33MHZ for three inputs of full adder. The propagation delay exhibit by each full adder designed with different logic families to compute Carry is shown in Table II.
TABLE II. Comparison of Propagation Delay Logic Family 1n1p Split 1n1p Quasi GFCAL Static CMOS Average Propagation Delay 2.03ns 2.88ns 6.91ns 0.1ns

0.5 0.97 1.63 2.44 3.38 4.43 5.58 6.81 8.1 9.45

1.44 2.6 4.24 6.30 8.69 11.4 14.2 17.2 20.2 23.3

2.43 3.38 4.19 4.9 5.54 6.11 6.63 7.11 7.55 7.96

4.49 6.29 8.15 10 11.9 13.8 15.7 17.6 19.5 21.3

On the basis of above results, a graph has been plotted as shown in figure 13.

IJ A
ISSN: 2230-7818

We can see from the above results, the full adder designed with static CMOS offers least propagation delay, as it uses a dc power supply. The fastest adiabatic full adder discussed here is 1n1p split, as it uses two spilt-level sinusoidal power clocks. The maximum propagation delay is encountered by GFCAL based full adder, as it uses a single triangular power clock.

C. Comparison on the basis of variation in Average Power Consumption with Load Capacitance In this section, we have compared the full adders designed with adiabatic logic styles and static CMOS logic on the basis of variation in average power consumption with variation in load capacitance. We have kept power clock frequency to be 100MHZ. Input frequencies are 25MHZ, 12.5MHZ and 8.33MHZ respectively for input A, B and C of a full adder. The operating temperature is 25C. The load capacitance CL is varied from 10 fF to 200 fF in steps of 20 fF and the resulting average power consumption is observed. The simulation results obtained are shown in Table III.

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Figure 13. Variation of Average Power Consumption with Load Capacitance

On the basis of above results, we can see that, the power consumption is increasing with increment in load capacitance in all the designs of full adder, as the dynamic power depends on load capacitance. Power dissipation in 1N1P quasi adiabatic logic occurs mainly due to threshold voltage of MOSFET which is proportional to CVt2 and energy dissipated in MOS resistance to charge and discharge the Load capacitance, E LINEAR. At low capacitance it has very small power dissipation. With increase in load capacitance the power dissipation increases. During the case, when input is logic 0, the power dissipation occurs due to threshold voltage of MOSFET, as well as the in on resistance of MOSFETs of pull up network. Whenever a potential difference exist between drain and source of MOSFET, current will flow through on resistance of MOSFET and power will dissipate and in this logic, current through the MOSFET flows for almost complete half cycle and power will dissipate. Now when input becomes logic 1, the amount of charge stored on capacitance is discharged to ground and dissipated as heat. So when we increase load capacitance these components of power dissipation rises and some point it even becomes more than in Conventional. Power dissipation in 1N1P split level adiabatic logic occurs due to finite rate of change of driving voltage. We

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know that, when ever potential difference exists between drain and source of MOSFET, current will flow through ON resistance of MOSFET and power will dissipate across it and in this family, the current through the pull up network flows through complete half cycle of input and same is true for pull down network in other half cycle of input. At small value of capacitance, it has least power dissipation. Now, when we increase the load capacitance the power dissipation will increase. But remember unlike the 1N1P quasi adiabatic logic no energy is discharged to ground and hence less power dissipation as compared to 1N1P quasi adiabatic logic. In GFCAL, the energy dissipation occurs due to threshold voltage (Vt) of MOSFET, diode cut in voltage (Vd) and energy dissipated in MOS resistance to charge and discharge the Load capacitance, ELINEAR. During charging of capacitance, the power dissipation occurs due to Vt, Vd, and ELINEAR. Same is true during discharge of load capacitance. With increase in load capacitance, the power dissipation due to these component increases. But this occurs only during charging and discharging operation. As it employs rectifying diodes, the power dissipation in pull up network occurs till capacitor is charged, because no backflow of current is possible. Same is true during discharge. So change in load capacitance will has slower rate of change of power dissipation in comparison to 1N1P split and 1N1P quasi adiabatic logic. It is found that, the full adder designed with 1n1p spilt level adiabatic logic offer upto 89% power saving in comparison to the full adder designed with static CMOS. The power saving is more pronounced at lower value of load capacitance. The full adder designed with 1n1p quasi adiabatic logic offer upto 68% power saving in comparison to the full adder designed with static CMOS. Again, the power saving is more pronounced at lower value of load capacitance. At higher value of load capacitance, it dissipates significant amount of power and at some points it exceeds the power consumed by static CMOS based full adder. The full adder designed with GFCAL offer up to 63% power saving in comparison to the full adder designed with static CMOS. Unlike 1n1p split and 1n1p quasi based design, the power saving is more pronounced at higher values of load capacitance, making it suitable to operate at large fan-out.

time periods of all three inputs will vary or their frequency will also vary. Th e si m ul a ti on r esul t s obt a i n ed ar e sh own in T a bl e IV .
Table IV. Variation of Average Power Consumption with Input Frequencies TA(ON) Nano second 50 100 150 200 250 300 350 400 450 500 Average Power Consumption in micro watts
1n1p Split 1n1p Quasi GFCAL Static CMOS

4.81 1.36 1.29 0.81 1.18 0.35 0.96 0.53 0.55 0.47

5.7 2.25 2.09 1.55 1.84 1.08 1.58 1.17 1.2 1.14

3.5 2.41 1.93 1.66 1.45 1.33 1.24 1.1 1.07 1.06

9.4 4.51 3.06 2.26 1.79 1.49 1.38 1.14 1.05 0.9

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ISSN: 2230-7818

D. Comparison on the basis of variation in average power consumption with input frequencies In this section we have compared the full adders designed with 1n1p split, 1n1p quasi, GFCAL and static CMOS on the basis of variation in average power consumption with variation in input frequencies. We have kept power clock frequency to be 100MHZ. The load capacitance CL is fixed at 10f farad and operating temperature is kept at 25C. Here, to represent frequency, we have used TON. Now, as we have used square pulse as input, we have TON = TOFF, so frequency, f =1/T, where T = TON + TOFF. So, as TON will increase, the frequency will decrease. Also, as full adder has three inputs; A, B and C, we have selected their time periods as TA =2TB =3TC. Here we have shown the variation of average power consumption with TON of input A. But as we have mentioned the relationship between time periods of input A, B, C, the

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Figure 14. Variation of Average Power Consumption with TA(ON) or input frequency

Input frequency is a parameter, which determines how often the logic switches between 1 and 0 and thus influences the power consumption of the gate. The variation of power consumed for various input data pulse widths is shown in figure 14. It is observed that lower input frequencies (higher time periods) give a low power dissipation. With increase in frequency, the power dissipation is increased as the possibility of logic switching between 1 and 0 is increased. Hence at higher input frequency, almost every logic family tends to show increased power consumption. But we also see that, some logic families show fluctuation in power dissipation/power consumed and that is expected. The power dissipation in adiabatic logic also depends on the value of power clock at the instant of switching. In adiabatic logic, the potential difference between the nodes through which charging or discharging will take place should be minimum at the time of switching. But as the input frequency is varied, the value of power clock at the time of switching may be different for different values of input frequency. This fluctuation is more pronounced in logic families which have ripples in the

On the basis of above results, a graph has been plotted as shown in figure 14.

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output. Because in these logic families, the potential difference between nodes can be different at the time of switching. It is found that full adder based on 1n1p spilt level pulse adiabatic logic offer upto 70% power saving in comparison to full adder design with static CMOS. The 1n1p quasi based design offer up to 50% power saving in comparison to full adder designed with static CMOS. But under certain input frequencies, it consumes more power than the static CMOS based design. The GFCAL based design offer up to 63% power saving in comparison to static CMOS based design. We can see from the simulation results, at the low input frequency or at large TON, the GFCAL based full adder consume more power than the static CMOS based design. It is also observed that, at smaller TON or high input frequencies, GFCAL based full adder offer excellent power saving. VI. CONCLUSION We have successfully design and simulated 1-bit full adder using 1n1p split-level pulse adiabatic logic, 1n1p quasi adiabatic logic and GFCAL. These designs of full adder along with static CMOS full adder were compared in terms of transistor count, propagation delay and average power consumed by them for different values of load capacitance and input frequencies. The full adder based on 1n1p spilt level pulse adiabatic logic is fastest among the entire three adiabatic logics based full adder. Also, it offers excellent power saving under certain operating conditions and its transistor count is also equal to static CMOS based design. But it is not suitable for pipelining and requires two power clocks. The full adder based on 1n1p quasi adiabatic logic is second fastest adiabatic full adder discussed here. It requires same number of transistors as required by static CMOS. It uses only one power clock. Under certain conditions, it consumes less power than static CMOS. It is also not suitable for pipelining.

[5]

K.A. Valiev and V. I. Staroselskii, A Model and Properties of a Thermodynamically Reversible Logic Gate, Russian Microelectronics, Vol. 29, No. 02, pp. 77-90, 2000. N.S. S. Reddy, M. Satyam and K. L. Kishore, Cascadable adiabatic logic circuits for low power applications, IET Circuits Devices Syst., Vol. 2, No. 06, pp. 518 526, 2008. V. I. StaroselSkii, Adiabatic logic circuits: A Review, Russian Microelectronics, Vol. 31, No. 01, pp. 37-58, 2002. V. I. StaroselSkii, Reversible logic, Microelectronika, Vol.28, Issue 03, pp. 213 -222, 1999. V.V. Losev and V. I. Staroselskii, Power consumption of asymptotically adiabatic static logic circuits, Russian Microelectronics, Vol. 33, No. 03, pp. 188-194, 2004. Y. Moon and D. K. Jeong, An Efficient Charge Recovery Logic Circuit, IEEE Journal of Solid State Circuits, Vol. 31, No. 04, pp. 514 -522, April 1996.

[6]

[7] [8] [9]

[10]

The full adder based on GFCAL requires 32 transistors in comparison to the 28 transistors required by 1n1p split, 1n1p quasi and static CMOS. It requires only one power clock. It offers good power saving in comparison to static CMOS based design under certain conditions, especially for large load capacitance and high input frequency. It is suitable for pipelining, but suffers from drawback of large propagation delay.
REFERENCES

[1]

[2] [3] [4]

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ISSN: 2230-7818

A. G. Dickinson and J. S. Denker, Adiabatic Dynamic Logic, IEEE Journal of Solid State Circuits, Vol. 30, No. 03, pp. 311 -315, March 1995. A. P. Cha ndrakasa n and R. W. Brodersen, Low-power CMOS digital design, Kluwer Academic Publishers, Boston, 1995 . G. Yeap, Practical low power digital VLSI design, Kluwer academic publishers, 1998. J. M. Raba ey a nd M. Pedra m, Low Power Design Methodologies, Kluwer Academic Publishers, Boston, 1996.

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