0,25 m NMOS TRANSISTOR WITH NITRIDE SPACER : REDUCTION OF THE SHORT CHANNEL EFFECT BY OPTIMISATION OF THE GATE REOXIDATION

PROCESS AND RELIABILITY

M.Ada-Hanifi, M.Bonis, Ch.Verove, M.T.Basso, N.Revil, M.Haond, M.Lecontellec. Centre-Commun CNET SGS-THOMSON, 850 Rue Jean Monnet 38921 Crolles, France

Abstract : In this work, we present an investigation of the gate reoxidation step on the short channel effect. The thicker the thermal oxide, the stronger the roll-down of the threshold voltage on the NMOS transistor. This major result lead us to develop an alternative process for nitride spacer with the pad deposited TEOS that behaves as a convenient etch stop layer and allows to obtain a reduced short channel effect. The reliability results on NMOS transistor for the nitride spacers process are similar to those obtained with the TEOS spacer spacer.

Introduction :Oxide spacers in deep sub-half micron technology are limited by a poor conformity of deposited oxides, trenching in the field oxide, and a high occurence of shunts between gate and drain or source, due to the salicidation step. Nitride spacers allow to overcome these difficulties, but usually require a thin oxide layer as etch stop of the nitride spacer etch, in order to prevent active area etch. In this study, it is demonstrated that the reoxidation after gate etch forms a bird's beak under the gate edges which induces an enhanced short channel effect. A thin TEOS deposited layer has been successfully used, in place of the thermal oxide, with the associated improvements of the device characteristics, in terms of short channel effect and Ion-Ioff trade-off optimisation. Process : 1/. In our CMOS 0.25mm process, 10 nm oxide is grown after gate etch and before LDD implants, this thickness is required to obtain a convenient etch stop for the nitride spacer etching. The thickness of the reoxidation was also checked for the TEOS spacer process. In this study, this thermal oxidation is compared with a TEOS oxide deposition of the same thickness 2/. Wet densification at 750C is introduced after LDD Arsenic implantation in NMOS. This improves the oxide integrity before nitride spacer deposition and etch. Nitride spacer etch is performed in a LAM4428 using a standard plasma HBr-SF6-O2 chemistry. Uniformity is 4% and selectivity on oxide is 8. For 110 nm nitride deposition, the spacer width is 70 nm. For process comparison, this nitride spacer is compared to a 110 nm wide TEOS spacer. Results . A- comparison of oxide and nitride spacer process: In Figure 1, the variation of the NMOS threshold voltage (VT) versus the effective channel length does not show any difference between the nitride and the TEOS spacer in the NMOS devices. Since the series resistance is the same, we obtain the same ION-IOFF

0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,15 0,25 0,35 0,45 Leff (m) Fig.1 : VT(Leff) for nitride and TEOS spacer
Nitride spacer TEOS spacer

-7,5 -8 -8,5 -9 -9,5 -10 -10,5 3 4 5 6 ION (mA) Fig.2 : ION-IOFF plot for nitride and TEOS spacer TEOS spacer Nitride spacer

behaviour for oxide and nitride spacer devices : Figure 2. Moreover the channel length is the same, in each case. B - Effect of the gate reoxidation on NMOS : TEOS spacers with a 5 nm thermal reoxidation indicate better performances than the above devices (10 nm reoxidation). Indeed, the VT(Leff) in Figure 3 indicates a reduction of the short channel effect and the ION-IOFF plot, given in Figure 4, shows a higher ION current for the same IOFF for the TEOS spacer with a 5 nm reoxidation, whereas series resistance is identical. The same behaviour is observed with a nitride spacer. These results clearly indicate the main reason of the electrical degradation, that is a thicker gate reoxidation.

0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,15

-5 -6 -7 -8 -9
5 nm gate reox. 10 nm gate reox. 0,35 0,55 Leff(m) Fig.3 : VT(Leff) plot for 5 and 10 nm gate reoxidation and TEOS spacer

10 nm gate reox. 5nm gate reox.

-10 -11 3 5 7 ION (mA) Fig.4 : ION-IOFF plot for 5 and 10 nm gate reoxidation and TEOS spacer

To prevent the short channel degradation and to obtain a good etch stop during the nitride spacer formation, alternative process were developped, based on thin TEOS layer deposition. Two thicknesses were experimented, respectively 10 and 20 nm after 3.5 nm thermal reoxidation. In both cases, significant improvement is obtained on the Vt(Leff) plot compared to the former process based on the 10 nm thermal polysilicon oxidation, (see Figure 5 below). As expected we observe in Figure 6, an improvement on the ION-IOFF plot with the 20 nm TEOS sidewall compared to the conventionnal 10 nm gate reoxidation. Moreover performant etch stop layer is obtained with TEOS deposition that allows us to use this step for nitride spacer process.

0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,15 0,35 0,55 0,75 Leff (m) Fig.5 : VT (Leff) for TEOS and thermal gate reoxidationbefore nitride spacer formation 10 nm gate reox. 20 nm TEOS layer 10 nm TEOS layer

-5 -6 -7 -8 -9 -10 -11 3 5 7 ION (mA) Fig.6 : ION-IOFF for 20 nm TEOS sidewall and 10 nm gate reoxidation layers 20 nm TEOS layer 10 nm gate reox.

Discussion :The thicker reoxidation leads to the formation of a "bird's beak" (i.e: increase of the gate oxide thickness at the gate edges), see TEM observation in Figure 7.

0.02 m 75 50

0,11 m 110

Fig.7 : TEM observation of the bird's beak formation under the gate (courtesy : TEM team of CNET). (A) The bird's beak is 75 at the edge after 5 nm reoxidation. (B) The bird's beak is 110 thick at the edge of the gate oxide after 10 nm reoxidation. The bird's beak is 110 thick at the edge of gate for the 10 nm nominal gate reoxidation and over 0,1 mm length, whereas for the thinner 5 nm nominal gate reoxidation, the gate oxide thickness is 75 at the edge and the bird's beak length is lower than 0,02mm. While this bird's beak has almost no effect on the long channel transistor electrical results, on the contrary it must be taken into account for short channel length. The gate oxide thickness increase at the edge of the channel, leads to an enhanced roll-up but also to an accentuation of the short channel effect according to the expression given below (1): VT = VT0 - DVT, where VT0 is long channel threshold voltage and DVT is the short channel term : DVT = 2.es.Tox.( 2.jF + a.VD)/(L. eox), Tox is the gate oxide thickness, L the channel length, VD the drain voltage and es , eox, the silicon and oxide permitivity respectively. An increase of the effective gate oxide thickness due to the gate reoxidation leads to the reduction of the gate control of the channel and to an aggravation of the short channel effect. In this condition the surface potential ys under the bird's beak is increased in the case of the weak inversion regimes (2). This can explain the higher value of the effective channel length obtained with 10 nm reoxidation. It is obvious that the behaviour described above is observed only if the "bird's beak" length is higher than the gate to source or drain extension overlap.

This explains why for our PMOS devices, where this overlap is higher, due to source-drain boron diffusion, the short channel effect is less sensitive to the gate reoxidation. (see Figure 8). -0,2 Hot carrier degradation : Nitride and TEOS spacer -0,3 10 nm gate reox transistors with 7 nm gate reoxidation were investigated. The 5 nm gate reox. -0,4 aging has been performed at wafer level under accelerated worst -0,5 static conditions (i.e. Vd varying from 3 to 4V and Vg chosen at maximum substrate current) and monitored by measuring the -0,6 degradation of the saturation drain current Ion. Figure 9 -0,7 compares the influences of TEOS and nitride spacer on the 0 0,2 0,4 0,6 degradation of the 0,25 mm transistor stressed under various Leff (m) Fig.8 :VT(Leff) for PMOS with 5 and 10 drain biases. The relatively large decrease of the saturation drain nm gate reoxidation and TEOS spacer current measured when the stress time goes on, as compared to previous process generation, is correlated to a change of the dominant degradation mechanism, negative oxide trapping after classical interface states generation, and reveals that the channel tends to be uniformally damaged. This has been confirmed by threshold voltage shifts and square shaped degraded charge pumping characteristics of the transistor. The degradation tendancy is similar for TEOS an nitride spacer devices. Finally, the elementary device DC drifttime has been extrapolated from the classical Takeda like plot (3) for each type of investigated devices, see figure 10, demonstrating that similar results are obtained whatever the space type is.
-0,1

on/ Ion
3 6 5 2 4 1 1,2,3: TEOS spacers 4,5,6 :nitride spacers 3V 4V 3.5V

Drift-time (s)
1: 0.25 m 2 : 0.3 m 3 : 0.4 m
10 years

3 2 1

Stress time (seconds) Fig.9 : Ion degradation for 0.25 NMOS TEOS and nitride spacer.

1/Vd (m/V) Fig.10 : drift-time vs 1/Vd for various gate length, considering a failure criteria of 10% Ion.

Conclusion : In this paper, we have shown that gate reoxidation is a critical step not only for the nitride spacer process as an etch stop layer, but also for the electrical device performances of deep sumicron CMOS technology. For these reasons, the promising results obtained with a TEOS deposited as good etch stop in replacement to 10 nm sidewall reoxidation and the low short channel effect obtained from numerical simulations and confirmed later by the electrical measurements lead us to consider that this process can be considered as an alternative process. (1)Y.P.TSIVIDIS, operation and modelling of the MOS transistor; Mac Graw Hill; p.189 (2)S.M.SZE,Physics of the semiconductor devices; J.Wiley&Sons, 1981; p.474 (3)E.TAKEDA and al. IEE Proc,130 pp144, 1983.