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CENTRACOM Gold Series Central Electronics Bank Maintenance Manual
2001 Motorola, Inc. All Rights Reserved Printed in U.S.A.
68P81095E50-A
Documentation copyrights
No duplication or distribution of this document or any portion thereof shall take place without the express written permission of Motorola. No part of this manual may be reproduced, distributed, or transmitted in any form or by any means, electronic or mechanical, for any purpose without the express written permission of Motorola. To order additional copies contact your Motorola Sales Representative.
Disclaimer
The information in this document is carefully examined, and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any products herein to improve readability, function, or design. Motorola does not assume any liability arising out of the applications or use of any product or circuit described herein; neither does it cover any license under its patent rights nor the rights of others.
Trademark information
Motorola and Motorola logo are registered trademarks of Motorola, Inc. CENTRACOM Gold Series, Series II Plus, MSF 5000, ASTRO, Touch-Code, Partsnet, Quik-Call I, Quik-Call II, and SmartZone are trademarks of Motorola,Inc. Windows and Windows NT are trademarks of Microsoft, Inc.
1 Table of Contents
Foreword
xv Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Model and kit identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Service information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
Replacement parts ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi Emergency Orders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii Electronic Order Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix Same Day Shipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix General safety information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Motorola limited hardware warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi I. GENERAL PROVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi II. WHAT THIS WARRANTY COVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi HOW TO RECEIVE DEPOT WARRANTY SERVICE . . . . . . . . . . . . . . . . . . . . . xxii Motorola limited software warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii Maintenance philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv Motorola System Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv Technical phone support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi
Chapter 1 Description
1-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Overview of the CEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 System functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Time division multiplex switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Data communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Land Mobile Products Sector

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Audio routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CEB fault maintenance system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Component descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Equipment racks and enclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Card cage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 System timer modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Console operator interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Operator audio expansion interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Base interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Direct phone interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Dual receive interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Phone patch interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 16 I/O board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Aux I I/O board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Aux II I/O board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 RS-232 board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 MDC channel signaling modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Logging recorder interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Remote operator CEB interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 RS-232 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Tone line operated busy light . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Dual tone line operated busy light . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 DC control/LOBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 System wiring and cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Base station control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Tone control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 DC control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Chapter 2 Paging
2-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Paging/signaling specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Quik-Call I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Quik-Call II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Quik-Call II translations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Touch code format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
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Digital dial format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Single tone format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Paging conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Quik-Call I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Quik-Call II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Use of common tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Use of uncommon tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Conversion of existing encoders to Gold Series . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Chapter 3 Descriptor String Assignments
3-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Descriptor string types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Example 1 Conventional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Example 2 Trunking Talkgroup (Type II/SmartZone) . . . . . . . . . . . . . . . . . . . . 3-8 Example 3 Trunking Talkgroup (Type I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Example 4 Selective Private Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Chapter 4 Options
4-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 List of options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Recommended test equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Notes for testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Option descriptions and test procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 K48 Supervisory takeover relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 K56 Mute second receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 K59 Line operated busy light (LOBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 K60 Switched output and separate input indicator (flashing) . . . . . . . . . . . . . . . 4-9 K70 Timed unselected audio mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 K121 Main/standby relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 K123 Switched output with one indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 K124 Switched output with two indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 K138 Switched output with separate external input . . . . . . . . . . . . . . . . . . . . . 4-14 K139 DC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 K143 Repeater control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
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K146 Do not disable tone encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 K170 Extended initial guard tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 K235 Priority channel marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 K380 Carrier operated relay input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 K570 Headset jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 K572 Footswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 K577 Telephone/headset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 K578 Audible alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 K700 PTT output relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 K704 Additional headset jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 K710 Self repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 K711 Coded/clear for DVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 K713 External input with two indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 K714 External input indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 K715 Two separate external input indicators . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 K735 Dedicated unselect speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 K739 Signaling input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 K744 PL Strip for paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 K748 High speed mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 K757 Dedicate select speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 K766 Latched input with individual reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Chapter 5 Maintenance and Diagnostics
5-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Fault maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Fault maintenance features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Response times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Failures not detected by fault maintenance system . . . . . . . . . . . . . . . . . . . . . . 5-4 Fault maintenance operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Tone loop tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Connecting an external printer or readout device . . . . . . . . . . . . . . . . . . . . . . . 5-13 Interpreting error message printouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Part 1: System integrity compromised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
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Part 2: Problem Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Part 3: Re-evaluation of system Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Part 4: Action taken and result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Recovery messages in Part 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Recovery status messages in part 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Recovery messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Part 5: End of error handling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Other system status and error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 SmartNet trunking system status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 SmartZone trunking system status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Running diagnostics from the operator position . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Running diagnostics from an external printer or readout device . . . . . . . . . . . . 5-60 Printing call data in selective signaling systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Printer capacity and data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Printer baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Converting from Fault Maintenance to Data Logger . . . . . . . . . . . . . . . . . . . . . 5-66 Data Logger Example and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 Replacing boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 Removing a board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 Addressing and jumpering a board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 Inserting a board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
Chapter 6 Hybrid Troubleshooting
6-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Hybrids covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Recommended test equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Digital Level Memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Hybrid troubleshooting procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Base Interface Module hybrids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Dual Receive Module hybrids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Bus driver hybrids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
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Chapter 7 CEB Card Cage Interconnect Board
7-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interconnect board compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Card edge pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Console interface terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Phone line terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Option I/O terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Extender boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Main extender board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Option extender board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 BLN1141A Main Extender Board Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 BLN1142A Option Extender Board Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 BLN6648A Backplane Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Chapter 8 Base Interface Module
8-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Receive audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Transmit audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 DLM audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Microprocessor system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Microprocessor reset and watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Module address programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Data communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Auxiliary input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Tone generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Guard tone gating and low pass filter hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Three-state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Logging recorder output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 BLN6654D Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
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Chapter 9 Dual Receive Interface Module
9-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Microprocessor system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Module address programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Microprocessor watchdog timer and reset sequence . . . . . . . . . . . . . . . . . . . . . 9-6 Transmit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Receive data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Bus driver/three-state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Module self test feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Auxiliary inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 DR module jumpering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 DR signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 BLN6656C Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Chapter 10 Console Operator Interface Module
10-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Microprocessor and peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Watchdog timer and three-state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Diagnostic tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Operator audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 CEB data bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Logic cell array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 DSP56166 and peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 Audio output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 Voltage regulation and power fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 LCA Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Jumper tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 BLN7061A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
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Chapter 11 DPI/SPI
11-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Features and capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 DPI and SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 MRTI RLM-3 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Ring detect circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Ring tone generator/ring driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Diagnostic tone tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Call detect and drop out delay select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Line seize and off hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 2-wire/4-wire converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 BLN6872A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 BLN6873A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Chapter 12 Punch Block and Spark Gap
12-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 BLN1147A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Chapter 13 System Timer Module
13-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Crystal oscillator/10 Hz generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 50/60 Hz conditioning circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 Vote/status circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 Enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Switched A+ and switched ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Programmable gate array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 System interconnect board interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 5 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
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12 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 BLN7011A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
Chapter 14 Operator Audio Expansion Interface
14-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Timing and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Audio inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Audio outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 Interfacing to the COIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 Power supply and voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 BLN6845A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Chapter 15 16 I/O Module
15-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Microprocessor control system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Watchdog timer and reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
three-state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Transmit data circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Receive data circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Local input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Remote input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Relay output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Input circuit jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 BLN6721C Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
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Chapter 16 Logging Recorder Interface Board
16-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Audio inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Audio filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 Testing the LORI Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 BFN6008A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Chapter 17 MDC Channel Signaling Modem
17-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 Serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 Squelch circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 BLN6893A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
Chapter 18 ASTRO Console Interface Module
18-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 BLN7025A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
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Chapter 19 Remote Operator CEB Interface Board (and Later Version)
19-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 Line transmitter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 Line receiver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 Oscillator/counter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 Handset microphone circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 Fail detect circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 BLN6831A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
Chapter 20 RS-232 Interface Relocator Board
20-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 Modes and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 MODEM and TERMINAL Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 Interface function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 COIM relocation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 Primary interface circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 Handshake signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 Secondary interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 Jumper configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 BLN6755C Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
Chapter 21 Auxiliary I Module
21-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 Simple input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 Relay output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 2-Wire main/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
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4-Wire main/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 Takeover circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 Serial data circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 BLN6664B Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19
Chapter 22 Auxiliary II Module
22-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 Simple input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 Relay output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 Transformer coupled input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 BLN6725A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
Chapter 23 Tone Line Operated Busy Light
23-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 Audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 Unity or 10 dB gain stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 Automatic Gain Control stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 First filter stage and limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 Guard tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 Guard tone detection inhibitor circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 BLN6666B/BLN6933A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
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Chapter 24 Dual Tone LOBL
24-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Input transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Variable gain stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 AGC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Activity checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 High-pass filter and attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 First high Q filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 Variable attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 Second high Q filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 Detection prevention circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 Guard tone level checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 Guard tone duration checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 Output buffer and inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 Notch filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 Tone detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 Testing the Dual Tone LOBL Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 BLN6830A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
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Chapter 25 DC Control/LOBL
25-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 DC current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 DC LOBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 DC enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 DC-to-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 Clock and data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 Initial charging of the line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 DC LOBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 Adjustment procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 BLN6665B Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 BLN6667B Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
Chapter 26 Power Supplies
26-1
About this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 Proprietary notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 Power factor correction module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 DC to DC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 Stepdown module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 SM8 monitor board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 CEB supply LEDs and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 Battery test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 Field replaceable items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
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Chapter 27 Cable and Hardware Kits
27-1
Models covered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 BKN6072A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 BKN6073A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 BKN6080A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 BKN6083A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 BKN6085A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 BKN6091A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 BKN6093A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 BKN6100A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 BKN6107A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 BKN6112A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 BKN6122A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 BKN6125A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14 BKN6126A/BKN6127A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15 BKN6147A Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 BLN6745A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 BLN6757A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 BKN6109A Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19
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1 1 Description
About this chapter

Section
Introduction Overview of the CEB System functional description CEB fault maintenance system Component descriptions System wiring and cabling Base station control functions
Page
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Introduction
Introduction
This manual provides maintenance instructions and theory of operation for the CENTRACOM Gold Series Central Electronics Bank (hereinafter referred to as the CEB). The CEB is part of the CENTRACOM Gold Series Console, which provides the operator interface to the radio base stations. The CEB includes the interfaces to the radio base stations, interfaces for each of the operator positions, and the switching electronics used to route audio from the base stations to the operators and vice-versa.
Overview of the CEB

The CEB is an electronics package which houses the interface modules for base stations, monitor receivers, operator positions, phone patch lines, and auxiliary inputs/outputs. All of the system audio routing is performed in the CEB, using the time division multiplex switching technique. The basic CEB is made up of a card cage, 15-foot 25-pair termination cable, punch block with spark gaps, and a power supply. Depending upon the size of the system and the number of interface modules required, additional card cages with termination accessories and power supplies are added. Each system includes two system timer modules and space for the proper number of interfaces.
Options
Options are made up of combinations of firmware, electrical, and mechanical configurations. Extra microphones, headsets and other external communications devices can be added as options. Most options are implemented, via firmware, through the CEB. Many other options are available besides the examples here. Some options may be added in the field at a later date. System expansion may also be accomplished in the field. Refer to Chapter 4 of this manual for descriptions of the available options.
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System functional description

General
The system electronics may be divided into two basic groups: the operator position(s) and the CEB. The operator position includes the controls for each radio channel and the speakers and microphone used by the operator to access those channels. The CEB includes the interfaces to the radio base stations, interfaces for each of the operator positions, and the switching electronics used to route audio from the base stations to the operators and vise-versa. A seven pair cable connects an operator position to the CEB. All interface between the boards in the CEB is accomplished via a TDM (Time Division Multiplexed) bus. Refer to Figure 1-1 for details.
T2 R R T22R BASE CENTRAL ELECTRONICS BANK DUAL RECEIVE MODULE BASE INTERFACE MODULE BASE INTERFACE MODULE T R TIRI BASE
TIMER MODULE TDM BUS WITH CONTROL SIGNALS
OPERATOR INTERFACE MODULE
OPERATOR INTERFACE MODULE
OPERATOR INTERFACE CABLE (ONE CABLE WITH 7 TWISTED PAIRS)
OPERATOR CONSOLE
OPERATOR CONSOLE
CEN026 110395JNM
Figure 1-1
Block diagram of the CEB
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Time division multiplex switching

The audio process used by the system to route audio to and from the different stations and operators is called Time Division Multiplexing (TDM). This digital process has distinct advantages over analog switching because of its high immunity to radio frequencies, allowing field or service personnel to use portable radios near the console without disrupting console operations, and because of its very low cross talk, even in large systems and under multiple patch conditions. In TDM, the audio from a base station is first digitized, or converted into its digital equivalent, by the Base Interface Module (BIM) in the CEB. The conversion method is 64 kilobit Pulse Code Modulation (PCM). The analog to digital conversion circuit samples the voice signal approximately 8000 times a second and creates a digital sample (or word eight- bits long) which summarizes the audio wave form. (See Figure 1-2.) The audio from the operators microphone is also digitized and placed on the bus. This 64,000 bit per second (eight-bits per sample, multiplied by 8000 samples per second) digital audio is then placed on one of three digital buses which link all of the modules in the CEB.
ANALOG AUDIO SIGNAL
01000000 01001001 01001111 01010101 DIGITIZED
SAMPLED AUDIO SIGNAL
CEN027 011796JNM
Figure 1-2
Audio Wave form digitization
The audio from each BIM and each operators microphone is assigned a specific slot or place in time on one of these buses. Each bus has room for 32 of these time slots as shown in Figure 1-3. Each user or audio source places one sample of its particular digital audio on the bus. After all 32 users have had their turn, the process is repeated and each user places the next sample of digital audio on the bus. The bus handles data at approximately two million bits per second (32 slots x 8 bits/slot x 8000 samples/second). This process defines the point at which each audio source places the PCM-encoded signal. When an operator selects a channel, the microprocessor on the Console Operator Interface Module (COIM) associated with the operator position accesses that TDM time slot and routes the signal to the proper output. Each bus can handle 32 separate sources and, since there are three distinct buses, up to 96 sources can be accommodated in a basic console system.
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32 TIME SLOTS
TIME
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0
0 1 2 3 4 5 6 7
8 BITS PER SLOT
CEN028 110395JNM
Figure 1-3
TDM bus time slot format
Data communications
In addition to the three digital audio buses, there is a fourth bus used for data communication between the CEB modules. The information sent on this bus includes instructions concerning which operators audio slot a particular BIM should listen to at a particular time, information about what function tone a BIM should send, or information to provide parallel operators with updated status when any one operator performs a console function. This fourth bus forms a 64,000 bit per second data channel. Access to this fourth data bus and to the three audio buses is controlled through dual level fail-safe three-state (or isolation) circuits. These three-state circuits are controlled in turn by a series of data grant lines which are separate from the bus system. Access to the data grant lines are also dual level three-state protected. Finally, there is one additional communication path between the COIMs which provides for the voting capability of the diagnostic systems. The maintenance/diagnostic section of this manual has additional details concerning the multiple levels of protection for all audio and data paths and the diagnostic and self-healing capabilities which provide this console with its high levels of reliability.
Audio routing
General
There are many audio sources in a system. These sources include operator position microphone audio, phone patch audio, receive audio from any radio receiver in the system, and any control audio generated by the CEB. All audio is converted from analog to digital and placed on a slot on the TDM bus where it can be received by another module and converted back from digital to analog. Since each audio source in the system is assigned to a particular slot on a TDM bus, any audio source can be selected by simply addressing the desired TDM source slot. This process greatly simplifies audio routing.
Receive Audio Routing

A typical receive operation is shown in Figure 1-4. Assume a mobile unit calls the operator and the signal is received on receiver #1. Assume also that the operator has selected receiver #1 audio to be monitored on the SELECT speaker. The audio from receiver #1 is applied to the input of the associated BIM in the CEB, where it is digitized
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and placed on slot I of the TDM bus. (Slot I of the TDM bus is selected by DIP switch settings on the BIM.) Since the operator has selected the audio from receiver #1 to be heard on the SELECT speaker, the microprocessor on the COIM addresses a programmable multi-slot receiver (also on the COIM) to retrieve the audio from TDM bus slot 1. The audio is then converted from digital to analog and routed to the SELECT speaker on the operators console.
NOTE The information that receiver #1 audio is on TDM bus slot I is programmed into the PROM on the COIM.
RCVR
P/O BASE INTERFACE MODULE
DLM
ANALOG TO DIGITAL CONVERTER
SLOT XTMR
SLOT NUMBER PROGRAMMING P/O CENTRAL ELECTRONICS BANK TDM BUS
P/O OPERATOR INTERFACE MODULE PROGRAMMABLE MULTI-SLOT RECEIVER AND DIGITAL TO ANALOG CONVERTER
MICROPROCESSOR SYSTEM
P/O 7 TWISTED PAIR CABLE
P/O OPERATOR CONSOLE
SELECT SPEAKER
SELECT SPEAKER
CEN029 110395JNM
Figure 1-4
Receive Audio Path, Simplified Block Diagram
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Transmit Audio Routing

A typical transmit operation is shown in Figure 1-5. Assume that the operator wants to reply to the mobile call that came in on receiver #1. The operator presses the instant transmit button on the channel for the area the mobile unit is in to initiate a reply. The microprocessor on the radio control board in the operator position encodes the instant transmit into a digital word and sends it to the COIM in the CEB. The microprocessor on the COIM looks up the data word in its personality PROM and discovers it to be a transmit command for base station #1, which is controlled by BIM #1. The operator interface sends a data packet to BIM #1, telling it to send the proper key up command to the base station and to listen to the digital audio slot on the TDM bus corresponding to the originating COIM. The BIM decodes the message and, when it has keyed the station and is ready to transmit, sends a data message back to the COIM, acknowledging that the key up has occurred and is ready for the audio message. The COIM microprocessor decodes the digital message and interrogates the personality PROM for instructions. At this point the personality PROM tells the COIM microprocessor to display the appropriate transmit indication at the operator position for the keyed-up channel, indicating that the base station is keyed and ready for the audio message. The operators audio is then routed through the COIM where it is converted to digital audio, placed on the appropriate slot on the TDM bus, retrieved from the TDM bus by the BIM, converted back to analog audio, and then routed to the base station for transmission. This audio routing and processing is quite similar to that performed on receive audio.
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XTMR
P/O BASE INTERFACE MODULE
LINE DRIVER
ANALOG TO DIGITAL CONVERTER
PROGRAMMABLE SLOT RCVR
MICROPROCESSOR SYSTEM CENTRAL ELECTRONICS BANK
TDM BUS
SLOT NUMBER PROGRAMMING
SLOT XTMR
SLOT NUMBER PROGRAMMING
A/D CONVERTER
P/O OPERATOR CONSOLE
DLM
CONSOLE MICROPHONE
CEN030 100295JNM
Figure 1-5
Transmit Audio Path, Simplified Functional Diagram
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CEB fault maintenance system
CEB fault maintenance system

The fault maintenance system is a distributed software structure that locates defective circuits, isolates these circuits, and notifies the user of any problems. The fault maintenance system runs continuously to ensure that no single point failure can bring the system down. The BIMs can be configured for redundancy at the customers option. If a module fails, the fault maintenance system then switches over to the redundant BIM automatically, and also causes a periodic automatic switchover. The periodic switchover ensures that failures that may occur when a module is in standby are also detected. The fault maintenance system tests the path of audio signals through many loops in the system. Based upon the results of these loop tests, failures are isolated to the circuit board level. The loop test is applied all the way to the base station phone line to assure a complete system fault maintenance test. The data communications links between the microprocessors in the system are also tested. Testing is performed by requiring the microprocessors to send sound off packets to each other once every five seconds. Each microprocessor expects to hear a sound off packet from all other microprocessors in the system at 5-second intervals. If a sound off packet does not occur, the system tries again at the next interval. If the packet is missed a second time, the system performs a series of tests to determine the faulty module. Once the faulty module is isolated, the module is three-stated and the redundant module (if there is one) is enabled. Whenever a module is three-stated because of a fault maintenance test failure, the operator is notified by a special error message that appears on the clock display of Classic Buttons and LEDs and Classic CRT consoles, and in the System Error display line located at the bottom of the Elite console screen display. If a failure occurs, the operator should notify maintenance personnel. The maintenance person then performs the tests listed in the Maintenance And Diagnostics section of this manual (chapter 5) to determine the exact nature of the fault. The maintenance person then replaces the faulty board. The board is then sent to the depot service facility listed in the Foreword of this manual for repair.
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Component descriptions
Equipment racks and enclosures
In all systems, the CEB equipment is housed in separate enclosure(s) or in standard EIA 19-inch rack(s) in a remote location or equipment room.
Card cage
Each card cage provides mounting space (slots) for up to 10 circuit boards. Two slots are dedicated to COIMs. The remaining eight slots can be populated with any of the following circuit boards, depending on the customers requirements: p p p p p p p p p p p p p p p p p System Timer Module (two required; one redundant) Base Interface Module (BIM) One BIM is required for each base station. Dual Receive (DR) Module Direct Phone Interface (DPI/SPI) module Audio Expansion Interface Module (AEI) 16 I/O Auxiliary I and/or Auxiliary II Module Logging recorder interface (LORI) board Modem Astro Console Interface Module (ACIM) Remote Console Operator Interface (ROCI) RS-232 interface board Auxiliary I Module (Aux I) Auxiliary II Module (Aux II) Tone LOBL Dual Tone LOBL DC Control/LOBL
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System timer modules may be located in either COIM or BIM slots of the cage. (See Figure 1-6) Above each slot in the cage is a second slot for the placement of an option card, which will then work with the module directly below it.
STATION CABLES FOR OPTIONS OPERATOR POSITION A CABLE BASE STATION CABLE OPERATOR P4 POSITION B CABLE P2 P5
P1
P3
MULTIPLE CARD CAGE DAISY CHAIN CABLE CONNECTIONS P8 (TOP) AND P7 (BOTTOM) OPTION BOARDS (RS-232, AUX1, AUX2)
POWER CONNECTION P6 (NOT SHOWN)
4 OTHERS (BIM, DR, SYS TIMER OR AUDIO EXPANSION INTERFACE) 2 OPERATOR INTERFACE MODULES CEB CARD CAGE
CEB MODULES (INTERFACE BOARDS)
4 OTHERS (BIM, DR, SYS TIMER OR AUDIO EXPANSION INTERFACE)
CEN140 021496JNM
Figure 1-6
CEB Card Cage
The top portion of the cage provides two seven-pair telco-style jacks for connection to the two operator positions associated with the COIMs, and one centrally located 25-pair telco-style jack for the 4-wire audio and logging recorder outputs of up to eight BIMs. There are two 25-pair connectors which provide the switched audio or input/output pairs if optional takeover relays, main/standby relays, or auxiliary input/outputs are used on the BIMs. One of these two connectors handles the four BIM slots on the left side of the card cage and the other connector handles the four on the right side. On the top and bottom edges of the cage are the power inputs and connectors to link multiple card cages together.
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When a system is expanded and additional interface modules and card cages are added, the new cages connect to the old ones with a plug-in cable. Since all of the audio routing is done on the shared digital buses, there is no wiring between the interface modules. Only the 4-wire base station phone lines must be wired to the punch block to complete the wiring installation.
Punch block and spark gap board

The system is supplied with one or more 25-pair termination cables that terminate in a punch block and 3-lead spark gaps. All wire line connections to and from base stations and telephone services connect to the punch blocks. The 3-lead spark gaps provide surge protection to all inputs. (Refer to Figure 1-7).
25-PAIR CABLE
GROUND STRAP
SPARK GAP
J1/P1 J2
SPARK GAP BOARD PUNCH BLOCK

CEN195 022096JNM
Figure 1-7
Punch Block
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Refer to Table 1-1 for pin arrangements.

Table 1-1
Punch Block
CEB Interconnect Board to Punch Block Pin Arrangements

CEB Interconnect Board Plug P2 Phone Line Connector Card Cage Slot No. 10 10 10 10 10 10 09 09 09 09 09 09 08 08 08 08 08 08 07 07 07 07 07 07 Option Option 04 04 04 04 04 04 2-Wire 2-Wire 4-Wire 4-Wire Log Log 31 32 29 30 21 22 57 58 59 60 63 64 Function Aux. Bd. Pin No. 21 22 29 30 31 32 21 22 29 30 31 32 21 22 29 30 31 32 21 22 29 30 31 32 Main Bd. Pin No. 63 64 59 60 57 58 63 64 59 60 57 58 63 64 59 60 57 58 63 64 59 60 57 58 CEB Interconnect Board Plug P3 Option Connector Card Cage Slot No. 10 10 10 10 10 10 10 10 10 10 10 10 09 09 09 09 09 09 09 09 09 09 09 09 08 08 08 08 08 08 08 08 Pin No.
CEB Interconnect Board Plug P1 Option Connector Card Cage Slot No. 04 04 04 04 04 04 04 04 04 04 04 04 03 03 03 03 03 03 03 03 03 03 03 03 02 02 02 02 02 02 02 02 Pin No
Pair
Pin No.
01
26 01
02 01 04 03 06 05 08 07 10 09 12 11 02 01 04 03 06 05 08 07 10 09 12 11 02 01 04 03 06 05 08 07
Log Log 4-Wire 4-Wire 2-Wire 2-Wire Log Log 4-Wire 4-Wire 2-Wire 2-Wire Log Log 4-Wire 4-Wire 2-Wire 2-Wire Log Log 4-Wire 4-Wire 2-Wire 2-Wire
02 01 04 03 06 05 08 07 10 09 12 11 02 01 04 03 06 05 08 07 10 09 12 11 02 01 04 03 06 05 08 07
02
27 02
03
28 03
04
29 04
05
30 05
06
31 06
07
32 07
08
33 08
09
34 09
10
35 10
11
36 11
12
37 12
13
38 13
14
39 14
15
40 15
16
41 16
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Table 1-1
Punch Block
CEB Interconnect Board to Punch Block Pin Arrangements (continued)

CEB Interconnect Board Plug P2 Phone Line Connector 03 03 03 03 03 03 02 02 02 02 02 02 01 01 01 01 01 01 2-Wire 2-Wire 4-Wire 4-Wire Log Log 2-Wire 2-Wire 4-Wire 4-Wire Log Log 2-Wire 2-Wire 4-Wire 4-Wire Log Log 31 32 29 30 21 22 31 32 29 30 21 22 31 32 29 30 21 22 57 58 59 60 63 64 57 58 59 60 63 64 57 58 59 60 63 64 CEB Interconnect Board Plug P3 Option Connector 08 08 08 08 07 07 07 07 07 07 07 07 07 07 07 07
Not Used Not Used
CEB Interconnect Board Plug P1 Option Connector 02 02 02 02 01 01 01 01 01 01 01 01 01 01 01 01

Not Used Not Used
17
42 17
10 09 12 11 12 11 10 09 08 07 06 05 04 03 02 01 -
10 09 11 12 12 11 10 09 08 07 06 05 04 03 02 01 -
18
43 18
19
44 19
20
45 20
21
46 21
22
47 22
23
48 23
24
49 24
25
50 25
System timer modules

The CEB contains two system timer modules, which synchronize the system and create the timing sequence permitting the CEB interface modules to access the three audio buses and the data bus. Only one timer is required at a time; the second timer is a hot standby unit. The system timer module does not include a microprocessor and is basically comprised of a clock and divider circuits. The system bit-rate clock runs at 2 MHz and provides all the basic timing for the system. The clock output defines each bit position within each slot on the TDM bus. The 2 MHz clock is divided down to 10 Hz, compared with the 50/60 Hz line frequency to maintain accuracy, and used as an input to the real time clock and calendar circuits. The slot counter provides the frame sync and slot assignment functions on the TDM bus. The 2175 Hz guard tone circuit divides the 2 MHz clock to provide the guard tone frequency. The majority rule detector circuit and three-state control circuit allow for automatic switchover to the second system timer module in the event of a failure and for hot standby of the second timer. Switchover between the two system timer modules occurs automatically once each day or upon a timer failure.
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Console operator interface module

The COIM provides the link to an operator position. Each COIM contains input/outputs that connect a radio control panel to the CEB, microphone audio from the operator, and four audio amplifiers that route receive audio to the operator. The COIM digitizes the microphone audio and places it on a TDM bus slot. It also converts digital audio on a selected TDM bus slot to analog for application to a speaker module at the operator console. The COIM microprocessor, along with a personality PROM, perform all the control functions between the operator position and the CEB modules. The personality PROM contains operating instructions for the microprocessor regarding every operating mode available at the operator position, as well as any options the system may contain.
Operator audio expansion interface module

The operator Audio Expansion Interface Module (AEI) expands the digital audio capabilities of COIMs in larger systems. An AEI is added to the system if the operator requires more than the standard two spare monitor speaker outputs. An additional AEI allows seven additional speakers to be added to the operator console. The AEI is controlled by the COIM to select the desired audio slot from the TDM bus.
Base interface module

The BIM provides a 4-wire (or 2-wire) interface for a single receiver base station. In the case of multiple receiver stations, one or more dual receive interface modules are used to expand the receiver inputs to match the base station requirements. Only one BIM is required per base station, no matter how many operators in the console system have access to the station. Redundant hot standby BIMs may be used in a system. The diagnostic system periodically tests the primary BIM and automatically switches over to the redundant BIM if the tests fail. Audio from the base station receiver is processed through the BIM and placed in a particular time slot on one of the three TDM buses. Other interface modules and COIMs listen to this TDM bus time slot if the audio from this receiver is to be monitored for any reason. Similarly, the BIM can listen to the digital audio on any time slot on any of the three TDM buses, convert the audio to analog, and pass the audio on to the base station for transmission. The microprocessor on the BIM interprets commands from the COIMs to generate function tone commands for the base station, and to generate paging or signaling formats, if required. The BIM microprocessor has six input/output ports to allow it, with the addition of an auxiliary interface module (Aux I or Aux II), to receive status information from an outside source such as an alarm, or to activate an outside device such as a garage door. These external inputs/outputs are referred to as auxios.
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Direct phone interface module

The Direct Phone interface (DPI) module allows an operator to access a commercial phone line directly from the console without the use of a separate telephone. It can be used to answer or initiate a phone call, for phone patch operations, or as an intercom between operators on separated systems (CEBs) where there is no data link. With this option, it is no longer required to run separate phone lines from an external telephone back to the phone patch interface in the CEB. All the functions previously performed by this external phone are now all self-contained within the console systemincluding dialing through the consoles keypad, spark gap protection, and an FCC-approved coupler. One DPI is required for each phone line to be controlled in this manner.
Dual receive interface module

The Dual Receive interface module (DR) provides the interface between the control center and two monitor receivers. Each DR contains two identical circuits, one for each monitor receiver. Audio from each receiver is digitized by the DR and placed in one of two assigned time slots on the TDM bus. The audio on the TDM bus may be retrieved by any other interface module through proper control addressing.
Phone patch interface module

The phone patch interface module is identical to a BIM except that it does not generate keying tones or currents. A registered protective coupler is included with the phone patch interface for connection to a telephone instrument with an exclusion key. Several phone patch modules may be installed in the CEB to provide multiple simultaneous phone patch capability.
16 I/O board
The 16 I/O Module provides 16 input or output circuits for connection to external devices or circuits. The module allows the console to monitor up to 12 local input circuits and up to four remote circuits.
Aux I I/O board

The Aux I input/output interface module (Aux I) plugs into the CEB card cage above a BIM. The six I/O pairs on the BIM connect to control relays or monitor indicators on the Aux I module. The relays then control external devices, or switch options. There are 40 jumper wires on the module which can be set to determine the functions used. The Aux I module adds additional auxio capability to the CEB.
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Aux II I/O board

The Aux II input/output interface module (Aux II) plugs into the CEB card cage above a BIM. The six I/O pairs on the BIM connect to control relays on the Aux II board, or monitor input circuit status. The relays are used to control external devices or to switch options. There are 15 jumper wires on the module, which can be set to determine the functions used. The Aux II board adds additional auxio capability to the CEB.
RS-232 board
The RS-232 option board provides a standard RS-232 input or output which may be used for computer interface, external printers, etc. The board is mainly used to interface data communications lines external to the CEB. Its circuitry consists of a 5 V voltage regulator, negative voltage generator, and level shifters.
MDC channel signaling modem

The channel signaling modem is an option to the BIM that provides channel signaling capability to the console.
Logging recorder interface board

The LORI provides connection for a recording device, which records certain calls coming into the console, such as emergency calls.
Remote operator CEB interface board

The ROCI is an optional board that permits a remotely located operator position to interface to the CEB via phone lines.
RS-232 interface
The RS-232 interface relocator board provides two functions: it interfaces a CEB board to an external device such as a printer, or it can act as an audio I/O port for special applications. It also permits a COIM to be installed in any slot in the card cage.
Tone line operated busy light

The tone LOBL is associated with a BIM and detects usage of the channel. It provides a busy indication for its channel at all consoles in the system, informing other operators when the channel is in use.
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Dual tone line operated busy light

The dual tone LOBL detects when a parallel console is transmitting on a channel and provides a busy indication, and it indicates when a trunking system has gone into Failsoft mode. It is for use in trunking systems only.
DC control/LOBL
This board performs the same busy indicator function as the tone LOBL, and it also generates dc control signals for keying a dc-controlled base station. It is mounted on its associated BIM on stand-offs and is corrected with a ribbon cable.
Power supply
Two power supplies are used in the CEB. One supply provides 9 V regulated dc and the other supplies 15 V regulated dc, each at 10 amperes. Both supplies provide brown out protection (including erratic brown out recovery protection), short circuit protection, and variable over-voltage protection. An uninterruptable power supply (UPS) is provided to allow retention of memory and real time clock operation during brief main power failures or during switchover to standby backup generators. (Refer to the Power Supply section of this manual for details.)
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System wiring and cabling
System wiring and cabling

Each systems wiring and cabling is fully documented in the As Built documentation shipped with the system from the factory. Refer to this documentation for all system wiring and cabling information as required.
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Base station control functions

There are two types of base stations: those controlled by specific tones, and those controlled by dc signals. If a dc-controlled base station is being used, a DC control module must be used in the associated BIM.
Tone control functions

Table 1-2 provides an index of the tone frequencies generated by the BIM under various control configurations.
Table 1-2
Tone Table T1 Standard T2 Standard W/8PL

PL MON F1 F1 W/O PL PL 5 PL 6 PL 7 PL 8 PL 1 PL 2 PL 3 PL 4
Freq.
2050 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050
W/O PL
PL MON F1 F1 W/O PL R2 OFF R2 ON RPTR OFF RPTR ON WC I ON WC I OFF WC II ON WC II OFF
W/4PL
PL MON F1 F1 W/O PL R2 OFF R2 ON RPTR OFF RPTR ON PL 1 PL 2 PL 3 PL 4
W/O PL
PL MON F1 F2 R2 OFF R2 ON RPTR OFF RPTR ON WC I ON WC I OFF WC II ON WC II OFF
W/4PL
PL MON F1 F2 R2 OFF R2 ON RPTR OFF RPTR ON PL 1 PL 2 PL 3 PL 4
W/8PL
PL MON F1 F2 PL 5 PL 6 PL 7 PL 8 PL 1 PL 2 PL 3 PL 4
T4 Standard
PL MON F1 F2 RPTR OFF RPTR ON F3 F4 WC II ON WC II OFF
T8 Standard
PL MON F1 F2 F7 F8 F3 F4 F5 F6
Note: 950, 850, 750, and 650 Hz are used for special applications and require a quotation. Note: PL stands for Private Line. Note: WC stands for Wildcard.
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DC control functions
Table 1-3 lists the dc currents generated by the dc control module under various control configurations.
Table 1-3
DC Control Applications
Function Nominal Current Minimum Current Maximum Current
T1 Standard W/O PL STRIP

F1 Transmit Repeater On Repeater Off Squelch Disable 5.5 mA 12.5 mA -5.5 mA -2.5 mA 4.6 mA 10.5 mA -6.4 mA -2.9 mA 6.4 mA 14.5 mA -4.6 mA -2.1 mA
T1 Paging W/PL STRIP

F1 Transmit F1 Page Squelch Disable 12.5 mA -12.5 mA -2.5 mA 10.5 mA -14.5 mA -2.9 mA 14.5 mA -10.5 mA -2.1 mA
T2 Standard
F1 Transmit F2 Transmit Mute R2 Squelch Disable 5.5 mA 12.5 mA -5.5 mA -2.5 mA 4.6 mA 10.5 mA -6.4 mA -2.9 mA -2.1 mA 6.4 mA 14.5 mA
T4 Standard
F1 Transmit F2 Transmit F3 Transmit F4 Transmit Squelch Disable 5.5 mA 12.5 mA -5.5 mA -12.5 mA -2.5 mA 4.6 mA 10.5 mA -6.4 mA -14.5 mA -2.9 mA 6.4 mA 14.5 mA -4.6 mA -10.5 mA -2.1 mA
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Description
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Paging
About this chapter

This chapter explains how to determine the paging codes to be entered, for Quik-Call I and II for the Centracom Gold Series encoder, when converting from an older series encoder. This chapter also provides information for determining the correct operation of any paging transmission capable of being generated by a CENTRACOM Gold Series console.
Section
Paging/signaling specifications Paging conversions 2-2 2-10
Page

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Chapter 2
Paging
Paging/signaling specifications
Quik-Call I
The duration and spacing of the tones for a Quik-Call I page is shown in Table 2-1:
Table 2-1
Quik-Call I Tones
Tone
800 mS 1200 mS 200 mS 1000 mS
Normal Call
Pre-Tone Delay Tones A and B Intertone Delay Tones C and D
Group Call
Pre-Tone Delay Tones A and C
Tone
800 mS 8000 mS
The occurrence of a group call is determined by the five-digit Quik-Call I code. A group call is made when the five-digit code, XABCD satisfies the conditions A = C and B = D. The first digit, digit X, represents a tone group that the tone frequencies reside in as shown in Table 2-2. In Quik-Call I, two tones from one group are generated simultaneously. The group used for a specific page is determined by the first digit of the five digit code as follows: First digit = 0: Tone Group = A First digit = 1: Tone Group = B First digit = 2: Tone Group = Z
Table 2-2
Quik-Call I Tone Frequencies (in Hz) Series A

358.9 398.1 441.6 489.8 543.3 602.6 668.3
Digit
0 1 2 3 4 5 6
Series B
371.5 412.1 457.1 507.0 562.3 623.7 691.8
Series C
346.7 384.6 426.6 473.2 524.8 582.1 645.7
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Chapter 2
Paging
Table 2-2
Quik-Call I Tone Frequencies (in Hz) (continued) Series A

741.3 822.2 912.0 1011.6 1122.1
Digit
7 8 9 A B
Series B
767.4 851.1 944.1 1047.1 1161.4
Series C
716.1 794.3 881.0 977.2 1084.0
Quik-Call II
The duration and spacing of the tones depend on the Quik-Call II format being used. The formats supported are listed in Table 2-3.
Table 2-3
Quick-Call II Timing (Seconds)

Tone & Voice K347AB Tone Only K347AC
0.9 1.1 0.4 0.0 0.8 --1.2 1.2
Normal Call
Pre-Tone Delay Intercall Gap Tone A Duration Intertone Gap Tone B Duration Pre-Warble Delay Warble Duration Talk Timer 0.9 1.1 1.0 0.0 3.0 1.2
Battery Saver K347AD

0.9 1.1 2.7 0.0 0.8
Competitive K347E
0.9 1.1 2.7 0.0 0.8 1.3 2.0 1.2
Long Tone B Group Call

Pre-Tone Delay and lntercall Gap Tone A Duration Pre-Warble Delay Warble Duration Talk Timer
Tone & Voice

0.9 8.0 1.2
Tone Only
0.9 8.0 --1.2
Battery Saver
0.9 8.0
Competitive
0.9 3.5 1.3 2.0
1.2
1.2
NOTE: Warble is 100 milliseconds of 800 Hz alternated with 100 milliseconds of 1500 Hz.
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NOTE Group call is selected when tone frequencies A and B are equivalent.
Quik-Call II translations
Procedure for converting tone frequency to keypad code
1.
Find tones in Table 2-4. TONE A = 470.5 TONE B = 1027.5 Group = 3 Group = 9 Row =7 Row =C
2.
Write digits in form: TONE A GROUP 3 TONE B GROUP 9 TONE A ROW 7 TONE B ROW C
3.
Convert column digits to paging prefix using Table 2-5. 3 9 ======> 2 B
4.
Append row digits in Step 2 to prefix digits in Step 3. 2B7C
Procedure for converting keypad code to tone frequency

1.
Write down keypad code. 2B7C
2.
Convert prefix digits to column data using Table 2-5. 2 B ======> 3 9
3.
Write column data prefix from Step 2 and append last two digits from Step 1. 397C
4.
Digits in step 3 are in form: TONE A GROUP, TONE B GROUP, TONE A ROW, TONE B ROW. TONE A is in GROUP 3, ROW 7 TONE B is in GROUP 9, ROW C
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CENTRACOM Gold Series Central Electronics Bank Maintentance Manual
Chapter 2 Paging Paging/signalling specifications
5.
Find tones in 2-4. TONE A = 470.5 TONE B = 1027.5 TONE B is in GROUP 9, ROW C
Table 2-4 Tone Frequency Assignments (in Hz) ENTRY 0 1 2 3 4 5 6 7 8 9 A B C D E F ENTRY 0 1 2 3 4 5 6 7 8 9 A B C D E F GROUP #0 330.5 349.0 368.5 389.0 410.8 433.7 457.9 483.5 510.5 539.0 1500.0 1550.0 1600.0 1650.0 1800.0 1950.0 GROUP #8 682.5 592.5 757.5 802.5 847.5 892.5 937.5 547.5 727.5 637.5 1192.5 472.5 487.5 502.5 742.5 982.5 GROUP #1 569.1 600.9 634.5 669.9 707.3 746.8 788.5 832.5 879.0 928.1 2856.0 2640.0 2440.0 2255.0 2084.0 1926.0 GROUP #9 652.5 607.5 787.5 2840.0 877.5 922.5 967.5 517.5 562.5 697.5 997.5 1207.5 1027.5 1042.5 1057.5 1077.5 GROUP #2 1092.4 288.5 296.5 304.7 313.0 953.7 979.9 1006.9 1034.7 1063.2 625.0 1695.0 1520.0 1405.0 1299.0 1201.0 GROUP #A 667.5 712.5 772.5 817.5 862.5 907.5 952.5 532.5 577.5 622.5 1087.5 1102.5 1117.5 1132.5 1147.5 1177.5 GROUP #3 321.7 339.6 358.6 378.6 399.8 422.1 445.7 470.5 496.8 524.6 1110.0 1026.0 949.5 735.0 825.0 749.0 GROUP #B 1743.0 1820.0 1901.0 1985.0 2073.0 2164.0 2260.0 2361.0 2465.0 2575.0 2688.0 2807.0 2932.0 3062.0 294.7 307.8 GROUP #4 553.9 584.8 617.4 651.9 688.3 726.8 767.4 810.2 855.5 903.2 900.0 643.0 672.0 701.0 732.0 765.0 GROUP #C 1220.0 335.6 350.5 366.0 382.0 399.2 416.9 435.3 454.6 474.8 495.8 1120.0 540.7 564.7 589.7 615.8 GROUP #5 1122.5 1153.4 1185.2 1217.8 1251.4 1285.8 1321.2 1357.6 1395.0 1433.4 799.0 834.0 871.0 910.0 1070.0 992.0 GROUP #D 358.9 398.1 441.6 489.8 543.3 602.6 668.3 741.3 822.2 912.0 1011.6 1122.1 1190.0 1265.0 1291.4 1355.0 GROUP #6 1472.9 1513.5 1555.2 1598.0 1642.0 1687.2 1733.7 1781.5 1830.5 1881.0 1036.0 1082.0 1130.0 1180.0 1232.0 1170.0 GROUP #E 371.5 412.1 457.1 507.0 562.3 623.7 691.8 767.4 851.1 944.1 1047.1 1161.4 1400.0 1430.5 1450.0 2100.0 GROUP #7 1930.2 1989.0 2043.8 2094.5 2155.6 2212.2 2271.7 2334.6 2401.0 2468.2 1344.0 1403.0 1465.0 1530.0 1280.0 1669.0 GROUP #F 346.7 384.6 426.6 473.2 524.8 582.1 645.7 716.1 794.3 881.0 977.2 1084.0 312.6 2250.0 2610.0 DC
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Table 2-5
Paging Group to Prefix Conversion

X5
45 46 47 48 49 20 09 89 8A BC 9A A2 A8 C9 E3 FD
X0
0X 1X 2X 3X 4X 5X 6X 7X 8X 9X AX BX CX DX EX FX 11 16 32 24 22 40 56 52 7C 80 BF 9D A3 C4 DE F8
X1
13 12 34 10 26 41 58 54 7D 8E C0 9E A4 C5 DF F9
X2
31 33 39 36 38 42 03 83 7E 8F C1 9F A5 C6 E0 FA
X3
23 19 35 14 18 43 05 85 7F BA C2 A0 A6 C7 El FB
X4
21 25 37 17 15 44 07 87 B9 BB C3 Al A7 C8 E2 FC
X6
55 57 02 04 06 08 01 50 A9 AB AD AF B1 CA E4 FE
X7
51 53 82 84 86 88 59 81 AA AC AE BO B2 CB E5 FF
X8
0A 0F 1E 2A 2F 30 4C 5B 60 61 65 B7 6E CC E6 27
X9
0B 1A 1F 2B B6 3E 4D 5C 63 62 66 6A 6F CD E7 28
XA
0C 1B B3 2C 3A 3F 4E 50 67 68 64 6B B8 CE E8 29
XB
0D 1C B4 2D 3B 4A 4F 5E 8B BD 9B 6C 7A CF E9 30
XC
0E 1D B5 2E 3C 4B 5A 5F 8C BE 9C 6D 7B D0 EA 69
XD
D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD 97 93 94
XE
EB EC ED EE EF F0 Fl F2 F3 F4 F5 F6 F7 91 98 96
XF
70 71 72 73 74 75 76 77 78 79 80 90 00 92 95 99
Prefix to Paging Group Conversion

0X 1X 2X 3X 4X 5X 6X 7X 8X 9x AX BX CX DX EX FX CF 31 55 FB 50 76 88 0F AF BF B3 B7 A1 DC E2 5E 66 00 04 02 51 07 98 1F 77 DE B4 C6 A2 0D E3 6E 26 11 40 20 52 70 99 2F 27 DF B5 C7 A3 1D E4 7E 62 01 03 12 53 17 89 3F 72 ED C0 2A A4 2D E5 8E 36 33 30 21 54 71 AA 4F 37 FD C1 2B D0 3D E6 9E 63 44 14 23 05 06 A8 5F 73 EF C2 2C D1 4D E7 AE 46 10 41 32 15 60 A9 6F 47 FE C3 49 D2 5D E8 BE 64 34 F8 24 25 16 8A 7F 74 DD C4 B8 D3 6D E9 CE 56 43 F9 42 35 61 9A 8F 57 EE C5 CA D4 7D EA F0 65 13 FA 22 45 67 FC 9F 75 FF 86 84 D5 8D EB F1 08 19 38 4A 5B 6C B9 CB 85 A5 87 93 D6 9D EC F2 09 1A 39 4B 5C 78 BA CC 8B AB 96 94 D7 AD 0E F3 0A 1B 3A 4C 68 79 BB 80 8C AC 97 95 D8 BD 1E F4 0B 1C 3B 58 69 7A BC 81 90 B0 A6 9B D9 CD 2E F5 0C 28 3C 59 6A 7B C8 82 91 B1 A7 9C DA E0 3E F6 18 29 48 5A 6B 7C C9 83 92 B2 B6 A0 DB E1 4E F7
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Paging
Touch code format

In touch code format the occurrence of a group call is determined by the number of digits that the operator enters into the keypad. If only one digit is entered, then a group call is placed. The formats supported are listed in Table 2-6. Row and column frequencies are generated simultaneously as shown in Table 2-7.
Table 2-6
Touch Code Format

Normal Digital Dial
Pre-tone delay Tone burst duration Delay between tones
800 mS 200 mS 200 mS
Touch Code Group Call

Pre-tone delay Tone burst duration 800 mS 5000 mS
Table 2-7
Touch Code Tone Frequencies

COL2 1336 Hz
2 5 8 0
COL1 1209 Hz
1 4 7 *F
COL3 1477 Hz
3 6 9 #E
COL4 1633 Hz
A B C D Row 1 Freq = 697 Hz Row 2 Freq = 770 Hz Row 3 Freq = 852 Hz Row 4 Freq = 941 Hz
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Digital dial format

Table 2-8
Digital Dial Format

Normal Digital Dial
Pre-tone delay Interdigit tone duration Dialing tones interruption Interrupt spacing
800 mS 500 mS 40 mS 60 mS
Digital dial formats include:

1. 2.
1500 Hz tone interrupted by dc (option K582) 2805 Hz tone interrupted by dc (option K355)
Single tone format

Table 2-9
Single Tone Formats
Normal Single tone Timing

Pre-tone delay Tone duration 800 mS or 1500 mS 500 mS or 1500 mS
Tone duration of the single tone format is an option set through the Console Database Manager. The frequency of the transmitted tone depends on the single keypad digit pressed by the operator when requesting single tone format. The relative frequencies are given in Table 2-10.
Table 2-10
Tone Output Frequencies

Tone Frequency (Hz)
750 900 1050 1200 1350 1500 1650 1800 1950 2100
Keypad Digit
0 1 2 3 4 5 6 7 8 9
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Chapter 2
Paging
Table 2-10
Tone Output Frequencies (continued)

Tone Frequency (Hz)
2250 2400 2550 2700 2850
Keypad Digit
A B C D E
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Paging conversions
Paging conversions
Quik-Call I
The K561 option adds the capability to generate 36 Quik-Call I tones to the Gold Series console. Most systems currently using Quik-Call I probably use only one of the three available groups of 12 tones. Each group of 12 tones is either of the A, B or Z Series. To determine the appropriate series, look at the letters on the reeds inside the existing encoder. To encode a tone sequence, five digits must be entered. The first digit determines the series, and the next four digits indicate the four tones to be sent. The following illustrates the digit which represents a particular series: p p p Series A Series B Series Z 0 1 2
To convert paging codes from an older series encoder to the Gold Series Encoder, refer to Table 2-11.
Table 2-11
Gold Series Tone Conversions

CENTRACOM I Encoder, B1339A
0 1 2 3 4 5 6 7 8 9 C U 0 1 2 3 4 5 6 7 8 9 A B
Very Old Encoder; Buttons labeled C to P

C D E F G H I K L M N P
Gold Series Encoder
In order to send a group call, five digits must also be entered. The sequence is x-y-z-y-z, where x denotes the series (0 for A Series, 1 for B Series, 2 for Z Series) and y and z are tones 0 through B. Note the pattern of repetition.
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Chapter 2
Paging
Quik-Call II
Quik-Call II
Use of common tones
CENTRACOM Gold Series has the ability to provide the 229 most commonly used Motorola, Bramco, G.E., Plectron, Howell, Comex, and Federal tones between 288.5 and 3062.0 Hz. It also includes the Quik-Call I tones which can be used in a paging sequence known as Code Plan Y. These are handled with Quik-Call II codes 9100 through 9999. There are four Quik-Call II formats available: K347AB (Tone and Voice), K347AC (Tone Only), K347AD (Battery Saver) and K347E (Competitive).
Use of uncommon tones

The 1 + 1 encoding technique is used for paging by many manufacturers. The Gold Series encoder contains all the tones commonly used by major manufacturers in the field. Even the Quik-Call I tones are included, since many systems have been converted from a 2 + 2 sequence to a 1 + 1 sequence without changing tones. Pagers generally use active filters or reed decoders to delineate the paging frequency. This requires that the tone received must be within 0.1% of the frequency to be decoded. The Gold Series system does not include every tone employed by all manufacturers. Refer to Table 2-12 for substitution tones.
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Chapter 2 Quik-Call II
Paging
Table 2-12
Substitution Table for Uncommon Frequencies Not Included: Use Instead:

Code # P41 G44 P52 R52 F02 R50 R48 F04 R45 R44 F05 R43 R42 F06 P10 G34 R39 G48 R35 R34 P17 B15 R29 R27 F14 R23 R16 R14 R12 321.4 457.5 517.8 653.0 692.0 700.0 750.0 810.0 832.0 862.0 877.0 892.0 923.0 949.0 950.0 1012.5 1025.0 1162.5 1177.0 1219.0 1287.0 1320.0 1449.0 1553.0 1780.0 1784.0 2274.0 2437.0 2612.0 Freq (Hz) 321.7 457.1 517.5 652.5 691.8 701.0 749.0 810.2 832.5 862.5 877.5 892.5 922.5 949.5 949.5 1011.6 1026.0 1161.4 1177.5 1220.0 1285.8 1321.2 1450.0 1555.2 1781.5 1781.5 2271.7 2440.0 2610.0 Freq (Hz) 140 EB G01 G10 JB P03 F03 157 127 G24 G25 G26 G28 NA F07 PB G49 B02 195 196 B18 172 177 177 206 F18 Code #
Manufacturer Code Federal GE Plectron Reach Federal Reach Reach Federal Reach Reach Federal Reach Reach Federal Plectron GE Reach GE Reach Reach Plectron Bramco Reach Reach Federal Reach Reach Reach Reach
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Chapter 2
Paging
Quik-Call II
Conversion of existing encoders to Gold Series

While most encoders in the field are two or three digit, paging entry in the Gold Series is four digit. The following sections describe how to convert paging codes.
Existing Motorola 4-digit encoder

Once the code plans of the four-digit Motorola encoder are known, refer to Table 2-13 and perform the following steps:
1.
The letters of the various CODE PLANS are shown. Find the letter that applies to the system across the top of the columns on Table 2-13. Come down that column until you line up with the current prefix that the system uses. (The prefix is the two digits pressed before the final two digits of the pager address is entered.) At the point where the CURRENT PREFIX row and the CODE PLAN column meet, there are two numbers separated by a comma. These numbers denote two of the code groups used in the decoder and the order in which they are used to signal units starting with this current prefix. Write these numbers down. In the CODE GROUPS column of Table 2-14, look up the code groups determined in step 2, making certain that the numbers are in the same order. Read the numbers which are in the Gold Series Prefix column; these are the first two digits that must be entered through the keypad. Note that the final two digits almost never change.
2.
3. 4.
5.
Some systems may currently be using more than one prefix and, consequently, have more than one new prefix. Example: The customer has a G/R code plan and is using 0300 to 0399, 0500 to 0599, 0800 to 0899 and 1900 to 1999 for the pagers, it can be determined from Table 2-13 that 03xx on a plan G/R encoder yields 3,3 (tone group 3 is used for the first tone, and tone group 3 is used for the second tone). Next, referring to Table 2-14 and referencing the CODE GROUPS column, it is found that 3,3 indicates 39 as the Gold Series PREFIX for the first hundred pagers. Therefore, where the operator previously used 0-3-2-4, he or she now uses 3-9-2-4. Similarly, 05xx yields 5,5 which, through the above process, indicates that 15 is the new prefix for the second hundred pagers. 08xx yields 3,5 which leads to 37 as the new prefix for the third hundred pagers. 19xx yields 6,4, resulting in a new prefix of 43 for the last hundred pagers.
NOTE A code plan of X indicates a non-standard reed arrangement. In this case, get a list of tones used in the current encoder (check the old pager or encoder order acknowledgments) and work backwards from the tone tables using the procedure outlined in the Conversion of Miscellaneous Plan X Motorola Encoders paragraph.
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Paging
Table 2-13
4-Digit Encoder to Code Groups Conversion Chart

H/Q J/P K/N L/M Y
Code Plan: Current Prefix

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 27 28 29 30
1,1 1,3 3,3 3,1 1,6 6,6 6,1 3,6 6,3 4,2 2,4 2,2 4,2 4,4 5,5 2,5 4,5 5,4 5,2
1,1 1,4 4,1 4,4 5,5 1,5 4,5 5,4 5,1 4,2 2,3 2,2 3,3 3,2 2,6 6,6 6,2 3,6 6,3
1,1 1,4 4,1 4,4 1,6 6,6 6,1 4,6 6,4 4,2 2,3 2,2 3,3 3,2 5,5 2,5 5,2 3,5 5,3
1,1 1,5 5,1 1,6 5,5 6,6 6,1 5,6 6,5 4,2 2,3 2,2 3,3 4,4 3,2 2,4 4,2 3,4 4,3 4,5 5,4 1,2 2,1
A,A B,B Z,Z A,B A,Z B,A Z,A B,Z Z,B
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Chapter 2
Paging
Quik-Call II
Table 2-13
4-Digit Encoder to Code Groups Conversion Chart (continued)

B/W C/V
1,1 2,2 1,2 4,4 1,4 2,1 4,1 2,4 4,2 4,2 3,5 5,3 3,3 3,6 5,5 6,6 6,3 5,6 6,5
D/U
1,1 2,2 1,2 1,5 5,5 2,1 5,1 2,5 5,2 4,2 3,4 4,3 3,3 4,4 3,5 6,6 6,3 4,6 6,4
E/T
1,1 2,2 1,2 2,1 1,6 6,6 6,1 2,6 6,2 4,2 3,4 4,3 3,3 4,4 5,5 3,5 4,5 5,4 5,3
F/S
1,1 1,3 3,3 4,4 3,1 1,4 4,1 3,4 4,3 4,2 2,5 2,2 5,2 2,6 5,5 6,6 6,2 5,6 6,5
G/R
1,1 1,3 3,3 3,1 5,5 1,5 5,1 3,5 5,3 4,2 2,4 2,2 4,2 4,4 2,6 6,6 6,2 4,6 6,4
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
2,4 1,1 2,2 3,3 1,2 1,3 2,1 3,1 2,3 3,2 4,2 4,6 6,4 5,6 4,4 5,5 6,6 4,5 5,4 6,5 6,6 1,5 5,1 1,4 4,1 2,5 5,2 4,5 5,4 1,2 2,1 1,3 3,1 2,3 3,2 3,4 4,3 3,5 5,3 3,3 6,1 6,2 6,3 6,4 6,5
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Paging
Table 2-13
4-Digit Encoder to Code Groups Conversion Chart (continued)

B/W C/V D/U E/T F/S G/R
45 46 47 48 49 60 61 62 63 64 65 66 67 68
1,6 2,6 3,6 4,6 5,6 G1,G1 G2,G1 G2,G2 G1,G2 G3,G3 G3,G1 G3,G2 G1,G3 G2,G3 The G means GE groups 1, 2 or 3.
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Chapter 2
Paging
Quik-Call II
Table 2-14
Code Groups to Gold Series Prefix Conversion Table

Gold Series Prefix
11 13 31 23 21 45 55 51 0A 0B 0C 0D 0# D1 #B 70 32 34 39 35 37 47 02 82 1# 1* B3 B4 B5 D3 #D 72 22 26 38 18 15 49
Code Groups
1,1 1,2 1,3 1,4 1,5 1,6 1,10 1,11 1,G1 1,G2 1,G3 1,P1 1,P2 1,A 1,B 1,Z 3,1 3,2 3,3 3,4 3,5 3,6 3,10 3,11 3,G1 3,G2 3,G3 3,P1 3,P2 3,A 3,B 3,Z 5,1 5,2 5,3 5,4 5,5 5,6
Code Groups
2,1 2,2 2,3 2,4 2,5 2,6 2,10 2,11 2,G1 2,G2 2,G3 2,P1 2,P2 2,A 2,B 2,Z 4,1 4,2 4,3 4,4 4,5 4,6 4,10 4,11 4,G1 4,G2 4,G3 4,P1 4,P2 4,A 4,B 4,Z 6,1 6,2 6,3 6,4 6,5 6,6
Gold Series Prefix

16 12 33 19 25 46 57 53 0* 1A 1B 1C 1D D2 #C 71 24 10 36 14 17 48 04 84 2A 2B 2C 2D 2# D4 ## 73 40 41 42 43 44 20
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Paging
Table 2-14
Code Groups to Gold Series Prefix Conversion Table (continued)

Gold Series Prefix
06 86 2* B6 3A 3B 3C D5 #* 74 56 58 03 05 07 09 01 59 4C 4D 4# 4* 5A D7 *1 76 7C 7D 7# 7* B9 8A A9 AA 60 63 67 8B
Code Groups
5,10 5,11 5,G1 5,G2 5,G3 5,P1 5,P2 5,A 5,B 5,Z 10,1 10,2 10,3 10,4 10,5 10,6 10,10 10,11 10,G1 10,G2 10,G3 10,P1 10,P2 10,A 10,B 10,Z G1,1 G1,2 G1,3 G1,4 G1,5 G1,6 G1,10 G1,11 G1,G1 G1,G2 G1,G3 G1,P1
Code Groups
6,10 6,11 6,G1 6,G2 6,G3 6,P1 6,P2 6,A 6,B 6,Z 11,1 11,2 11,3 11,4 11,5 11,6 11,10 11,11 11,G1 11,G2 11,G3 11,P1 11,P2 11,A 11,B 11,Z G2,1 G2,2 G2,3 G2,4 G2,5 G2,6 G2,10 G2,11 G2,G1 G2,G2 G2,G3 G2,P1
Gold Series Prefix

08 88 3D 3# 3* 4A 4B D6 *0 75 52 54 83 85 87 89 50 81 5B 5C 5D 5# 5* D8 *2 77 8D 8# 8* BA BB BC AB AC 61 62 68 BD
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Chapter 2
Paging
Quik-Call II
Table 2-14

Gold Series Prefix
8C D9 *3 78 B* C0 C1 C2 C3 9A AD A# 65 66 64 9B 9C DB *5 80 A3 A4 A5 A6 A7 A8 B1 B2 6# 6* B8 7A 7B DD *7 00 D# D*
Code Groups
G1,P2 G1,A G1,B G1,Z G3,1 G3,2 G 3,3 G3,4 G3,5 G3,6 G3,10 G3,11 G3,G1 G3,G2 G3,G3 G3,P1 G3,P2 G3,A G3,B G3,Z P2,1 P2,2 P2,3 P2,4 P2,5 P2,6 P2,10 P2,11 P2,G1 P2,G2 P2,G3 P2,P1 P2,P2 P2,A P2,B P2,Z B,1 B,2
Code Groups
G2,P2 G2,A G2,B G2,Z P1,1 P1,2 P1,3 P1,4 P1,5 P1,6 P1,10 P1,11 P1,G1 P1,G2 P1,G3 P1,P1 P1,P2 P1,A P1,B P1,Z A,1 A,2 A,3 A,4 A,5 A,6 A,10 A,11 A,G1 A,G2 A,G3 A,P1 A,P2 A,A A,B A,Z Z,1 Z,2
Gold Series Prefix

B# DA *4 79 9D 9# 9* A0 A1 A2 A* B0 B7 6A 6B 6C 6D DC *6 90 C4 C5 C6 C7 C8 C9 CA CB CC CD C# C* D0 97 91 92 *8 *9
68P 81095E 50- A 11/30/2000
2-19
Paging
Table 2-14

Gold Series Prefix
#0 #1 #2 #3 #4 #5 #6 #7 #8 #9 #A 93 98 95
Code Groups
B,3 B,4 B,5 B,6 B10 B,11 B,G1 B,G2 B,G3 B,P1 B,P2 B,A B,B B,Z
Code Groups
Z,3 Z,4 Z,5 Z,6 Z,10 Z,11 Z,G1 Z,G2 Z,G3 Z,P1 Z,P2 Z,A Z,B Z,Z
Gold Series Prefix

*A *B *C *D *# ** 27 28 29 30 69 94 96 99
Existing 3-digit encoder

Determine which code plan the 3-digit Motorola encoder has and perform the following steps:
1.
Look up the code plan letter that applies to the system across the top of the columns in Table 2-15. Find the row that has the number that the system used. Find the intersection of the OLD NUMBER row and the CODE PLAN column. The numbers here are the new prefixes. Push this two button prefix before pushing xy.
3-Digit Encoder to Series H Prefix Conversion Table
B C D New Prefixes
19 11 12 39 13 31 16 32 33 34 11 12 13 14 23 16 24 19 10 11 12 13 21 15 16 22 25 26 11 12 13 16 45 20 40 46 41 11 31 39 14 32 23 24 35 36
2.
Table 2-15
Code Plan: Old No.

0xy 1xy 2xy 3xy 4xy 5xy 6xy 7xy 8xy 9xy
2-20
6 8 P8 1 0 9 5 E5 0 - A 1 1/ 30 /2 00 0
Chapter 2
Paging
Quik-Call II
Table 2-15
3-Digit Encoder to Series H Prefix Conversion Table (continued)

G H J New Prefixes
11 31 39 32 15 21 22 37 38 11 31 39 32 45 20 40 47 42 11 23 24 14 15 21 17 18 22 11 23 24 14 45 20 40 48 43 11 21 22 45 15 20 40 49 44
Code Plan: Old No.

Code Plan: Old No.

P New Prefixes
10 33 12 39 14 34 19 10 35 36
10 33 12 39 34 15 25 26 37 38
10 33 12 39 34 46 20 41 47 42
10 19 12 10 14 15 25 17 18 26
10 19 12 10 14 46 20 41 48 43
Code Plan: Old No.

U New Prefixes
10 25 12 26 46 15 20 41 49 44
10 35 36 39 14 15 37 17 18 38
10 35 36 39 14 47 20 42 48 43
10 37 38 39 47 15 20 42 49 44
10 48 43 49 14 15 20 17 18 44
68P 81095E 50- A 11/30/2000
2-21
Paging
Existing Motorola 2-digit encoder

1.
Read the numbers on the reeds inside the encoder. These are Motorola reed reference numbers or code numbers. Refer to the CODE column of Table 2-16 to determine which group they are from. Most old encoders have 3 to 5 reeds, all from the same group. If you cannot find any reed numbers, but can find the frequencies, skip to the Conversion of Miscellaneous Plan X Motorola Encoders paragraph.
2.
Example: Assume that reed numbers 138, 108, 139 and 109 are in the encoder. By looking up these numbers in Table 2-16, it can be determined that they are all group 3 reeds, and that they correspond to buttons 1 through 4, respectively. Since the reeds are all from group 3, the first and second tone come from the same group, which, in this example, is 3. Refer to Table 2-14. Look up 3, 3 in the CODE Groups column. The proper Gold Series prefix is 39. Therefore, Unit #34 is now paged by entering 3-9-3-4.
Existing GE encoders
If you are replacing a GE encoder with a Gold Series encoder, note the following:
1.
GE uses a diagonal tone, which is automatically inserted (in lieu of the first tone) where the equivalent Motorola encoder would send a long tone B group call. This conflict affects the 60 Prefixes (group G1), the 62 Prefixes (group G2), and the 64 Prefixes (group G3). (The other prefixes use a second tone from a different group than the first tone so there is no need for a diagonal tone.) If, for example, the system uses GE group #1 and the operator wanted to call unit xy, he or she would enter 60xy. There is no problem except when x and y are the same number. The code sequence 6011, for example, calls for a GE diagonal tone where the Motorola encoders want to send a long tone B group call. Whenever this situation arises, the diagonal tone can be programmed by using the following chart:
Instead of Codes:
60xx 62yy except 6233 6233 64zz
Use:
60#x 63#y 7D#7 68#z
Example:
6088 becomes 60#8 6299 becomes 63#9 6233 becomes 7D#7 6455 becomes 68#5
2-22
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Chapter 2
Paging
Quik-Call II
2.
Since GE and Motorola have one tone in common (#3 of the 2nd group), rather than repeating this tone, Motorola uses the space for another tone. To avoid the substituted tone in group 2, refer to the following chart:
Instead of Codes:
613a 63b3 66c3 683d
Use:
0*7a 7Db7 C0c7 1B7d
Example:
6134 becomes 0*74 6353 becomes 7D57 6683 becomes C087 6839 becomes 1B79
If the GE encoder does not follow the normal tone line-up, or if there is uncertainty, refer to the following paragraph.
Conversion of miscellaneous plan X Motorola encoders
NOTE The following section contains information to be used when the encoding requirements are unique.
1.
To effect the conversions, go directly to the encoder and write down the tones that are used. If the system has only a few pagers, it may be easier to write down the specific sequences by reading the tone frequencies on the reeds or on the back of each pager unit. Refer to Table 2-17 to determine the group and button numbers associated with those tones. Refer to Table 2-14 to find the correct Gold Series prefixes.
2.
3.
Example: To find the requirements for unit #412, first refer to the following chart which gives the tones a unit designation. Next, look up these tones in Table 2-17. You will be find that 339.6 Hz is in group 4, button 1. 358.6 Hz in group 4, button 2. Therefore, the last two digits will be 1-2, as indicated by the buttons.
68P 81095E 50- A 11/30/2000
2-23
Paging
Unit Designation
#412 #434 #2 #5 Cancel Fire EMS Siren
Tone 1
339.6 669.9 1985 765 992 2807 2465 2575
Tone 2
358.6 903.2 1232 1180 1036 1082 871 950
To find the correct prefix, first note that both tones are from group 4. Then, look up 4,4" in the Code Groups column of Table 2-14. For 4,4, the Gold Series Prefix is 14. Therefore, Unit #412 is now paged by entering 1-4-1-2. Example: The conversion for Unit #434 is determined in the same manner. Using Table 2-17, the 669.9 Hz tone is found in group 2 button 3, while the 903.2 Hz tone is found in group 5 button 9. The last two digits, therefore, are 3-9. The associated prefix will be one which uses groups 2 and 5 in that order. Referring next to the Code Groups column of Table 2-14, it can be seen that 25 is the proper prefix. Therefore, the digits to enter are 2-5-3-9 to page Unit #434.
2-24
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Chapter 2
Paging
Quik-Call II
Table 2-16
Gold Series Encoder Tone Table Group 1 Freq Code

110 111 112 113 114 115 116 117 118 119 R28 + B20 CQ + B21 B22 DQ
Button
Group 2 Freq
569.1 600.9 634.5 669.9 707.3 746.8 788.5 832.5 879.0 928.1 2856.0 2640.0 2440.0 2255.0 2084.0 1926.0
Group 3 Code Freq

1092.4 288.5 296.5 304.7 313.0 953.7 979.9 1006.9 1034.7 1063.2 625.0 1695.0 1520.0 1405.0 1299.0 1201.0 F13 F12 + B09 F11 F10 F09
Group 4 Code Freq

321.7 339.6 358.6 378.6 399.8 422.1 445.7 470.5 496.8 524.6 1110.0 1026.0 949.5 735.0 825.0 749.0 F03
Code
140 + P41 141 142 143 144 145 146 147 148 149 F08 F07 + R39 F06 + P10
0 1 2 3 4 5 6 7 8 9 A B C D # *
330.5 349.0 368.5 389.0 410.8 433.7 457.9 483.5 510.5 539.0 1500.0 1550.0 1600.0 1650.0 1800.0 1950.0
120 121 122 123 124 125 126 127 + G22 + R45 128 129 F20 F19 F18 F17 F16 F15
189 138 108 139 109 160 130 161 131 162
Button Freq
0 1 2 3 4 5 6 7 8 9 A B C D # * 553.9 584.8 617.4 651.9 688.3 726.8 767.4 810.2 855.5 903.2 900.0 643.0 672.0 701.0 732.0 765.0
Group 5 Code
150 151 152 153 154 155 156 + KB 157 + F04 158 159
Group 6 Freq
1122.5 1153.4 1185.2 1217.8 1251.4 1285.8 1321.2 1357.6 1395.0 1433.4 799.0
Group 10 Code Freq

1472.9 1513.5 1555.2 1598.0 1642.0 1687.2 1733.7 1781.5 1830.5 1881.0 1036.0 1082.0 1130.0 1180.0 1232.0
Group 11 Freq
1930.2 1989.0 2043.8 2094.5 2155.6 2212.2 2271.7 2334.6 2401.0 2468.2 1344.0 1403.0 1465.0 1530.0 1280.0 1669.0 P23
Code
170 171 172 173 + P22 174 175 176 177 + F14 178 179 P12 P13 P14 P15 P16
Code
200 201 202 203 204 205 206 + R16 207 208 209 P18 P19 P20 P21
190 191 192 193 194 195 + P17 196 + B15 197 198 199 P06 P07 P08 P09
P01 P02 P03 P04 P05
834.0 871.0 910.0 1070.0 992.0
P11
1170.0
68P 81095E 50- A 11/30/2000
2-25
Paging
Table 2-16
Gold Series Encoder Tone Table (continued) Group G1 Freq Code

G12 G06 G17 G20 G23 G26 + R43 G29 G03 G15 G09 G50 G43 G42 G41 G16 G32
Button
Group G2 Freq
652.5 607.5 787.5 2840.0 877.5 922.5 967.5 517.5 562.5 697.5 997.5 1207.5 1027.5 1042.5 1057.5 1077.5 G25 + F05 G28 + R42 G31 G01 + P52 G04 G13 G33 G51 G35 G36 G37 G38
Group G3 Freq
667.5 712.5 772.5 817.5 862.5 907.5 952.5 532.5 577.5 622.5 1087.5 1102.5 1117.5 1132.5 1147.5 1177.5
Group P1 Freq
1743.0 1820.0 1901.0 1985.0 2073.0 2164.0 2260.0 2361.0 2465.0 2575.0 2688.0 2807.0 2932.0 3062.0 294.7 307.8 P40
Code
G10 + R52 G07 G19
Code
G11 G14 G18 G21 G24 + R44 G27 G30 G02 G05 G08 G39 G40 G45 G46 G47 G49+R35
Code
P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37
0 1 2 3 4 5 6 7 8 9 A B C D # *
682.5 592.5 757.5 802.5 847.5 892.5 937.5 547.5 727.5 637.5 1192.5 472.5 487.5 502.5 742.5 982.5
Button
Group P2 Freq Code

B02 + R34 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 B11 P53 P54 P55 P56
Group A Freq
358.9 398.1 441.6 489.8 543.3 602.6 668.3 741.3 822.2 912.0 1011.6 1122.1 1190.0 1265.0 1291.4 1355.0
Group B Freq
371.5 412.1 457.1 507.0 562.3 623.7 691.8 767.4 851.1 944.1 1047.1 1161.4 1400.0 1430.5 1450.0 2100.0
Group Z Code Freq

346.7 384.6 426.6 473.2 524.8 582.1 645.7 716.1 794.3 881.0 977.2 1084.0 312.6 2250.0 2610.0 Not R12 Usable
Code
CA DA EA FA GA HA JA KA LA MA NA + G34 PA B12 B14 B03 B16
Code
CZ DZ EZ FZ GZ HZ JZ KZ LZ MZ NZ PZ BZ
0 1 2 3 4 5 6 7 8 9 A B C D # *
NOTES:
1220.0 335.6 350.5 366.0 382.0 399.2 416.9 435.3 454.6 474.8 495.8 1120.0 540.7 564.7 589.7 615.8
CB DB EB + G44 FB GB HB JB + F02 KB + 156 LB MB NB PB + G48 B17 + R30 B07 B18 + R29
1. All frequencies in Hz.
2-26
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Chapter 2
Paging
Quik-Call II
Table 2-17
Gold Series Encoder Frequencies

Group
3 P1 3 3 P1 Z 3 4 1 P2 4 Z 1 P2 4 A P2 1 B 4 P2 Z 1 A P2 4 1 B P2 4 Z 1 P2 A 4 1 # 2 3 * C 4 0 0 1 1 0 1 2 2 0 3 2 0 3 4 1 3 1 5 4 4 1 6 5 2 5 7 2 6 108 139 P40 BZ 109 P4 1: USE 321.7 140 110 P42 141 CZ 111 P43 142 CA P44 112 CB 143 P34 DZ 113 DA P46 144 114 DB P47 145 EZ 115 P48 EA 146
Tone (Hz)
288.5 294.7 296.5 304.7 307.8 312.6 313.0 321.4 321.7 330.5 335.6 339.6 346.7 349.0 350.5 358.6 358.9 366.0 368.5 371.5 378.6 382.0 384.6 389.0 398.1 399.2 399.8 410.8 412.1 416.9 422.1 426.6 433.7 435.3 441.6 445.7
Button
138
Common Designator
68P 81095E 50- A 11/30/2000
2-27
Paging
Table 2-17
Gold Series Encoder Frequencies (continued)

Group
P2 B 1 4 G1 Z P2 1 G1 A P2 4 G1 B 1 G2 4 Z G3 1 P2 A G1 5 B G2 P2 2 G3 Z 5 P2 G1 2 8 2 6 7 B 3 9 7 C 3 A 8 D 3 8 7 9 4 7 9 C 4 7 0 4 8 D 0 8 5 1 # 1 1
Tone (Hz)
454.6 457.1 457.5 457.9 470.5 472.5 473.2 474.8 483.5 487.5 489.8 495.8 496.8 502.5 507.0 510.5 517.5 517.8 524.6 524.8 532.5 539.0 540.7 543.3 547.5 553.9 562.3 562.5 564.7 569.1 577.5 582.1 584.8 588.9 589.7 592.5 600.9
Button
P49 EB
Common Designator
G44: USE 457.1 116 147 G43 FZ P50 117 G42 FA P51 148 G41 FB 118 G01 P52: USE 517.5 149 GZ G02 119 P53 GA G03 150 GB G04 P54 120 G05 HZ 151 R55 P55 G06 121
2-28
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Chapter 2
Paging
Quik-Call II
Table 2-17

Group
A G2 P2 5 G3 B 3 2 G1 5 Z 5 G2 G3 A 2 5 G1 5 B G2 5 2 G3 Z 5 G1 5 4 A 5 1 * 2 9 5 A 2 9 B 6 3 0 0 6 3 C 0 4 6 9 D 4 1 7 5 8 # D 7
Tone (Hz)
602.6 607.5 609.0 615.8 617.4 622.5 623.7 625.0 631.0 634.5 637.5 643.0 645.7 651.9 652.5 653.0 667.5 668.3 669.9 672.0 676.0 682.5 688.3 691.8 692.0 697.5 700.0 701.0 707.3 712.5 716.1 725.0 726.8 727.5 732.0 735.0 741.3
Button
HA G07 R54 P56 152 G08 HB R53 122 G09 P01 JZ 153 G10
Common Designator
R52: USE 652.5 G11 JA 123 P02 R51 G12 154 JB F02: USE 691.8 G13 R50: TRY 701.0 P03 124 G14 KZ R49 155 G15 P04 KA
68P 81095E 50- A 11/30/2000
2-29
Paging
Table 2-17

Group
G1 2 4 G1 5 5 B G3 G2 2 Z 6 G1 5 G3 A 4 2 6 G1 B 5 G3 6 G2 2 Z G1 5 # 5 * 2 * 6 7 2 2 6 8 A 3 7 3 8 # 7 B 4 8 8 4 C 4 8 9 5 A
Tone (Hz)
742.5 746.8 749.0 750.0 757.5 765.0 767.4 772.5 776.0 787.5 788.5 794.3 799.0 802.5 804.0 810.0 810.2 817.5 822.2 825.0 832.0 832.5 834.0 847.5 851.1 855.5 862.0 862.5 871.0 877.0 877.5 879.0 881.0 892.0 892.5 900.0
Button
G16 125 F03
Common Designator
R48: TRY 749.0 G17 P05 156 KB G18 R47 G19 126 LZ P06 G20 R46 F04: USE 810.2 157 G21 LA R45: USE 832.5 127; G22 P07 G23 LB 158 R44: USE 862.5 G24 P08 F05: USE 877.5 G25 128 MZ R43: USE 892.5 G26 -
2-30
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Chapter 2
Paging
Quik-Call II
Table 2-17

Group
5 G3 6 A G2 2 G1 B 4 G3 3 G2 Z 3 G 6 G2 3 A 4 G2 3 10 G2 B G2 3 6 G2 9 5 D 9 5 9 6 9 C 6 5 6 A 6 * * A 7 A B C 8 A D A # 9 # * G38
Tone (Hz)
903.2 907.5 910.0 912.0 922.5 923.0 928.1 937.5 944.1 949.0 949.5 950.0 952.5 953.7 956.0 967.5 977.2 979.9 982.5 990.0 992.0 997.5 1006.9 1011.6 1012.5 1025.0 1026.0 1027.5 1034.7 1036.0 1042.5 1047.1 1057.5 1061.0 1063.2 1070.0 1077.5
Button
159 G27 P09 MA G28
Common Designator
R42: USE 922.5 129 G29 MB F06 P10 G30 160 R41 G31 NZ 130 G32 R40 P11 G33 161 NA G34: USE 1011.6 R39: USE 1026.0 F07 G35 131 P12 G36 NB G37 R38 162
68P 81095E 50- A 11/30/2000
2-31
Paging
Table 2-17

Group
10 Z G3 3 G3 4 G3 P2 A 6 10 G3 G3 6 B 10 G3 10 6 A G1 3 G2 6 P2 10 6 A 11 6 B B A 0 B A C B B 0 C D # 1 B * * D 2 C A * B 3 0 # 4 D # 5 -
Tone (Hz)
1082.0 1084.0 1087.5 1092.4 1098.0 1102.5 1110.0 1117.5 1120.0 1122.1 1122.5 1130.0 1132.5 1137.0 1147.5 1153.4 1161.4 1162.5 1170.0 1177.0 1177.5 1180.0 1185.2 1190.0 1192.5 1201.0 1207.5 1217.8 1219.0 1220.0 1232.0 1251.4 1261.0 1265.0 1280.0 1285.8 1287.0
Button
P13 PZ
Common Designator
G39 189 R37 G40 F08 G45 B11 PA 190 P14 G46 R36 G47 191 PB G48: USE 1161.4 R35: USE 1177.5 G49 P15 192 B12 G50 F09 G51 193 R34: USE 1220.0 B02 #P16 194 R33 B14 195 P17: USE 1285.8
2-32
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Chapter 2
Paging
Quik-Call II
Table 2-17

Group
A 3 6 11 A 6 6 B 11 3 B 6 B 11 10 1 10 3 11 1 10 10 1 10 1 11 10 3 10 # # 6 A * 7 8 C B D D 9 # C 0 A 1 C D B 2 3 C 4 D * 5 B 6
Tone (Hz)
1291.4 1299.0 1306.0 1320.0 1321.2 1344.0 1352.0 1355.0 1357.6 1395.0 1400.0 1403.0 1405.0 1430.5 1433.4 1449.0 1450.0 1465.0 1472.9 1500.0 1513.5 1520.0 1530.0 1550.0 1553.0 1555.2 1598.0 1600.0 1608.0 1642.0 1650.0 1664.0 1669.0 1687.2 1695.0 1723.0 1733.7
Button
B03 F10 R32
Common Designator
B15: USE 1321.2 196 P18 R31 B16 197 198 B17; R30 P19 F11 B07 199 R29: USE 1450.0 B18 P20 170 B20; R28 171 B09; F12 P21 B21; CQ R27: TRY 1555.2 172 173 B22 R26 174 DQ R25 P23 175 F13 R24 176
68P 81095E 50- A 11/30/2000
2-33
Paging
Table 2-17

Group
P1 10 1 P1 10 10 P1 2 11 1 P1 11 11 P1 2 11 B 11 P1 11 Z 2 P1 11 11 P1 11 0 7 # 1 8 9 2 * 0 * 3 1 2 4 # 3 * 4 5 5 D D 6 6 7 7 8 F17 P30 206 R16: USE 2271.7 207 R15 P31 208
Tone (Hz)
1743.0 1780.0 1781.5 1784.0 1800.0 1820.0 1830.5 1847.0 1881.0 1901.0 1912.0 1926.0 1930.2 1950.0 1980.0 1985.0 1989.1 2043.8 2049.0 2073.0 2084.0 2094.5 2100.0 2121.0 2155.6 2164.0 2196.0 2212.2 2250.0 2255.0 2260.0 2271.7 2274.0 2334.6 2354.0 2361.0 2401.0
Button
P24
Common Designator
F14: USE 1781.5 177 R23: TRY 1781.5 P25 178 R22 179 P26 R21 F15 200 R20 P27 201 202 R19 P28 F16 203 R18 204 P29 R17 205
2-34
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Chapter 2
Paging
Quik-Call II
Table 2-17

Group
2 P1 11 P1 Z 2 P1 P1 G2 2 P1 P1 C 8 9 9 # B A B 3 A C D R12: USE 2610.0 F19 P34 R11 P35 F20 P36 P37
Tone (Hz)
2437.0 2440.0 2465.0 2468.2 2523.0 2575.0 2610.0 2612.0 2640.0 2688.0 2704.0 2807.0 2840.0 2856.0 2932.0 3062.0
Button
Common Designator
R14: USE 2440.0 F18 P32 209 R13 P33
68P 81095E 50- A 11/30/2000
2-35
Paging
2-36
6 8 P8 1 0 9 5 E5 0 - A 1 1/ 30 /2 00 0
3 3 Descriptor String
Assignments
About this chapter

This chapter describes how to manually generate descriptor strings for assignments. These manually generated descriptor strings are used to make assignments to an assignable module on a Classic operator position in addition to assignments available via the consoles alias list.
Section
Introduction Descriptor string types 3-2 3-7
Page

68P 81095E 50- A 11/30/2000- U P
3-1
Chapter 3
Descriptor String Assignments
Introduction
Introduction
Descriptor strings are a series of characters that the console needs in order to assign a channel to an assignable Display Channel Control Module (DCCM) or assignable Channel Control Window (CCW). On a Classic Console Operator position, to assign any assignable module via the keypad or mouse, a descriptor string of as many as 12 characters is used. The entered descriptor string is displayed where the clock display normally appears. You must refer to the As-Built documentation shipped with the control console in order to correctly determine the appropriate descriptor string for a specific channel available at your console. For the data used in the following examples, refer to the TRUNKING ID INFORMATION, MISCELLANEOUS INFORMATION, and PHONE LINE TERMINATIONS pages of the As-Built document for your system. Refer to Figure 3-1, 3-2, and 3-3. For calculating type I trunking descriptor strings, Table 3-1 will also be needed. If you are adding channels to your control console, you must obtain the same information from your Motorola Sales Representative.
3-2
6 8 P8 1 0 9 5 E5 0 - A 1 1/ 30 /2 00 0
Chapter 3
Descriptor String Assignments Introduction
The information required from Figure 3-1 is:

A.
The BID number Indicates the Fleet/Subfleet CCMs
B.
The SYS number Indicates the System
C.
The MAP letter Indicates the Size Code
D.
The FLT number Indicates the Fleet
E.
The S/F number Indicates the Subfleet
F.
The F/S RPTR number Indicates which repeater is the Failsoft Repeater
G.
The RGRP status (Y /N ) Indicates whether or not the Subfleet is Regroupable
H.
The OP#/INDIVIDUAL ID numbers These columns provide the IDs for the Individual Operators Position
B.
C.
D.
E.
F.
G.
A.
H.
TRUNKING ID INFORMATION
BID NAME A1 A2 A3 A4 STATE POLICE N DYNAMIC FLEET A FLEET B
SYS,SITE MAP 1FC9 1FC9 1FC9 1FC9 B M B M
F/S FLT S/F RPTR RGRP? 405 600 405 600 2 1 0 0 3 2 Y Y
{ 2/001 1/002 2/000 1/000
OP#/INDIVIDUAL ID
CEN022 011796JNM
Figure 3-1
Trunking ID information page
68P 81095E 50- A 11/30/2000
3-3
Chapter 3
Introduction
The information required from Figure 3-2 is:

A.
The Internal System ID
MISCELLANEOUS INFORMATION
CUT CUT CUT CUT CUT
JUMPERS JUMPERS JUMPERS JUMPERS JUMPERS
JU1 JU1 JU1 JU1 JU1
THROUGH THROUGH THROUGH THROUGH THROUGH
JU9 JU9 JU9 JU9 JU9
ON ON ON ON ON
CEB CEB CEB CEB CEB
INTERCONNECT INTERCONNECT INTERCONNECT INTERCONNECT INTERCONNECT
BOARD, BOARD, BOARD, BOARD, BOARD,
CARD-CAGE CARD-CAGE CARD-CAGE CARD-CAGE CARD-CAGE
1 2 3 4 5
INTERNAL SYSTEM ID
TRUNKING SYSTM
AMSS SITE
00 01
1FC9 BB31
CEN023 122795JNM
Figure 3-2
Miscellaneous information page
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Chapter 3
Descriptor String Assignments Introduction
The information required from letter A in Figure 3-3 is the Base Identification number (MID) and the associated TDM slot assigned to a particular CEB card.
PHONE LINE TERMINATIONS
CAGESLOT#
MODEL # (MN/ALT)
FUNCTION
P2
MID/TDM
LABEL
CAGESLOT#
MODEL # (MN/ALT)
FUNCTION
P2
MID/TDM
LABEL
CARDCAGE # 1
1- 1
B1422A
2W 4W LOG RCDR 2W 4W LOG RCDR N/A N/A
23,48 24,49 25,50 17,42 18,43 19,44
B07/00
CONVEN
1- 2
B1617A
2W 4W LOG RCDR 2W 4W LOG RCDR N/A N/A
20,45 21,46 22,47 14,39 15,40 16,41
B02/01
SYS 1FC9 RPTR 2 852012.5 kHz SYS 1FC9 RPTR 4 854012.5 kHz
1- 3
B1617A TRUNK SW BLN6845A BLN6650A
B03/02
SYS 1FC9 RPTR 3 853012.5 kHz
1- 4
B1617A
B04/03
1- 7 1- 9
1- 8 1- 10 CARDCAGE # 1
BLN6650A BLN6008A
2- 1
B1618A
2W 4W LOG RCDR 2W 4W LOG RCDR N/A
23,48 24,49 25,50 17,42 18,43 19,44
B06/06
CONVEN
2- 2
N/A
2- 3
B1422A TRUNK SW BLN6845A
B08/08
SYS 1FC9 RPTR 3 853012.5 kHz
2- 4
B1617A
2W 4W LOG RCDR 2W 4W LOG RCDR N/A
14,39 15,40 16,41 09,34 08,33 07,32
B01/09
SYS 1FC9 RPTR 1 851012.5 kHz SYS1FC9 RPTR 5 855012.5 kHz
2- 7
2- 8
B1617A
B05/0C
2- 9
B1423A
LINE1 LINE 2
06,31 05,30
B11/0E B12/0F
MONITOR 1 MONITOR 2
2- 10
CEN024 031296JNM
Figure 3-3
Phone line terminations page
If any of the above information is not available in the As-Built document shipped with your control console system, obtain it from your local Motorola Sales Representative or Service Representative.
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Table 3-1
Available bit patterns

Bit patterns
PPPF PPPF PPPF PPPS PPPF PPPF PPPF PPPF PPPF PPPF PPPF PPSS PPSS PSSS PSSS SSSS SSSS FFFF FFFS FSSS SSII FFFF FFFF FFFF FFFS FFSS FSSS SSSS SSSI SSII SSII SIII SIII IIII FFSS SSII SIII IIII FSSI SSSI SSII SIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
Code
A B C D E F G H I J K L M N O P Q
where: P refers to PREFIX bits F refers to FLEET bits S refers to SUB FLEET bits I refers to individual ID bits
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Descriptor String Assignments Descriptor string types
Descriptor string types

There are 5 types of descriptor strings. Each type and its format is shown below.: p Conventional AA CCbbB Where: m AA is the Ambassador Electronics Bank (AEB) ID number m CC is the Central Electronics Bank (CEB) ID number m bb is the base station identification number (BIM/BID code) m B designates conventional base station
NOTE You do not need to use the AEB number if your system is non-Embassy. You do not need the CEB number if your system has only one CEB.
Type II/SmartZone trunked talkgroup ttttsiiiirrA or ttttsiiiirrD Where: m tttt is the talk group m s is the trunked system ID (0 - 7) m iiii is the individual ID m rr is the Failsoft repeater number (Embassy systems) OR the TDM slot (non-Embassy) m A designates re-groupable trunked group m D designates not re-groupable trunked group
Type I trunked talkgroup sggggrrA or sggggrrD Where: m s is the trunked system ID (0 - 7) m gggg is the trunked group ID m rr is the Failsoft repeater number (Embassy systems) or the TDM slot (non-Embassy) m A designates re-groupable trunked group m D designates not re-groupable trunked group
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Selective call suuuuC or rsuuuuE Where: m r indicates whether the assigned channel talks to Enhanced or non-Enhanced Private Conversation II mobiles (ring enabled or not) m s is the trunked system identification number m uuuu is the console unit identification number m C designates Private Call II m E designates Aliased or Enhanced Private Call II operation
The following examples show how to calculate the descriptor string information using Figures 3-1, 3-2, and 3-3, and Table 3-1.
Example 1 Conventional
Format: AACCbbB The bb in the descriptor string is found on the PHONE LINE TERMINATIONS page of the As-Built document (Figure 3-3). Find the listing for CONVEN in the LABEL column. The base station number is decimal and is found in the MID portion of the MID/TDM column. Simply use the two numbers and disregard the initial letter B. The number value will be between 00 and 99. The B is the final character of the descriptor string. For an Embassy sytem, AA the AEB ID, and CC the CEB ID must be determined for each conventional descriptor string. The AEB ID and CEB ID determine the location of the conventional resource in the system. This information is currently not available within the As-Built document.
Example 2 Trunking Talkgroup (Type II/SmartZone)

Format: ttttsiiiirrY or ttttsiiiirrD The s in the descriptor string is the Internal System ID found on the MISCELLANEOUS INFORMATION page of the As-Built document. The ggggrr in the descriptor string is calculated from information on the TRUNKING ID INFORMATION page, the MISCELLANEOUS INFORMATION page, and the PHONE LINE TERMINATIONS page of the As-Built document, as well as from information in Table 3-1. The following steps describe the procedure for calculating Type II/SmartZone trunking talkgroup descriptor strings.
1.
Refer to Figure 3-1. Select the talk group for which you wish to generate a descriptor string. For this example, the STATE POLICE talk group will be used. Read the SYS, SITE column entry for STATE POLICE. In this example the SYS, S ITE is lFC9. Refer to the MISCELLANEOUS INFORMATION page of the As-Built document (Figure 3-2). Find the Internal System ID for SYS, SITE lFC9. The Internal System
2.
3.
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ID is 0. The 0 is the character to be entered in place of the s in Type II/SZ descriptor strings. The descriptor string now looks like this: tttt0iiiirrY or tttt0iiiirrN
4.
Find the talk group for STATE POLICE from the Field Code Management System (in this example, use talkgroup 124). Change this number to hex - 007C. Replace the talkgroup portion of the descriptor string with this number. The Type II/SZ descriptor string now looks like this: 007C0iiiirrY or 007C0iiiirrN
5.
Use the Field Code Management System to identify an unused individual ID in the system (in this example, use 1042). Change this number to hex - 0412. Replace the individual ID portion of the descriptor string with this number. The Type II/SZ descriptor string now looks like this: 007C00412rrY or 007C00412rrN
6.
Refer to Figure 3-1. Read the F/S RPTR column for the STATE POLICE talk group, which is 3 for this example. For Smartzone talkgroups there is no associated failsoft repeater; replace the rr in the descriptor string with FF and go on to step 8.
6.1 6.2
If this is an Embassy system, replace the rr in the descriptor string with the F/ S RPTR number and go on to step 8. If this is a non-Embassy system,refer to Figure 3-3 (the PHONE LINE TERMINATIONS page of the As Built document). Find the listing for SYS lFC9 RPTR 3 in the LABEL column. Read the TDM hex number in the TDM portion of the MID/TDM column corresponding to SYS lfc9 RPTR 3, which is 02 in this example.
7.
Replace the rr in the descriptor string with the hex TDM number. The descriptor strings now looks like this: 007C0041202Y or 007C0041202N
8.
Refer to Figure 3-1 and read the letter in the RGRP column for the STATE POLICE talk group, which is Y for this example. If the entry is a Y, change the final character of the descriptor string to A. If the entry is an N, change the final character of the descriptor string to D. For this example the entry is a Y. So, the final Type II/ SmartZone trunking talkgroup descriptor string looks like this: 007C0041202A
Example 3 Trunking Talkgroup (Type I)

Format: sggggrrY or sggggrrN The s in the descriptor string is the Internal System ID which is found on the MISCELLANEOUS INFORMATION page of the As-Built document. The ggggrr in the descriptor string is calculated from information contained in the TRUNKING ID INFORMATION page, MISCELLANEOUS INFORMATION page, and the PHONE LINE TERMINATIONS page of the As-Built document as well as from information in
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Table 3-1. The following steps describe the procedure for calculating Type I trunking talkgroup descriptor strings.
1.
Refer to Figure 3-1. Select the talkgroup for which you wish to generate a descriptor string. For this example, the STATE POLICE talk group will be used. Read the SYS, SITE column entry for STATE POLICE. In this example the SYS, S ITE is lFC9. Refer to Figure 3-2. Find the Internal System ID for SYS, SITE lFC9. The Internal System ID is 0. The 0 is the character to be entered in place of the s in Type I descriptor strings. The descriptor string now looks like this: 0ggggrrY or 0ggggrrN
2.
3.
4.
Refer to Figure 3-1 again. Read the entry in the MAP column for the STATE POLICE talk group (which is B for this example). Refer to Table 3-1. Copy the bit pattern that corresponds to the MAP letter. Table 3-1 shows the bit pattern for the letter B as: PPPF FFFS SSII IIII
5.
6.
Refer to Figure 3-1. Read the three-digit hex number in the FLT column for the STATE POLICE talk group (which is 405 for this example). Convert the most significant digit into a three bit binary number. Replace the P characters in the bit pattern found in Table 3-1 with this three-bit binary number (100 in this example). The bit pattern now looks like this: 100F FFFS SSII IIII
7.
8.
Convert the two least significant digits of the FLT number found in Step 6 into a binary number with as many bits as Fs in the bit pattern found in Step 5. This translates to 0101 (four Fs in the bit pattern; four bit binary 5). Substitute this binary pattern for the Fs in the bit pattern found in Step 5. The bit pattern now looks like this: 1000 101S SSII IIII
9.
10.
Refer to Figure 3-1. Read the decimal number in the S/F column of the STATE POLICE talk group (which is decimal 2 for this example). Convert the decimal number to a binary number with as many bits as Ss in the bit pattern found in Step 5. This translates to 010 (three Ss in the bit pattern; three bit binary 2). Substitute this binary pattern for the Ss in the bit pattern found in Step 5. The bit pattern now looks like this: 1000 1010 10II IIII
11.
12.
Refer to Figure 3-1. Read the three-bit hex number following decimal OP# in the OP#/INDIVIDUAL ID column for the STATE POLICE talk group (which is hex 001 for this example). Convert this three-bit hex number into a 12-bit binary number. The 12-bit binary conversion for 001 is: 0000 0000 0001.
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13.
Since there are six Is in the bit pattern, use only the six least significant bits (00 0001) of the 12-bit binary conversion. Replace the Is in the bit pattern found in Step 5 with as many of the least significant bits of the binary number as there are Is in the bit pattern. The bit pattern found in Step 5 now looks like this: 1000 1010 1000 0001
14.
Now convert each of the four final 4-bit binary numbers appearing in Step 13 to hex, starting from least significant 4-bit binary number to the most significant 4-bit binary number, as follows. Binary number pattern: from Step 13: Convert to hex: 1000 8 1010 A 1000 8 0001 1
15.
Replace the gggg in the descriptor string sggggrrY or sggggrrN with the 4-bit hex number found in Step 14. The Type I descriptor string now looks like this: 08A81rrY or 0 8A8lrrN
16.
Refer to Figure 3-1 and read the F/S RPTR column for the STATE POLICE talk group, which is 3 for this example. If this is an Embassy system, replace the rr in the descriptor string with the F/S RPTR number and go on to step 18.
17.
If this is a non-Embassy system, refer to the PHONE LINE TERMINATIONS page of the As Built document (Figure 3-3). Find the listing for SYS lFC9 RPTR 3 in the LABEL column. Read the TDM hex number in the TDM portion of the MID/TDM column corresponding to SYS lfc9 RPTR 3, which is 02 in this example. Replace the rr in the descriptor string with the hex TDM number. The descriptor strings now looks like this: 08A8102Yor 08A8102N
18.
Refer to Figure 3-1 and read the letter in the RGRP column in the STATE POLICE talk group, which is Y for this example. If there is a Y entry, change the final character of the descriptor string to A. If there is an N entry, change the final character of the descriptor string to D. For this example the entry is a Y. So the final Type I Trunking Talkgroup descriptor strings looks like this: 08A8102A
Example Trunking Talkgroup (Type I): MAP bit pattern differences

Suppose the descriptor string for the DYNAMIC talk group is to be calculated (See Figure 3-1). The FLT number is 600 and the MAP letter is M. This changes some aspects of the calculation in Example 3, which are clarified in the following calculation.
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NOTE The steps in the following calculation follow the same (step procedure numbers) as Example 3.
1.
Refer to Figure 3-1. Select the talkgroup for which you wish to generate a descriptor string. For this example, the STATE POLICE talk group will be used. Read the SYS, SITE column entry for STATE POLICE. In this example the SYS, S ITE is lFC9. Refer to Figure 3-2. Find the Internal System ID for SYS, SITE lFC9. The Internal System ID is 0. The 0 is the character to be entered in place of the s in Type I descriptor strings. The descriptor string now looks like this: 0ggggrrY or 0ggggrrN
2.
3.
4.
The bit pattern for MAP code M is: PPSS SSII IIII IIII
5.
The FLT number is 600. Converting the most significant hex digit into the three-bit binary pattern is 110. Since there are only two P characters in the bit pattern found in Step 5 of Example 1, only the two most significant digits of the binary number are used: 11 (the 0 is dropped). The bit pattern then is: 11SS SSII IIII IIII
6.
The last two digits of the FLT number are 0, but since there are no F characters in the bit pattern found in Step 5, these digits are ignored and the bit pattern remains: 11SS SSII IIII IIII
7.
The decimal subfleet number is 1, which when converted to a binary number and inserted for the S characters, provides the following bit pattern: 1100 01II IIII IIII
8.
The OP#/INDIVIDUAL ID number is 002 (0000 0000 0010 in binary). Using the required number of least significant bits of the binary code to replace the ten Is in the bit pattern, the bit pattern is now: 1100 0100 0000 0010
9.
Convert the bit pattern found in Step 8 to hex: Binary number pattern: from Step 8: Convert to hex: 1100 C 0100 0000 0010 40 2
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10.
Replace the gggg in the descriptor string sggggrrY or sggggrrN with the 4-bit hex number found in Step 9. The descriptor string now looks like this: 0C402rrY or 0C402rrN
11.
The F/S RPTR number is 2, with a corresponding TDM slot number 01. Substituting the 01 for the rr in the descriptor string yields: 0C40201Y or 0C40201N Refer to Figure 3-1 and read the letter in the RGRP column in the STATE POLICE talk group, which is Y for this example. If there is a Y entry, change the final character of the descriptor string to A. If there is an N entry, change the final character of the descriptor string to D. For this example the entry is a Y. So the final Type I Trunking Talkgroup descriptor strings looks like this: 0C40201A
Example 4 Selective Private Call

Format: suuuuC or rsuuuuE To determine descriptor strings for Private Call II operation, follow the procedure for the Type I trunking talkgroup descriptor strings. The TDM slot of the failsoft repeater and re-groupability status are not applicable for Private Call II operation. You may choose any valid talkgroup for use in generating the system and group ID fields of the entered string. There are two types of Selective Call. If the assignment is made on a console which does no have the Enter ID switch available, the Selective Call descriptor string suuuuC is used. For these types of Selective Calls, the ID of the mobile unit called is entered when the assigned DCCM is selected. The s in the string is calculated exactly the same as the s is calculated in Step 3 of Example 3. Replace the s in the descriptor string with the value found in the calculation. The unit ID, uuuu, may be either a Type I or Type II/SZ ID. If a Type I ID, calculate the unit ID in exactly the same way as the calculation for gggg found in Steps 4 through l5 of example 3. Replace uuuu in the descriptor string with the calculated value. If a Type II/SZ ID is desired, choose an unused individual ID using the Field Code Management System, change the ID to hex, and use this ID in the string. The final letter of the selective call descriptor string is C. The second type of Selective Call is Aliased or Enhanced Private Conversation II operation, where the Enter ID switch is used to enter the ID of the mobile unit called. The Selective Call descriptor string looks like rsuuuuE. Calculate the console ID, (uuuu in the descriptor string), as described above. Use a 1 for the r in the descriptor string if the channel is to be used to talk to mobiles with Enhanced Private Call capabilities (ring enabled). Use a 0 for the r if the channel is to be used to talk to non-enhanced ( non-ring enabled) mobiles.
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The final letter of the Selective Call descriptor string is E. Since only Type II/SZ mobiles are capable of using Enhanced Private Call, only a Type II/SZ unit ID will be accepted if the r number is 1.
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4 4 Options
About this chapter

Section
General List of options Recommended test equipment Option descriptions and test procedures Troubleshooting
Page
4-2 4-3 4-4 4-6 4-33

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Chapter 4 General
Options
General
There are a number of options available for the CENTRACOM Gold Series console, allowing a customers system to be tailored to their needs. This chapter describes some of these options. Along with the functional descriptions, a series of tests is also provided for each option in the event of a malfunction. Since most of these options are implemented in firmware, attempts at field repair of specific malfunctions should usually not be attempted. Problems can sometimes be the result of an improperly programmed EPROM or a failure to insert the appropriate firmware after swapping modules. Therefore, after each test, the possible source of a malfunction is suggested. Whenever an option fails its tests, it is recommended that all the cabling, particularly the COIM-to-console data link, be checked.
NOTE The test procedure steps for activating an option described in this chapter are specific to a Classic Buttons and LEDs operator position. If your system has Classic CRT or Elite operator positions, refer to the appropriate Operators Manual for information on using the optional features.
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Options
List of options
List of options
Table 4-1 provides a list of options described in this section.
Table 4-1
List of CEB Options

Description
Supervisory Takeover Relay Mute Second Receiver Line Operated Busy Light Switched Output and Separate Input Indicator Timed Unselected Audio Mute Main/Standby Relay Switched Output with One Indicator Switched Output with Two Indicators Switched Output with Separate External Input DC Control Repeater Control Dont Disable Tone Encoding Extended Initial Guard Tone Priority Channel Marker Carrier Operated Relay Input Headset Jack Footswitch Telephone/Headset Interface Audible Alarm PTT Output Relay Additional Headset Jack Self Repeat Coded/Clear for DVP External Input with Two Indicators External Input Indicator Two Separate External Input Indicators Dedicate Unselect Speaker Signaling Input PL Strip for Paging High Speed Mute Dedicate Select Speaker Latched Input with Individual Reset
Option
K48 K56 K59 K60 K70 K121 K123 K124 K138 K139 K143 K146 K170 K235 K380 K570 K572 K577 K578 K700 K704 K710 K711 K713 K714 K715 K735 K739 K744 K748 K757 K766
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Options
Recommended test equipment

General
The following test equipment is required to perform the recommended tests.
Table 4-2
Test Equipment Required for Option Testing

Example
Tektronix 7623A Hewlett Packard 3551A Lambda LQ-521 Fluke 8010A
Equipment Required
Oscilloscope, Digital Storage Transmission Test Set
Power Supply (current limited, adjustable to 100 mA) Digital Multimeter R1012 or R1032 DVP Test Set
In addition to test equipment, it is recommended that the As-Built documentation for the system you are testing be available. This documentation contains the I/O information for hardware/software options as well as information about system topology. Ensure that all peripheral hardware required to implement an option is available at the time of test.
Notes for testing

Before performing any of the following tests, note the following: p p p Options which do not require functional tests are not covered in the test procedures. Unless otherwise stated, all hardware and hardware options should have their jumpers (if any) configured for normal operation. All phone lines used for audio tests shall either be terminated in a 600 load (10%) or terminated by an actual base station or a telephone line routed to a base station. Unless otherwise stated, all phone line measurements with an oscilloscope are made in a differential manner. The scope should be set for ac measurements, with sensitivity and timebase settings needed to display a 1000 Hz tone at + 15 dBm and modified as required. All phone line measurements made with a transmission test set shall be made with the device configured to allow only one 600 load on the phone line (i.e., bridging mode is selected for an already terminated line). The phone line test set should be capable of a bridged operating mode which is fully isolated from earth ground.
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Options
p p
All measurement procedures should begin with the console in the initial power-up mode (the mode the console enters immediately upon power up or reset). Many of these tests require qualified personnel at more than one site simultaneously. In order to communicate effectively between sites, the use of portable communication devices is recommended.
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Options
Option descriptions and test procedures

K48 Supervisory takeover relay
Description
This option controls a relay that disconnects the transmit wire pair of remote control units from a base station. The audio of these remote units must be routed through the console in order for this option to be employed. This option adds the TAKEOVER feature to a console channel.
NOTE This option is not compatible with the K380 and K748 options.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, channel control module, and multiple phone line terminations for the channel using the takeover option. Determine if the channel under test is 2-wire or 4-wire, and if the BIM uses tone or DC control. Attach the probes from the receive section of a telephone line test set (in bridging mode) across the transmit lines of the BIM. Attach the probe from the transmit section of the test set across the receive lines of the BIM.
2.
3.
4.
NOTE The receive lines are the same as the transmit lines in a 2-wire configuration.
5. 6.
Configure the test set transmitter to send a 1000 Hz tone at a level of 0 dBm. Check the TAKEOVER switch in its normal mode (yellow LED on, green LED off) and verify that both the main and remote consoles are capable of receiving the 1000 Hz tone from the telephone line test set. Initiate a transmit function from the remote console and verify that the audio from the remote is detected on the receiver of the telephone line test set.
7.
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Options
8.
Refer to the K59 option for details on verifying correct operation of any LOBLs employed in the system. Press the TAKEOVER switch. Verify that the yellow LED on the switch extinguishes and the green LED lights. Initiate a transmit function from the remote console. Verify that transmit audio from the remote cannot be detected at the test set. Verify that a normal audio transmission from the main console is unaffected by the takeover function. Verify that the receive audio (1000 Hz tone) is received by the main console and by the remote console (except if the remote is a 2-wire tone type). Press the TAKEOVER switch again and verify that both consoles return to their previous state. Refer to Table 4-5 on page 4-33 in the event of test failure.
9.
10. 11.
12.
13.
14.
K56 Mute second receiver

Description
This option allows the operator to mute the second receiver from a two receiver base station. This option is normally employed with a 2-wire base station. The option adds the MUTE R2 feature to a console channel.
Tests Required
1.
Refer to the As-Built documentation to determine:

1.3 1.4
the phone line terminations for BIMs. which BIMs are capable of performing the MUTE R2 function.
2.
Attach the output of one of these BIMs to a standard Motorola MSF5000TM base station, equipped with a C668AA diagnostic metering panel. Press the MUTE R2 button at the operator position and verify that the corresponding LED lights. Verify that, as the button is pressed, the diagnostic metering panel detects the command to mute the second station receiver. The command is detected when the R2 MUTE LED on the panel lights. Press the button a second time and verify that its corresponding LED extinguishes, along with the R2 MUTE LED on the diagnostic metering panel. Refer to Table 4-5 on page 4-33 in the event of test failure.
3.
4.
5.
6.
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Options
K59 Line operated busy light (LOBL)

Description
This option allows the console operator to monitor any control (key-up) activity performed by external controllers. Any external key-ups cause the console to exhibit a busy status on the busy channel and inhibit the keying of that channel by the console operator unless the console is a supervisor position. This option is available for both tone (K59AL) and DC (K59AK) control formats.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, channel control module, and phone line terminations for the channel employing a LOBL function. In addition, identify any other termination points for the audio pairs routed to the remote console device. Verify that the LOBL board (tone or DC) is securely fastened to the BIM and has its 20-pin ribbon connector firmly in place. Connect the receive probes of a telephone line test set (bridging mode) to the transmit phone lines of the BIM. Connect the transmit probes of the test set to the receive phone lines of the BIM.
2.
3.
4.
NOTE The receive and transmit line are the same for a 2-wire configuration.
Tone LOBL
1.
Verify that the BIM operates correctly by performing a voice transmission and receiving the transmission with the telephone line test set. Configure the test set to transmit 1000 Hz at a level of 0 dBm and verify that the audio causes the red CALL LED to light on the console. Disable the test set audio. Verify that the yellow BUSY LED corresponding to the channel under test is off. Configure the transmitter of the test set to transmit 2175 Hz 1 Hz at a level of -25 dBm. Enable the 2175 Hz source and verify that the BUSY LED lights. Reduce the transmit level of the test set to -55 dBm, and verify that the BUSY LED is still lit. Disable the test set.
2.
3. 4. 5.
6. 7.
8.
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9.
Press the Instant Transmit button on the CCM corresponding to the channel under test. Verify that before, during, and after the switch is pressed, no spurious illumination of the yellow BUSY LED occurs. Refer to Table 4-5 on page 4-33 in the event of test failure.
10.
DC LOBL TEST
1. 2.
Repeat Tone LOBL Test steps 1 through 3. Attach a 3.9k resistor ( 1%) across the telephone lines of the BIM which is using the LOBL function. Attach a power supply in parallel with the resistor. Make sure that the resistor and power supply are the only terminations on the phone line. Set the voltage of the power supply to 7.4 V( 0. 1V). Adjust the LOBL sensitivity potentiometer (R103) to the point which just allows the LOBL to cause the BUSY LED to light at the appropriate channel control module. Vary the voltage of the supply at a slow rate (approximately 0.1 V per second) and verify that the LOBL yields a solid detect (via BUSY LED indication) at voltages of 7.4 V and higher. Remove the voltage source and verify that the BUSY LED extinguishes. Remove the resistor and voltage source from the phone lines. Terminate the lines in a standard load and initiate a standard voice transmission. Verify that before, during, and after the transmission, there are no spurious indications on the console BUSY LED. Refer to Table 4-5 on page 4-33 in the event of test failure.
3.
4. 5.
6.
7. 8. 9.
10.
K60 Switched output and separate input indicator (flashing)

Description
This option provides a switch which controls a green LED and a relay. Relay operation may be momentary or latching. The green LED is lit when the relay is enabled and extinguished when the relay is disabled. This option provides a separate external closure indicator (flashing yellow = external switch on). The external input may be included in an alarm group. This option is custom labeled on the console.
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Test Required Green LED check

1.
Refer to the As-Built documentation to determine the output relay contact terminations for the option under test. Identify the input option as either momentary or latching. Place an ohmmeter across the output relay terminations. Verify an open circuit reading on the ohmmeter. Verify that the green LED corresponding to the control switch is extinguished. Press and hold the button corresponding to the option under test. Verify that the green LED on the button illuminates and the the ohmmeter indicates a closed circuit. Release the button and verify that for a latching option no further changes take place. Verify that releasing the button causes a momentary function to return to its previous state. Verify that pressing the button again (for a latching option) cause the LED and relay contacts to change state. Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3. 4. 5.
6.
7.
8.
9.
Yellow LED check

1.
Refer to the As-Built documentation to determine the input contact terminations from the input circuit under test. Verify that the yellow LED (lower LED) on the channel control module is off, indicating an open input condition. Use a clip lead or similar device to short the two input contact terminations together. Verify that this causes the yellow LED to flash. Remove the clip lead and verify that the yellow LED extinguishes. Refer to Table 4-5 on page 4-33 in the event of test failure.
2.
3.
4. 5.
K70 Timed unselected audio mute

Description
When activated, this option provides about 24 dB of attenuation (with respect to maximum volume) to all audio routed into the UNSELECT speaker(s). This function times out automatically in 30 seconds and can be manually overridden by pressing the switch again before the time-out period. The automatic timer and mute level may be
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field-modified by changing the PROM. This option adds the ALL MUTE feature to a console.
Tests Required
1.
Inject a 1000 Hz tone at 0 dBm into a system receive path (BIM or DR). Refer to As-Built documentation for system telephone line I/O information. All receive paths in the system should be routed such that only the path with the 1000 Hz tone is routed to the UNSELECT speaker. Set the individual volume potentiometer governing the path containing the 1000 Hz tone to full volume (fully clockwise). Attach a phone line test set across the speaker leads of the UNSELECT audio speaker.
2.
3.
CAUTION Test set must be either fully bridging or isolated from earth ground or damage will result to the speaker amplifier.
4. 5.
Configure the test set to receive in a bridged (high impedance) mode. Adjust the UNSELECT speaker volume pot so that the output level of the speaker, as measured on the test set, is 0 dBm ( 0.2 dBm). Press the ALL MUTE button (or choose the All Mute toolbar icon) and verify that the output level of the speaker, as measured on the test set, drops to -24 dBM ( 2.0 dBm). Allow the mute condition to continue and measure the time-out period. Verify that this period lasts for thirty seconds ( 2 seconds). Verify that the audio level present in the UNSELECT speaker returns to 0 dBm following the time-out. Repeat 1 through 9 to test the removal of the option. This time, however, press the ALL MUTE switch again after approximately five seconds and verify that full volume (0 dBm) is restored to the speaker. Adjust the individual volume potentiometer so that the UNSELECT speaker output is less than -25 dBm as measured on the test set output. Press the ALL MUTE button and verify that no change occurs in the output level of the UNSELECT speaker.
6.
7. 8. 9.
10.
11.
12.
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NOTE If custom time-out and mute level parameters are used in the system under test, the above test procedures should be modified to correspond to these custom parameters.
13.
Refer to Table 4-5 on page 4-33 in the event of test failure.
K121 Main/standby relay

Description
This option provides the relay necessary to implement the main/standby feature. These options provide a 2 or 4 pole double-throw enclosed relay to switch the audio from a BIM to one of two base station phone line pairs.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, channel control module, and phone line terminations corresponding to the main and standby channels. Attach the probes of the receive section of a telephone line test set (in bridging mode) to the transmit phone lines of the main channel. Attach the probes from the transmit section of the test set to the receive phone lines of the channel (these are the same phone lines for a 2-wire configuration). Configure another test set in similar fashion to the phone lines of the standby phone channel. Configure each test set to transmit 1000 Hz at a level of 0 dBm. At the console, verify that the green LED corresponding to the MAIN/STANDBY switch is lit and the yellow LED is extinguished, indicating that the MAIN channel is selected. Enable the transmitter from each of the test sets alternately and verify that only the transmitter on the MAIN channel produces a flashing CALL LED and receive audio. Initiate a voice transmission from the console and verify that only the test set attached to the MAIN channel receives the transmit audio. Press the MAIN/STANDBY button and verify that the green LED extinguishes and the yellow LED lights. Repeat Steps 2 through 9 and verify that the STANDBY channel is now functional and the MAIN channel is bypassed.
2.
3.
4.
5. 6.
7.
8.
9.
10.
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11.
K123 Switched output with one indicator

Description
This option provides a switch which controls a green LED and a relay. Relay operation may be momentary or latching. The green LED is lit when the relay is enabled and extinguished when the relay is disabled. This option is custom labeled at the console. This option does NOT provide the relay output.
Tests Required
1.
Refer to the As-Built documentation to determine the output relay contact terminations for the option under test. In addition, identify the input option as either momentary or latching. Place an ohmmeter across the output relay terminations. Verify that the impedance measured with the ohmmeter indicates an open circuit. Verify that the green LED corresponding to the control switch is extinguished. Press and hold the button corresponding to the option under test and verify that the green LED corresponding to the button illuminates and a closed circuit is indicated on the ohmmeter. Release the button and verify that for a latching auxio no further changes take place. Verify releasing the button causes a momentary function to return to its previous state. For a latching auxio, press the button again and verify that the LED and relay contacts change state. Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3. 4. 5.
6. 7.
8.
9.
K124 Switched output with two indicators

Description
This option is similar to the K123 option, except that two LEDs are provided. When the relay is enabled, the green LED is on and the yellow LED is off. When the relay is disabled, the green LED is off and the yellow LED is on. This option is custom labeled at the console.
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Tests Required
Repeat the test for the K123 option, with the exception that when the green LED is extinguished, the yellow LED is lit; and when the green LED is lit, the yellow LED is extinguished.
K138 Switched output with separate external input

Description
This option provides a switch and one indicator (green = switch on) plus a separate indicator for an external closure which is received at the CEB (yellow = external switch on). This option is similar to a K123 option, with an added external input to control the yellow LED. The external input may be included in an alarm group. This option is custom labeled at the console. This option does NOT add the input buffer required to condition the input signal.
Tests Required
This option is tested exactly as the K60 option with the exception that the yellow LED does not flash.
K139 DC control
Description
This option modifies the personality PROMs in the COIMs to allow them to interpret the appropriate BIM as a DC control module. Additionally, a hardware module is added to the BIM which produces the DC keying currents. Use of this option automatically disables the tone remote signaling operation of the BIM unless a K146 option is also requested.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, channel control module, and the phone line termination for the channel employing the DC control option. Identify the plus and minus sides of the transmit line.
2.
NOTE The plus (+) side of the 2-wire line has pin designations ranging from 26-50 on connector P3 of the CEB interconnect board.
3.
Terminate the 2-wire phone lines from the BIM with a 10k resistance ( 1%).
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4.
Place a current meter in series with the termination and configure the meter to measure current in the range of 15 mA. Press the TRANSMIT button and verify that the current measured is + 5.5 mA. Refer to Table 4-5 on page 4-33 in the event of test failure.
5. 6.
K143 Repeater control

Description
This option allows the operator to control the enable/disable status of a repeater-style base station with either tone or DC control. This option adds the REPEATER DISABLE feature to a console channel.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, channel control module and phone line termination for the channel employing repeater control. Connect a telephone test set to the 2-wire phone line from the BIM. Press the REPEATER DISABLE button on one of the operator positions and verify that the LED corresponding to this button illuminator. Verify that the repeater disable function tone is sent. Press the button a second time and verify that the LED corresponding to the REPEATER DISABLE button extinguishes. Verify that the repeater enable function tone is sent. Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3.
4. 5.
6. 7.
K146 Do not disable tone encoding

Description
This option allows tone control to remain effective when a BIM is configured for DC or E&M (relay) control.
Tests Required (for channels using DC and tone control)

1.
Refer to the As-Built documentation to determine the BIM, the phone line terminations, and the channel control module corresponding to the channel employing this option. Terminate the 2-wire phone line from the BIM with a 10k ohm resistor.
2.
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3.
Connect an oscilloscope to the 2-wire line. Set the oscilloscope for 5 V per division, 20 msec per division. Connect a current meter in series with the termination. Press the TRANSMIT button and verify that the DC control currents and function tones are sent simultaneously by observing a current reading of + 5.5 mA on the current meter and a sudden pulse on the oscilloscope. Refer to Table 4-5 on page 4-33 in the event of test failure.
4. 5.
6.
K170 Extended initial guard tone

Description
This option extends the initial guard tone duration to be compatible with RA-link tone controlled stations.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, the telephone line termination, and the channel control module which correspond to the channel employing extended tone control. Set the oscilloscope to storage mode and set sweep time to 0.5 sec per division. Place the oscilloscope probes across the phone lines of the BIM. Perform an instant transmit on the appropriate channel control module. Measure the duration of the high guard tone burst. Verify that this period is 600 msec ( 10 msec). Allow the channel to de-key to complete the test. Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3. 4.
5. 6. 7.
K235 Priority channel marker

Description
This option when activated, transmits a 500 msec burst of 700 Hz every 10 seconds on the currently selected channel. The tone is not transmitted if the selected channel is busy. This periodic tone signal is used to warn low priority or unauthorized radio users to avoid using this priority channel. This option adds the CHANNEL MARKER feature to a console channel.
Tests Required
1.
Select one channel at a console.
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2.
Place the probes of an oscilloscope across the phone lines of the BIM which corresponds to the selected channel at the test console (refer to the As-Built documentation). Enable the channel marker function by pressing the button once. Verify that the tone burst described in the above description paragraph occurs on the idle channel output. Verify that an additional depression of the switch cancels the channel marker operation. Refer to Table 4-5 on page 4-33 in the event of test failure.
3. 4.
5.
6.
K380 Carrier operated relay input

Description
This option allows the receive portion of a BIM to work in an E&M signaling format. Instead of VOX operation of the CALL LED and patch keying functions, the BIM will accept a switch closure to perform these operations. One of the six auxiliary I/Os on the BIM is used for this option.
NOTE The K748 and K48 options are incompatible with this option.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, auxiliary I/O switch terminations, and channel control module corresponding to the channel employing the carrier operated relay input option. Verify that in the idle state, the channel control module corresponding to the channel under test has no active CALL LED. Use a a clip lead or similar device to short circuit the two auxiliary switch inputs together to simulate a relay closure. Verify that this operation forces the CALL LED on the appropriate channel to light. Remove the clip lead. Initiate a patch between the channel under test and any other channel capable of patch in the system under test. Repeat Step 3 and verify that this operation lights the CALL LED on the appropriate channel and also causes the second channel involved in the patch to automatically initiate a transmit function.
2.
3.
4. 5. 6.
7.
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8. 9.
Remove the clip lead and verify that the console returns to its previous state. Refer to Table 4-5 on page 4-33 in the event of test failure.
K570 Headset jack

Description
This option provides a double plug headset jack (mounted under the writing surface) with dual volume controls for radio and phone audio. Inserting a headset into the jack automatically disconnects the microphone and disables the console SELECT speaker. Select audio is then routed to the headset. The headset jack accommodates both a 4-wire and a 6-wire headset.
NOTE If a 4-wire headset is plugged into the jack without cutting jumper JU1 on the headset jack board, the console PTT will key the selected channel and the corresponding red TRANSMIT LED illuminates.
Tests Required
1. 2.
Verify that audio can be received and transmitted through the headset. If the headset does not operate properly, check the electrical connections from the options interconnect panel to the headset jack board. Refer also to the schematic diagram for the headset jack board in the appropriate console maintenance manual. If the problem persists, replace the headset jack board.
K572 Footswitch
Description
The footswitch provides transmit and monitor functions, allowing the operator to control these commonly used functions without use of the hands.
Tests Required
1. 2. 3.
Select a single channel at any operator position with a footswitch. Press the large footswitch pedal, which corresponds to a transmit bar. Verify that the single channel initiates a transmit function as if the transmit bar were pressed. Repeat the test with more than one channel selected.
4.
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5.
If the test fails:

5.1 5.2 5.3
check for a lit red LED on the associated COIM. If lit, it is possible that the personality PROM (U44) is incorrectly programmed. Verify that the personality PROM on the COIM contains the proper code. Check connections between the radio control board in the console and the COIM.
K577 Telephone/headset interface

Description
This option allows the console operator to answer a commercial telephone mounted in the console.
NOTE This option requires use of the headset jack option (K570).
Tests Required
1. 2.
Verify that audio is being transmitted to and from the headset. If audio is not present, check connections from the options interconnect board to the telephone/headset interface board. Refer to the telephone/headset interface schematic diagram this manual to check for possible component failure. Replace board if problem persists.
3.
4.
NOTE This option must be connected to an external FCC-registered telephone interface device which is not supplied with the console. This interface device may be the cause of the problem. In that case, the device should be replaced or repaired. Consult the appropriate service manual for details.
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K578 Audible alarm

Description
This option consists of an audible alarm located at one operator position (option may be installed at several positions). The alarm is enabled whenever there is a change of state on any of a group of selected aux I/O inputs. A reset switch is provided to disable the alarm until the next change of state occurs. Alarm inputs are described under different option listings. Only one K578 option may be added to a console.
Tests Required
1.
Refer to the As-Built documentation to determine the auxiliary I/O terminations for each of the alarm inputs controlling the alarm function under test. Verify that all aux I/O inputs to the alarm are in their open state and that the RESET button indicates a reset state (LEDs off).
2.
NOTE The inputs may function differently from one another. Refer to the As-Built documentation to determine the type of input and switch combinations included in the alarm input set.
3.
Use a clip lead or similar device to short the two input contact terminations of one of the alarm inputs. Verify that the individual alarm indicator responds per its functional description. Verify that the audible alarm sounds and the lower LED corresponding to the RESET button lights. Press the RESET button and verify that the audible alarm stops and that the lower LED corresponding to the RESET button is extinguished. Verify that there is no change of state in the individual LED status of the alarm input at the console. Remove the clip lead from the input contact terminations and verify that the alarm process initiates. Repeat Steps 2 through 7, this time attaching and removing the clip lead several times before pressing the RESET button. Refer to Table 4-5 on page 4-33 in the event of test failure.
4. 5.
6.
7.
8.
9.
10.
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K700 PTT output relay

Description
This option uses one of the auxiliary I/Os from a BIM to close a relay to signify a transmit PTT. This type of transmit control is typically used in an E&M signalling format. Additionally, this option may be used as a push-to-talk counter.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, auxiliary relay output terminations, and channel control module corresponding to the channel employing the PTT relay option. Using an ohmmeter, measure the impedance across the relay contact terminations and verify that the impedance indicates an open circuit. Initiate an instant transmit on the channel under test and verify that the impedance measured on the ohmmeter indicates a short circuit. Verify that the impedance returns to an open circuit measurement when the transmission is terminated. Refer to Table 4-5 on page 4-33 in the event of test failure.
2.
3.
4.
5.
K704 Additional headset jack

Description
This option allows the addition of a second headset jack to an operator position.
NOTE In order to have two operational headsets at a console at the same time, the telephone/headset jack interface board option (K577) must be installed.
Tests Required
Refer to headset jack option K570. If the test fails, in addition to checking the headset jack board as outlined for the K570 option, check the telephone/headset interface board. (Refer to option K577.)
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K710 Self repeat

Description
This option allows the received audio from a duplex base station (or from a Spectra-Tac comparator) to be re-transmitted under operator control through the console and out to the BIM which originally received the audio. This option adds the SELF REPEAT feature to a console channel.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM phone line terminations and the channel control module for the channel to be tested. Attach a telephone line test set to the receive telephone lines (4-wire) of the BIM. Set the test set to transmit a signal of 1000 Hz at a level of 0 dBm. Verify that this transmission forces the red CALL LED to light at the console. Place the probes from the receive section of the test set across the transmit phone lines (2-wire) of the BIM and verify that no audio is being transmitted from the BIM. Press the SELF REPEAT button and verify that the corresponding yellow LED (already lit) extinguishes and the corresponding green LED lights. Verify that the received tone is now being retransmitted from the BIM by measuring the 1000 Hz tone on the transmit phone lines of the BIM. Press the SELF REPEAT button a second time and verify that the green LED extinguishes and that the yellow LED lights. Verify that the operation of the BIM is restored to normal operation. Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3. 4. 5.
6.
7.
8.
9. 10.
K711 Coded/clear for DVP

Description
This single button option provides the means for the operator to specify whether the transmitted audio is to be sent in a coded or clear (uncoded) format from the DVP or DES encrypted base station. This option adds the CODED/CLEAR feature to a console channel.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM, phone line terminations, and the channel control module corresponding to the DVP channel to be tested.
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2. 3.
Attach a base station to the phone lines of the DVP channel. Select the appropriate channel at the operator position and press its CODED/ CLEAR button. Verify that the yellow LED (already lit) corresponding to the CODED/CLEAR button extinguishes and that the green LED lights. Verify that the DVPCODED function tone is sent. (Refer to Table 4-4 on page 4-30). Initiate a standard voice transmission from the console. Attach the probes from a telephone line test set in the receive (bridging) mode across the station transmit screw terminals of the General Purpose Interface Unit (GPIU) interconnect board located at the base station. The station transmit terminals are labeled as terminations 15 and 16 on P911 of the GPIU. Verify that the encrypted audio is unintelligible. Disconnect the telephone line test set and attach an R1012 or R1032 DVP test set across the same screw terminals.
4.
5.
6. 7.
8. 9.
NOTE An R1012 test set is used for systems employing VULCAN encryption and the R1032 test set is used for systems employing DES encryption. The appropriate test set must have the encryption key actively loaded.
10.
Verify that upon standard audio transmission, the audio monitored by the DVP test set is intelligible and free from obvious break-up or chatter. At the console, select the channel and verify that audio transmitted to the console from the DVP test set is intelligible (unencrypted). Press the CODED/CLEAR button and verify that the green LED extinguishes and that the yellow LED lights. Verify also that the DVPCLEAR tone is sent. Verify that all transmissions initiated in this mode are accompanied by a received alert beep tone from the GPIU at the base station (heard in the consoles SELECT speaker output). Refer to Table 4-5 on page 4-33 in the event of test failure.
11.
12.
13. 14.
15.
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K713 External input with two indicators

Description
This option provides a green LED indicator which lights by a closure input from some external event. A yellow LED remains extinguished for the duration of the closure. When the input registers an open condition, the LEDs change state (yellow lights, green extinguishes).
NOTE This option does NOT provide a switch at the operator position. This option does NOT provide the input buffer necessary to condition the input signal.
Tests Required
1.
Refer to the As-Built documentation to determine the input contact terminations for the input circuit under test. Verify that the green LED (upper LED) on the appropriate portion of the channel control module is off and that the yellow LED (lower LED) is on, indicating an open input condition. Use a clip lead or similar device to short circuit the two input contact terminations together. Verify that this operation causes the yellow LED to extinguish and the green LED to light. Verify that removing the clip lead causes the LEDs to toggle back to their original state. Refer to Table 4-5 on page 4-33 in the event of test failure.
2.
3.
4.
5.
6.
K714 External input indicator

Description
This option is similar to the K713 option except that only the green LED is used. There is no indication of an open contact condition.
Tests Required
1.
Refer to the As-Built documentation to determine the input contact terminations from the input circuit under test.
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2.
Verify that the green LED (upper LED) on the appropriate portion of the channel control module is off indicating an open input condition. Use a clip lead or similar device to short circuit the two input contact terminations together. Verify that this operation causes the green LED to light. Verify that removing the clip lead causes the green LED to extinguish. Refer to Table 4-5 on page 4-33 in the event of test failure.
3.
4. 5. 6.
K715 Two separate external input indicators

Description
This option provides a pair of indicators which are independently controlled by a closures from two separate external events. A green LED is lit when a closure is applied to one input and a yellow LED is lit when the closure is applied to the second input. This option is similar to using two K714 options, except that both LEDs on the button are used.
NOTE This option does NOT include either of the two input buffers needed to condition the input signals.
Tests Required
1.
Refer to the As-Built documentation to determine the input contact terminations for the two inputs involved with the option under test. Verify that both the green and yellow LEDs are off, indicating that each of their inputs is registering an open input condition. Use a clip lead or similar device to short circuit the input contact terminations of the first input. Verify that this operation causes the green LED to light. Remove the clip lead and verify that the green LED extinguishes. Use the clip lead to short circuit the input terminations of the second input. Verify that this operation causes the yellow LED to light. Remove the clip lead and verify that the yellow LED extinguishes. Use two clip leads and place them on the contacts at different times in order to verify that the two inputs circuits are operating independently of one another.
2.
3.
4. 5. 6. 7. 8. 9.
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10.
K735 Dedicated unselect speaker

Description
This option allows the unselect audio to be divided among several speakers, helping the operator clearly hear unselect audio messages in a larger system. The UNSELECT speaker at the operator position is defined as a monitor speaker capable of monitoring unselect audio output for up to four audio sources. This firmware option requires the use of an additional monitor speaker hardware option.
Tests Required
1.
Refer to the As-Built documentation to determine which audio paths (BIDs) are to be routed to the dedicated UNSELECT speaker, and to determine the points on the punchblock where each of these BIDs are routed. For each BID, audio should be routed into the system and verified according to the following test procedure.
NOTE The audio sources listed should be the only audio sourcing the system during the tests.
2. 3. 4. 5. 6.
Attach a telephone test set across the telephone line receive path under test. Configure the test set to generate a signal of 1000 Hz at 0 dBm. Press the SELECT button on the CCM module corresponding to the received audio. Verify that the received audio is routed through the SELECT speaker only. Press any other SELECT button on the console in order to unselect the received audio. Verify that the unselect audio is routed into the dedicated UNSELECT speaker. Repeat Steps 2 through 7 and verify that all BIDs assigned to the dedicated UNSELECT speaker are routed through the dedicated UNSELECT speaker when they are not selected. Verify that no other receive audio path (when unselected) is routed to the dedicated UNSELECT speaker. Repeat Steps 2 through 9 for any other speakers which may be used as dedicated UNSELECT speakers.
7. 8.
9.
10.
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K739 Signaling input

Description
This option allows an external (auxiliary) encoder device to be attached to the console. This encoder operates on selected channels. The option provides audio and PTT inputs for the external encoder. This option provides PL strip requirements for base stations requiring this type of feature for signaling.
Tests Required
1.
Refer to the As-Built documentation to determine the BIM phone terminations and the Aux I/O point at the radio control panel which accepts the PTT input for the external encoder. Place the probes of a telephone line test set across the BIM terminations. On the console equipped with the external signaling input, select the channel corresponding to the BIM monitored by the test set. Attach one end of a clip lead or similar device to the PTT Aux I/O input on the operator position. Use a second telephone line test set to inject audio into the signaling input by attaching the transmit probes across the balanced signaling input located on the options interconnect panel of the appropriate operator position. Set transmit source impedance to 600 , and transmit frequency to 1000 Hz. Attach the receive probes of the same test set (in the bridging received mode) across the signaling input in parallel with the transmit probes. Vary the transmit level until the receive display of the test set registers a level of 1000 Hz at -15 dBm ( 1 dBm). Enable the auxiliary signaling transmission by grounding the unattached end of the auxiliary PTT clip lead. Verify that this operation causes no change in activity on the console VU meter. Verify that a 1000 Hz tone is present and verify that no audio generated at the operator position (microphone or telephone headset) appears on the output lines of the appropriate BIM. Verify the presence or absence of PL-related function tones on the output of the BIM. PL strip capability exists within the console and is optionally activated. (Refer to As-Built documentation for information on requirements of PL tone activity.) Refer to Table 4-5 on page 4-33 in the event of test failure.
2. 3.
4.
5.
6. 7.
8.
9.
10. 11.
12.
13.
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Options
K744 PL Strip for paging

Description
This option modifies the personality PROMs in the COIMs in order to allow a BIM to send the PL/DPL strip command when the signaling option or external signaling input is used.
NOTE This option applies to T1R1 base stations only.
Tests Required
Before performing the following tests, refer to the As-Built documentation to determine the BIM, the telephone line termination, and the channel control module corresponding to any transmit channel.
DC Stations
1. 2. 3. 4.
Terminate the 2-wire phone line from the BIM with a 10k ohm resistor. Attach a telephone test set to the 2-wire line. Connect a current meter in series with the termination. Verify that when a paging PTT is activated, the proper DC current is generated. (See Table 4-3 for DC current levels.)
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Options
Table 4-3
DC Control Applications
Function
Nominal Current
T1 Standard
Minimum Current 4.6 mA 10.5 mA -6.4 mA -2.9 mA Maximum Current 6.4 mA 14.5 mA -4.6 mA -2.1 mA
F1 Transmit Repeater On Repeater Off Squelch Disable
5.5 mA 12.5 mA -5.5 mA -2.5 mA
T1 Paging
F1 Transmit F1 Page Squelch Disable 12.5 mA -12.5 mA -2.5 mA 10.5 mA -14.5 mA -2.9 mA 14.5 mA -10.5 mA -2.1 mA
T2 Standard
F1 Transmit F2 Transmit Mute R2 Squelch Disable 5.5 mA 12.5 mA -5.5 mA -2.5 mA 4.6 mA 10.5 mA -6.4 mA -2.9 mA 6.4 mA 14.5 mA -4.6 mA -2.1 mA
T4 Standard
F1 Transmit F2 Transmit F3 Transmit F4 Transmit Squelch Disable 5.5 mA 12.5 mA -5.5 mA -12.5 mA -2.5 mA 4.6 mA 10.5 mA -6.4 mA -14.5 mA -2.9 mA 6.4 mA 14.5 mA -4.6 mA -10.5 mA -2.1 mA
Tone operated stations

1.
Attach a telephone line test set to the phone line from the BIM.
Verify that the proper function tone is sent when a paging PTT is activated. (See Table 4-4 on the next page for the proper tones.)
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Options
Table 4-4
Function Tone Applications

Function Tone Usage
Receive PL/DPL disable. Transmit on Fl AND set multi-frequency receiver to RI OR Transmit on F1 with PL/DPL (paging only). Transmit on F2 AND set multi-frequency receiver to R2 OR Transmit on Fl without PL (paging only). Mute receiver R2 OR select PL code 5. Unmute receiver R2 OR select PL code 6. Repeater disable OR PL on OR maximum squelch OR select PL code 7. Repeater enable OR PL off OR minimum squelch OR select PL code 8. Transmit on F3 AND set multi-frequency receiver to R3 OR Wildcard I on OR select PL code 1. Transmit of F4 AND set multi-frequency receiver to R4 OR Wildcard I off OR select PL code 2. Wildcard II on OR D VP clear OR transmit on F5 OR select PL code 3. Wildcard II off OR DVP coded OR transmit of F6 OR select PL code 4. Special application OR transmit of F7. Special application OR initiate loop test. Special application OR transmit on F8. Special application.
Frequency (Hz)
2050 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 950 850 750 650
K748 High speed mute

Description
This option assigns one of the auxiliary I/Os to act as a high speed receive audio mute. An external switch or relay closure is required to drive the aux I/O. This external stimulus is typically an output from a data system controller.
NOTE This option is not compatible with another K748 or K48 option.
Tests Required
1.
Refer to the As-Built documentation for the system under test in order to determine the BIM, phone line terminations, channel control module, and auxiliary I/O input corresponding to the channel employing the high speed mute option. Place a telephone line test set across the appropriate phone line and configure the test set to transmit 1000 Hz at a level of 0 dBm.
2.
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Options
3.
Select the appropriate channel on the console and verify that the audio routes through the SELECT speaker Using a clip lead or similar device, ground the appropriate auxiliary I/O termination on the radio control panel and verify that the audio immediately mutes. Refer to Table 4-5 on page 4-33 in the event of test failure.
4.
5.
K757 Dedicate select speaker

Description
If it is desired that every base station (or group of base stations) have its own speaker, it is possible to dedicate the SELECT speaker to a channel or group of channels. When this option is used, the SELECT capability on all control modules only control transmit audio. When this option is employed, the headset option may not be used.
Tests required
1.
Refer to the As-Built documentation in order to determine which BIM routes audio to which speaker when the audio is selected or unselected. Attach a telephone line test set to the telephone line receive inputs under test and configure the telephone test set to generate a signal of 1000 Hz at 0 dBm (plus or minus 0.5 dBm). Verify, according to the As-Built documentation, that the audio received from the BIM routes to the correct speaker.
2.
3.
NOTE Audio is routed to the same speaker regardless of whether the audio is selected or unselected.
4. 5.
Repeat Steps 2 and 3 for all BIMs in the system. Refer to Table 4-5 on page 4-33 in the event of test failure.
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Options
K766 Latched input with individual reset

Description
This option provides the same functions as the K578 audible alarm function, but has no audible alarm. In other words, the option provides a green LED which latches in the on state when its input changes state. The option also provides a means to reset the latch condition. No input buffer is provided to condition the input signal.
Tests Required
This test is identical to the K578 option, except no audible alarm is sounded.
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Options
Troubleshooting
Troubleshooting
Table 4-5 contains fault isolation procedures pertaining to each option.
Table 4-5
Fault Isolation Procedures Option Procedure

On Classic B&L console, check the electrical operation of the associated switch on the radio control panel using Diagnostic 15. If the switch fails the test, replace the module containing the switch. Verify that the personality PROM on the COIM is properly programmed and contains the proper firmware. Check for a red LED on the associated COIM.
K70 and K578
K235
On Classic B&L console, check the electrical operation of the associated switch on the RCP using Diagnostic 15. If the switch fails the test, replace the module containing the switch. If the test fails on one channel but not on the other, replace the BIM associated with the failed channel. If the test fails on all the channels and if the connections between the console and the CEB are tight, the problem is probably the personality PROM in the associated COIM.
K56, K143, K710 and K711
On Classic B&L console, check the electrical operation of the associated switch on the radio control panel using Diagnostic 15. If the switch fails the test, replace the module containing the switch. Substitute another properly equipped BIM, making certain that the proper firmware is installed and that the address switch is set identically.
K59, K139, K146, K170, K380, K700, K713, K714, K715, K744, K748, and K766
Substitute another properly equipped BIM, making certain that the proper firmware is installed and that the address switch is set identically. Verify that the personality PROM on the COIM is properly programmed and contains the proper firmware. Check for a red LED on the associated COIM.
K60, K123, K124 and K138
On Classic B&L console, check the electrical operation of the associated switch on the radio control panel using Diagnostic 15. If the switch fails the test, replace the module containing the switch. Substitute another properly equipped BIM, making certain that the proper firmware is installed and that the address switch is set identically. Verify that the personality PROM on the COIM is properly programmed and contains the proper firmware. Check for a red LED on the associated COIM.
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Options
Troubleshooting
Table 4-5
Fault Isolation Procedures (continued) Option Procedure

If the test fails on one channel but not on the other, replace the BIM associated with the failed channel. If the test fails on all the channels and if the connections between the console and the CEB are tight, the problem is probably the personality PROM in the associated COIM.
K735, K739 and K757
K48 and K121
Substitute another properly equipped BIM, making certain that the proper firmware is installed and that the address switch is set identically. Verify that the personality PROM on the COIM is properly programmed and contains the proper firmware. Check for a red LED on the associated COIM. The AUX I board located above the appropriate BIM may be jumpered incorrectly. Refer to the Auxiliary I Module section of this manual for jumper information.
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Options
Troubleshooting
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Troubleshooting
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5 5 Maintenance
and Diagnostics
About this chapter

Section
Fault maintenance Error messages Diagnostics Replacing boards
Page
5-2 5-13 5-37 5-68

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Chapter 5
Maintenance and Diagnostics
Fault maintenance
Fault maintenance
CENTRACOM Gold Series consoles are designed to ensure the highest possible reliability. To this end, the console contains a sophisticated fault maintenance system that has the following goals: p p p p Limit the impact of a single failure to just one module. Regardless of the failure mode, recover as much functionality as possible without human intervention. Detect, isolate, and report malfunctions.
There are several methods by which faults in the console can be isolated. These are: Audio loop tests The console continuously runs audio loop tests to verify audio signal paths through the system. There are seven audio loop tests; each consists of a 30 msec tone burst of 2175 Hz. p Keypad diagnostics These are tests that are initiated by service personnel from the operator position keypad (on Buttons and LEDs and CRT operator positions). The results of the tests can be directed to an external terminal or printer. The audio loop tests that the console performs automatically can also be manually initiated as keypad diagnostics.
Fault maintenance features

The fault maintenance system consists of distributed hardware and software that identifies and isolates defective modules, thus minimizing the impact on total system performance. To aid in this process and to increase console reliability, the following items are included in the console.
Redundant system timer modules

The system timer provides the master timing signals for the entire console, so a failure in the timer could disable the entire radio system. Therefore, CENTRACOM Gold Series consoles have redundant system timer modules. If a failure is detected in one system timer module, the other is automatically placed into operation. When both modules are functioning properly, the system alternates between them, switching modules each evening around midnight.
Double three-state circuitry

Bus drivers on all boards use double three-state circuitry, which ensures that a module with an error condition is electrically isolated from the system. This prevents the errant operation of one module from affecting other modules.
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Maintenance and Diagnostics Fault maintenance
Separate communication path for COIMs

The console operator interface module (COIMs) communicate with each other over an exclusive data communications bus that is separate from the system data communications bus, to provide for redundant operation and to prevent a defective module from seizing control of the system data bus.
Timer circuits
Watchdog timer circuits are built into all CEB modules to detect malfunctioning microprocessors. Software timers are included to detect data communication failures.
Response times
The fault maintenance system diagnoses problems in the following time spans: p p Audio processing circuit problems take up to two minutes to be diagnosed. Data communication network problems take up to 20 seconds to be diagnosed.
If the system contains main and alternate BIMs and DRs, the main module is normally active. If the main module fails, the alternate module is automatically activated. After failure, the switching time is 20 to 120 seconds. When a switch takes place, there may be a noise burst at the console. After a BIM is switched, the base station associated with the standby BIM is initialized.
Recovery mode
Three types of events cause the system to go into Recovery mode: p p p If two modules fail within 10 seconds of each other. If two modules are pulled from the card cage within 20 seconds. If there is a bus driver/three-state failure.
In Recovery mode, all console operations cease for up to two minutes. As Recovery mode attempts to isolate the faulty module, there are popping sounds at the console and an OOPS message appears on the clock display of the operator position (or a System Error message appears on an Elite Console screen). The red LED on the modules is lit. During the recovery sequence, check the COIM diagnostic messages on the printer/ terminal. After the recovery sequence, check the CEB for red LEDs, which indicate failed modules. Then replace any faulty modules as explained in this manual.
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Fault maintenance
Failures not detected by fault maintenance system

It is recommended that a Fault Maintenance diagnostic system status dump be performed at least once every six months to detail the faults detected automatically by the fault maintenance system. Refer to Running diagnostics from an external printer or readout device on page 5-60 . There are certain failures that cannot be automatically detected by the fault maintenance system: p
Switch and LED failures on a Classic Buttons and LEDs operator position
Initiate diagnostic 15 as detailed in this manual to check these components. It is recommended that this be done at least once every six months. p
Operator position failures
The fault maintenance system does not test the other aspects of the operator position electronics. p
Software errors
A console or channel may rarely lock up in an undesirable state. If this occurs, press the red ReSet button on the affected module. This causes a software restart. If possible, document the symptoms of the problem and the sequence of operator actions that led to it. If it is possible to recreate the problem repeatedly, notify your Motorola field service personnel.
Fault maintenance operation

The CENTRACOM Gold Series fault maintenance system is a distributed software system that resides on each COIM. When an error occurs in a system with more than one COIM, each COIM diagnoses the problem independently of the others and then votes as to how to handle the error. The majority vote determines the systems response. This prevents a single COIM, which itself may be in error, from trying to correct an error that does not exist. Other CEB modules have a passive role in the fault maintenance system. These modules respond to interrogation by the COIMs. The fault maintenance system consists of two basic sections: p p The error check routines continually monitor system functions and alert the error servicing routine when they detect an error. The error servicing routine determines the majority vote concerning an error and acts to correct it and minimize loss of system capability.
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Error check routines

Each error check routine performed by the fault maintenance system is described below. p
Sound off check
Each TDM slot user is required to send a sound off packet on the data bus at five-second intervals. This test checks for data bus users jumping slots, for new users appearing on the bus, or for current users dropping off the bus. p
Sent packet check
A COIM sends a data packet and immediately reads it back. This verifies proper operation of the data bus. p
Cyclic redundancy check on incoming packets
The COIM checks data packets from other users for bit errors. Two errors within a certain time period indicates an error. p
Guard tone check
Guard tone from the system timer module is routed to all modules by means of the CEB backplane. The presence of this tone is checked by the COIM. p
RAM/ROM address check
Each CEB module compares its TDM slot address, determined from its on-board DIP switches, with its image stored in RAM to make sure the module does not jump to a different TDM slot. p
Internal tone continuity check
When a transmit function is not in progress, guard tone from the system timer module is periodically gated onto the COIMs tone detector. The COIM detects the tone and verifies proper operation of its tone detector. See COIM internal loop test on page 5-6. p
External tone continuity check
Tone continuity checks can be performed by each COIM through all BIMs and DR modules in the system as well as through itself. Guard tone from either the system timer module or a COIM (sourcing guard tone into its TDM slot) can be gated through these modules and put on the TDM bus in their assigned slots. The COIM, listening to the bus, verifies whether or not tone is present. Four loop paths are tested through the BIM, one path through the DR, and one path through the COIM. Each of these paths are explained in the Tone Loop Tests section. p
Radio control board (RCB) sound off and continuity check
The COIM can verify communications with the RCB in the operator position by requiring the RCB to periodically send a data packet down its dedicated serial link.
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Fault maintenance
Tone loop tests

This section describes the purpose of each tone loop test. The tone loop tests, which are run by the fault maintenance system automatically, can also be initiated manually using keypad diagnostics. The results of the most recent tone loop tests can also be called up using keypad diagnostics.
NOTE Keypad diagnostics are only available on a Classic operator position. (See Running diagnostics from the operator position on page 5-37 for an explanation of diagnostic routines).
COIM internal tone loop test

This is a self-test on the tone detector circuits. It is executed before any other tone loop test and can be initiated by the system or by the technician. Results for this test can be called up using diagnostic routine 10.
TDM BUS
COIM
DRM
A/D
SLOT RECEIVERS 2, 3, 4
A/D
BIM
TONE DETECTOR LOOP 1 LINE DRIVER P ANALOG GATE GUARD TONE
D/A
A/D DLM
MICROPROCESSOR
CEN034 021496JNM
Figure 5-1
COIM internal tone loop test
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Chapter 5
COIM system timer guard tone loop test

This test checks the ability of the COIM to digitize audio and place it on the TDM bus. Refer to Figure 5-2. Initiate the test for each COIM by using console diagnostic 13. Diagnostic 2 displays the results for each COIM in the system according to their TDM slot addresses. The results of this test appear on the CEB diagnostic print-out in the column entitled MUX GT.
TDM BUS
COIM
DRM
A/D
A/D
BIM
TONE DETECTOR
D/A LINE DRIVER P ANALOG GATE
GUARD TONE
A/D DLM
MICROPROCESSOR
CEN035 021496JNM
Figure 5-2
COIM system timer guard tone loop test
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Fault maintenance
BIM system timer guard tone loop test

This test checks the receive path of the BIM. Depending on the BIMs TDM address, a different slot receiver may be tested. Initiate the test for each BIM by using console diagnostic 13. Diagnostic 02 displays the results for each BIM in the system according to their TDM slot addresses. The results of this test appear on the CEB diagnostic print-out under the column entitled MUX GT. Refer to Figure 5-3.
TDM BUS
COIM
DRM
A/D
A/D
BIM
GUARD TONE LINE DRIVER D/A ANALOG GATE GUARD TONE P MICROPROCESSOR A/D DLM GUARD TONE TONE DETECTOR
CEN036 021996JNM
Figure 5-3
BIM system timer guard tone loop test
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BIM TDM tone loop test

This test checks the ability of the BIM to communicate in both directions with the TDM bus. Refer to Figure 5-4. Depending on the BIMs TDM address, a different slot receiver may be tested. Initiate the test for each BIM by using console diagnostic 13. Diagnostic 02 displays the results for each BIM in the system according to their TDM slot addresses. The results of this test appear on the CEB diagnostic print-out under the column entitled TDM LP.
TDM BUS
COIM
DRM
A/D
A/D
BIM
TONE DETECTOR
GUARD TONE
MICROPROCESSOR A/D DLM
CEN037 021496JNM
Figure 5-4
BIM TDM tone loop test
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Fault maintenance
BIM micro-generated tone loop test

This test checks the BIM microprocessors ability to generate function tone data under COIM control. This test is executed only: m on COIM initialization m once every 24 hours (approximately 12:00 midnight) m when a COIM is forced to execute this via diagnostic 13) Depending on the BIMs TDM address, a different slot receiver may be tested. Manually initiate the test for each BIM by using console diagnostic 13. Diagnostic 02 displays the results for each BIM in the system according to their TDM slot addresses. The results of this test appear on the CEB diagnostic print-out under the column entitled MICRO GT.
TDM BUS
COIM
DRM
A/D
A/D
BIM
TONE DETECTOR
D/A
LINE DRIVER
ANALOG GATE P
GUARD TONE
MICROPROCESSOR
A/D
DLM
CEN039 021496JNM
Figure 5-5
BIM micro generated tone loop test
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Chapter 5
BIM phone line transformer tone loop test

This test uses the transmit circuits, which means that the XMIT line driver is on and guard tone test audio is present at the output transformer. Since guard tone appears on the phone line, parallel remotes without notch filters recite this tone. This test is executed only: m on COIM initialization m once every 24 hours (approximately 12:00 midnight) m when a COIM is forced to execute this test via diagnostic 13. This test may fail if the output of the BIM is adjusted too low. Refer to Figure 5-6 for the test signal path. Depending on the BIMs TDM address, a different slot receiver may be tested. Initiate the test for each BIM by using console diagnostic 13. Diagnostic 02 displays the results for each BIM in the system according to their TDM slot addresses. The results of this test appear on the CEB diagnostic print-out under the column entitled PH XFRM.
TDM BUS
COIM
DRM
A/D
A/D
BIM
GUARD TONE TONE DETECTOR
GUARD TONE
MICROPROCESSOR A/D DLM
CEN038 021496JNM
Figure 5-6
BIM phone line transformer tone loop test
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Fault maintenance
DR system timer guard tone loop test

Each of these tests checks the receive path of a Dual Receive Module (DRM). The first test is run on the number one receiver, then the next TDM slot is selected and the second receiver is tested. Depending on the DRs TDM address, a different slot receiver may be tested. Initiate the test for each DR by using console diagnostic 13. Diagnostic 02 displays the results for each DR in the system according to its TDM slot address. The results of this test appear on the CEB diagnostic print-out under the column entitled MUX GT.
TDM BUS
COIM
DRM
GUARD TONE 7A A/D DLM SLOT RECEIVERS 2, 3, 4
A/D DLM GUARD TONE 7B
BIM
TONE DETECTOR
D/A
LINE DRIVER
ANALOG GATE P
GUARD TONE
MICROPROCESSOR
A/D
DLM
CEN040 021496JNM
Figure 5-7
DR system timer guard tone loop test
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Chapter 5
Maintenance and Diagnostics Error messages
Error messages
This section describes the error messages that may appear on the external printer or readout device. The external printer must be connected to view the error messages. The procedure for connecting an external printer is also provided in this section.
Connecting an external printer or readout device

For diagnostics, CEB connection from the RS232 board to a PC can be performed using a BKN6181 cable and information viewed using a terminal program. A diagnostic port is provided on the BLN6755 RS-232-C Interface Board which allows a diagnostic terminal or printer to be connected to the CEB using the options slot above a COIM, LOMI, AIMI, CIMI, or TIMI board. The external device can be remotely controlled from the CEB via a modem for enhanced serviceability. To connect directly to a terminal, use a BKN6107A RS-232-C cable. To connect to a modem for remote access, use a BKN6122A Modem RS-232-C cable. The BKN6122A cable is normally used for the TIMI-to-TCI link. Connect either cable to J3 on the RS-232 board in the CEB. If 212A modems are used on a dedicated phone line for remote access, then the modem switch settings for SW7 and SW8 are as follows (C = Closed, O= Open): At terminal end:
SW7 1
O
2
C
3
O
4
O
5
O
6
O
7
O
8
O
SW8
1
C
2
O
3
C
4
O
At COIM end:
SW7 1
C
2
C
3
O
4
O
5
O
6
O
7
O
8
O
SW8
1
C
2
O
3
C
4
O
The terminal-end modem is set for Forced Originate, the COIM-end modem is set for Forced Answer. Each modem is set for:
p p p p
private line DTR ignored asynchronous 10 Bit per character operation
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Error messages
When used for COIM, AIMI, or LOMI diagnostics, the diagnostic terminal must be configured at 300 baud, 8 data bits, 1 stop bit, and no parity. To use the diagnostic terminal for TIMI or CIMI diagnostics, the terminal must be configured for 9600 baud data. All other parameters are the same as those listed for COIM diagnostics. The terminal used must assert a DATA TERMINAL READY signal by pulling pin 20 of the BKN6107A or BKN6122A cable high (+ 5V to + 12V). If the DATA TERMINAL READY signal is not present, data is not sent to the terminal.
Interpreting error message printouts

The table below shows the five-part sequence of diagnostic routines the system follows to resolve a problem and the error messages that may appear in each part. The errors are then described in greater detail.
Part
1. System integrity compromised
Possible Error Messages

CRC error Data packet failure No data busy interrupt No data grant No data slot interrupt Duplicate slot = xx Hrdw-RAM mismatch Hrdw addr. is xx RAM addr. is yy Internal error Invalid slot xx Missing slot(s) = xx No 10Hz clock No sound off activity No System Timer guard tone Rcv CRC errors No Sys Timer Maintenance switch Unscheduled System Timer switch Via write error
2. Problem recognition
System Timer Switch Active System Timer = A (or B)
3. Re-evaluation of system integrity
Errors are: No errors detected any of the errors in part 1
4. Action taken and result
Reset missing slot Reset successful Reset unsuccessful Three-state Vote for Recovery Recovery
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Part
Recovery messages:
Possible Error Messages

System OMI(s) = xx yy OMI = xx Abort tone test Slot Status
4. Action taken and result Recovery Status messages: Echo pck Echo reply xx Gt. pck xx Gt. reply No slot rcv xx No tone Pwr up pck Pwr up reply Pwr down pck Pwr down reply TRF Recovery messages: Failed slot(s) = xx yy Active slot user(s) - aa bb cc No response 5. End of error handling sequence Other system status and error messages Q.E.D AIMI system fault maintenance ASTRO TBIM ACIM link status CIMI system fault maintenance Local 12V restored New slot user(s) = xx yy No ack from RCP No Sys Timer maint. switch No 10Hz clock RF signaling modem status Slot assignment Slot receiver status Sys power supply failure Sys power supply restored System Timer maintenance switch Tone continuity test status
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Error messages
Part 1: System integrity compromised

CRC error
When a COIM formats a data message, it calculates a two byte CRC (Cyclic Redundancy Check) code which appears at the end of the data message. This CRC assures the integrity of the whole data message. When transmitting a data message, the COIM reads back the last two bytes of the data to verify the transmission correctness. This check performs two functions: p p Verifies the integrity of the data arbiter located on the system timer module. Assures that no one module is misusing the data bus.
This error message indicates that this COIM has experienced the transmission of two or more data messages with faulty CRC within the last 10 second interval. This error can be caused by incorrect busy bus jumpering on a module (refer to the As-Built document).
Data packet failure

This message occurs if a COIM cannot access the data bus on either a transmit or a receive data packet. This type of error is followed by one or more of the following error messages: p p p No data busy interrupt No data grant No data slot interrupt
Any COIM experiencing this problem votes for a system timer module switch. If only one COIM reports the error, then the failure can be isolated to that COIM. If all COIMs report the error, then the system timer module is at fault. m No data busy interrupt This message indicates that this COIM failed to detect the beginning of a data message transmission (indicated by detecting a change of state in the DBSY signal), whether the data message originated from another module or from itself. DBSY is generated by the system timer module when its data arbiter grants a module the use of the data bus. DBSY appears as a processor interrupt on the module requesting the use of the data bus. m No data grant This message indicates that this COIM failed to send a complete data packet on the data bus. With this error alone, the COIM is still capable of listening to the bus. For this type of failure mode, either the COIM failed to send a data request (DRDY) or the system timer module failed to recognize the COIMs data request. m No data slot interrupt This message indicates that the synchronization signal, used to notify the COIM that it is time to transmit or receive the next data byte, did not occur. This signal originates on the system timer module and appears on the COIM as SF (start of frame) interrupt.
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Duplicate slot = xx
This message indicates that two or more slots have been assigned the same TDM slot address as determined by the modules DIP switch settings. This message generally occurs at system initialization, or when a new module is inserted into an active system. Either one or both modules three-state. A DR module occupies two slots on the TDM bus. The DIP switch address must be programmed on an even boundary. As a result, the DR address +1 automatically defines the second slot address. Therefore, addressing another module at any DR address +1 results in a duplicate slot error message. This error is detected immediately upon inserting an incorrectly programmed module. Verify the DIP switch settings on the affected boards. If the address is correct, there may be a hardware problem on one of the modules (e.g., microprocessor not reading the DIP switches properly).
Hrdwr-RAM mismatch Hrdwr addr. is xx RAM addr. is yy

At system initialization, each module reads the hardware address programmed on its DIP switches. A copy of this address is then stored in RAM and is referred to as the modules hardware address. The DIP switch address is continually compared to the module hardware address stored in RAM. If a mismatch occurs, due to either a memory or hardware failure, the module sends a message to all COIMs with both addresses contained in the message packet. The hardware address displayed is not necessarily the DIP switch address, since the failure could be in the hardware associated with the DIP switches. After sending this message, the module three-states. Other diagnostic action follows, indicating that this slot is now missing. This type of failure occurs if the DIP switches are purposely changed while the module is active in the system. If the error occurs because the DIP switch settings were changed during operation, press the reset button on the module. If the error occurs spontaneously during operation, the module should be replaced.
Internal error
This message indicates a serious internal error and always causes the COIM to three-state (red LED on). The COIM must be replaced.
Invalid slot xx
This error occurs either on system initialization or when a new module is inserted into an active system. The problem occurs if the module DIP switches are programmed for an address greater than the maximum allowable. Any module with incorrect DIP switch addresses, except the COIMs, sends a message packet containing this address, and then three-states. Since this module was never logged into the system, no further diagnostic action occurs. The valid address range is 00 - 5F hexadecimal. For Embassy systems the address must be less than 20 hexadecimal.
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Error messages
This error also occurs when a COIM is inserted into an active system and the TDM address of the DIP switches does not match the TDM address contained in the personality PROM.
NOTE If the DIP switches were programmed incorrectly, make the necessary corrections and press the reset button.
Missing slot(s) = xx
This message indicates that the module with address XX failed to send a sound off message over the data bus for two consecutive five-second sound off intervals.
No 10 Hz clock
This message indicates that the time base located on the system timer module used for generating the real time clock is malfunctioning. If all operator positions display this message, then the source of this problem is the 10 Hz clock circuitry located on the active system timer module. This type of failure alone does not cause the system to switch to the redundant system timer module. When the scheduled switch to the redundant module occurs, the error clears. If only one operator position displays this error, the source of the problem is the input circuitry located on the COIM which reported the error. If all COIMs report the error, the active (green LED) system timer module is defective and must be replaced. The problem can be immediately remedied by removing this module from the CEB (the redundant system timer module takes over immediately). Replace the defective module as soon as possible, so that the system has a functional redundant timer.
No sound off activity

This message indicates that all modules in the system failed to send a data message during the past two consecutive five-second sound off intervals. This message is a possible indication that the data arbiter is faulty on the system timer module.
No System Timer guard tone

Between module-to-module tone continuity loop testing, each COIM performs an internal tone test. This test verifies that the system timer module is generating guard tone, and that the tone detector located on the COIM can detect it. No digitization of the guard tone occurs in this test. This error indicates a failure to detect guard tone in this manner. This test shares common circuitry with voice from the radio control panel, with voice receiving higher priority. Therefore, when this error is detected, the error servicing routine waits 45 seconds for a system timer module switch to allow other system COIMs to detect this
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error. If a system timer module switch does not occur after this 45-second interval, then most likely the error is contained on that particular COIM.
No Sys Timer maint. switch

This message indicates that the switch to the redundant system timer module, scheduled to occur once every 24 hours (usually around midnight), did not occur. The vote/status circuitry which controls the switch is located on system timer module A. If all operator positions report this error, this vote/status circuit is faulty. However, if this error is reported by only one operator position, then the status circuitry on the associated COIM is faulty. During normal system operation all COIMs vote for the same system timer module. As a result, the vote signal should always be either a logic high or logic low rather than at half supply voltage.
If active System Timer Module is...
The Vote Signal is... And Status Signal is...
A
high low
B
low high
This message can also occur if the time of day clocks at each operator position are not synchronized, such as in a system without a Level I Supervisor COIM.
Rcv CRC errors

This message indicates that three or more data messages received in a five-second interval failed data integrity checks. This might be the only message received if a new module is plugged into the system and it consistently fails to send a complete data message. As a result, this module is never recognized as a new active user by the rest of the system. After approximately two minutes, this module three-states. If a module has three-stated (red LED on), it must be replaced. If the error occurs repeatedly at only one COIM, that COIM should be replaced. If it occurs repeatedly at more than one COIM, the system timer module active at the time of the error may be defective. It can also occur when new modules are plugged into the system (due to disruption of the data bus). In that case, it should be ignored unless it occurs again when the system is stable.
Unscheduled System Timer switch

This message indicates that a system timer switch has occurred due to one of the following reasons: p p The vote circuitry, located on System Timer A, has forced a switch under hardware control. The majority of the system COIMs have detected an error which requires a switch in order to proceed with further error processing.
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Error messages
This message can also be caused by the clocks not being synchronized. This can occur if there is no Supervisor Level I COIM installed in the system, or within two minutes of a new COIM being installed in the CEB.
VIA Write Error

This error indicates that this COIM could not successfully vote for the redundant system timer module. After a COIM votes for the redundant timer, it reads back its vote to ensure that its vote circuitry is operating properly. This failure occurs if the system is unable to obtain a majority vote to switch to the redundant timer. Replace the COIM if this failure occurs.
Part 2: Problem Recognition

System Timer switch
This message indicates that the majority of the system COIMs have detected an error and have voted for a system timer module switch which has now occurred. This is an informational message that does not indicate an error.
Active System Timer = A (or B)

This message indicates the system timer module that is active after the majority of the system COIMs voted for a switch, which has now occurred. This is an informational message that does not indicate an error.
Part 3: Re-evaluation of system Integrity
NOTE All the messages listed in part 1 can also occur in part 3.
Errors are:
This message indicates that the system COIMs are now evaluating system integrity under operation of the currently active system timer module. Any errors incurred within this evaluation period (approximately 10 seconds) are displayed.
No errors detected
This message indicates that this COIM experienced no errors while operating under this system timer module. This usually means that the system timer module active prior to the switch (now with the yellow LED) may be defective. It may also be part of a normal
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sequence during installation or troubleshooting, such as the error sequence initiated when any module other than the inactive system timer is removed from the CEB.
Part 4: Action taken and result

Reset missing slot
This message indicates that all system COIMs that detected this missing module will now send it a reset message in an effort to restore it to full integrity.
Reset successful
This message indicates that the previously missing module was capable of accepting the reset message, and is now present and sending sound off messages. This indicates a spurious failure, and requires no further action. If the same slot repeatedly causes this message sequence, that module should be replaced.
Reset unsuccessful
If no sound off messages were received within 10 seconds of sending the reset message, then this module is logged off the system and Reset Unsuccessful is displayed. If the reset attempt was not successful, the failed module three-states (red LED on). Resetting the module manually may bring it back into the system. If this fails, or only succeeds temporarily, replace the module.
NOTE If a standby module is assigned to this base station site, all subsequent transmissions are directed through the standby module.
Three-state
Three-state refers to a slot being electronically removed from the system buses. This message indicates that the COIM has been three-stated. This condition indicates a serious nonrecoverable error. The COIMs red LED is on when it is three-stated, which occurs under the following conditions: p
Duplicate slot assignment
The duplicate slot assignment is this COIMs slot address. p

Hardware-RAM address slot assignment
This COIMs address, as stored in RAM, no longer agrees with the address as programmed by the DIP switches.
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Error messages
Recovery poll failure
This COIM did not correctly respond when being interrogated by the controlling COIM during a recovery sequence. p
Three-state
The COIM is three-stated because a system timer switch did not occur. If this COIM experiences any error which would ultimately result in a recovery sequence, but neither the initial nor second switch occurs, this COIM three-states. p
Invalid slot number
This COIMs slot address is higher than the maximum allowable. Valid slot addresses are from 00 - 5F hexadecimal. For Embassy systems the address must be less than 20 hexadecimal.
Vote for recovery

This message indicates that this COIM has placed a second vote (i.e., a vote back to the original system timer module), indicating that an error has been detected after the initial system timer module switch which requires a recovery sequence to resolve.
Recovery
This message indicates that the majority of system COIMs have experienced one or more of the errors detected after the initial system timer module switch and have voted and detected a second system time module switch. All COIMs now three-state from the buses. All CEB modules three-state in approximately 30 seconds. The entire console is nonfunctional during the recovery sequence. The procedure that follows evaluates each module in the CEB, and those which fail remain three-stated (red LED on) at the conclusion of the recovery sequence. The COIM with the lowest address becomes the controlling COIM and attempts the recovery sequence by coming out of three-state mode and performing the following: p Send a dummy message to itself to verify correct CRC. If it fails this test it three-states and passes control to the COIM with the next highest address. If equipped with an external device, the message Data Packet Failure appears. Verify that internal tone checks are correct for system timer module guard tone, tone detector resetting, and tone detector falsing. Verify that this COIM is sourcing guard tone into its assigned slot on the TDM bus. Begin interrogating all modules for data bus integrity and guard tone being sourced into its assigned slot on the TDM bus.
p p p
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NOTE Recovery also occurs if two or more slots are lost within a 10-second period (such as during servicing). If multiple modules must be removed for maintenance, remove them slowly (not more than one every 30 seconds) to prevent the recovery sequence from occurring and causing the system to go off the air.
Recovery messages in Part 4

System OMI(s) = xx yy
This message lists the TDM slot addresses of all COIMs in the system. This message occurs only during a recovery sequence.
OMI = xx
This is the TDM slot address of the controlling COIM, the COIM which is currently executing the interrogation process. This message occurs only during a recovery sequence.
Abort tone test

If, during the initial attempt to begin a recovery sequence, this COIM fails to pass its internal tone tests, it causes this message and discontinues these tests if it becomes the controlling COIM once again.
Slot status
A sample slot status printout is shown below. This printout occurs after the recovery sequence, and is the result of the recovery interrogation process as seen by this COIM, which is not necessarily the TDM slot address of the COIM conducting the interrogation. For example, the COIM with address 01 might be conducting the interrogation process, but the external device (i.e., printer) is connected through the COIM with address 03.
Sl ot Stat us 06 P w r up r epl y 07 P w r up r epl y 5E No slo t r cv 5F No slot r cv
One or more of the following 14 recovery status messages may occur as a result of the recovery interrogation process. Only slots which failed some portion of the interrogation process are listed in the printout. These error messages are printed only during the recovery sequence.
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Error messages
Recovery status messages in part 4

Pwr up pck
The controlling COIM was unable to send a power-up packet to the interrogated module.
Pwr up reply
The interrogated module failed to come out of three-state and send a power-up reply to the controlling COIM. If the controlling COIM was sending spurious data request (DRDY) signals to the data arbiter, then all slots interrogated will terminate here with the Pwr Up Reply message. In this case, the controlling COIM recognizes that communication is impossible and therefore three-states and passes control to the next COIM in the system.
Echo pck
After the interrogated module returned from three-state mode, the controlling COIM could not conduct two-way data communication between itself and the module. The module could be sending spurious DRDY signals to the data arbiter.
Echo reply
The interrogated module failed to send a message to the controlling COIM acknowledging that it received the echo packet.
xx Gt. pck
The controlling COIM was unable to send a guard tone packet to the interrogated module. This packet indicates that the interrogated module should send 30 milliseconds of guard tone into its slot. xx is the slot receiver that this COIM uses to detect the tone.
xx Gt. reply
The interrogated module failed to send a message to the controlling COIM acknowledging that it received the guard tone packet. xx is the slot receiver that this COIM uses to detect the tone.
No slot rcv
The controlling COIM failed to find a working slot receiver mapped to the same TDM bus that the interrogated module is sourcing digital audio into.
xx No tone
The controlling COIM failed to detect the guard tone sent by the interrogated module. The module could be sourcing guard tone into the wrong slot on the TDM bus, or it could have previously failed this test unrelated to the recovery sequence. xx is the slot receiver that the controlling COIM uses to detect the tone.
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Pwr dwn pck

The controlling COIM was unable to send a power down packet to the module presently being interrogated.
Pwr dwn reply

The interrogated module failed to send a message to the controlling COIM acknowledging that it received the power down packet.
TRF
The COIM prints this message, which means Tone Reset Failure, opposite the interrogated module if, during the recovery sequence, the COIM could not successfully reset its tone detector. If this COIM has control, it passes it to the next COIM in the system. This COIM aborts the tone test if control returns to it.
Recovery messages
Failed slot(s) =xx yy . . .
This is a summary of the slot status data and indicates modules that failed to pass the interrogation process. This message occurs only during the recovery sequence. In the message printout, xx yy represents the address of any modules which failed to pass all tests during the recovery sequence. They remain three-stated (red LED on) and should be replaced. If a group of modules have failed (such as an entire card cage), first check the power supplies and daisy-chain cables.
Active slot user(s) = aa bb cc ...

This is a summary of the module addresses which are currently in the system after the recovery process and are sounding off. This message occurs only during the recovery sequence.
No response
If the controlling COIM completes the interrogation and finds that no module successfully passed the interrogation process, this message is printed and control is passed to the next COIM in the system. This error occurs if the COIM controlling the interrogation is bad or if both system timer modules are bad.
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Error messages
Part 5: End of error handling sequence

Q.E.D.
This message indicates that the controlling COIM has concluded the current error sequence.
Other system status and error messages

The following messages indicate an error or change in system status. They are asynchronous messages. These errors do not cause a switch to the redundant system timer module.
AIMI system fault maintenance

This message displays the status of the AIMIs within the COIMs CEB. The message appears in Embassy systems only. A sample printout of this message appears below.
AIMI system I.D. = 00 Main = 5E Alt = 5F Global Q = 05 Q = 05 01/01/96 00:00:08 Standby Active
Global indicates that the CEB is communicating to the AEB (Ambassador Electronics Bank) through the AIMI/AMB link. There are two other possible status messages: Local, indicating that the CEB is not communicating with the AEB; or Initial, indicating that the CEB is initializing and status has not yet been determined. The second and third lines of the message display the status for the Main and Alt AIMIs respectively. p
Main/Alt = 5E
This indicates whether the AIMI is the main or Alternate. 5E is the AIMIs TDM slot assignment. p
Q = 05
This indicates the quality of the AIMI/AMB link. 05 indicates good quality. Any number other than 05 indicates an error. p The AIMI status can be one of the following:
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Active
This AIMI is currently in control of audio and data communications with the AEB.
Standby No Link Config AEB Fault No sound off activity Mismatch CEB IDs
This AIMI is ready to move to the Active state if the currently active AIMI fails. The link between AIMI and AMB is down. The link between AIMI and AMB is up, but audio summing has not completed. Two different CEBs are configured to use the same AEB backplane bus. This is a system configuration error. The AIMI is not sounding off as a TDM console slot user, and therefore is considered failed. There is a mismatch between the COIM and AIMIs AEB/CEB ID. One or both IDs are programmed incorrectly.
ASTRO TBIM ACIM link status

This message shows the status of the BIM/ACIM link, ACIM/DIU link, and ACIM EEPROM for ASTRO trunking BIMs (TBIMs) within the COIMs CEB. This message occurs only in a SMARTNET ASTRO system. An example of this message is shown below, along with a description of the possible messages.
Astro Slot 4 5 6 7 TBIM Type TRK_TR TRK_TR TRK_TR TRK_TR Link-ACIM Status Sys 0 0 0 0 SoundOff PASS PASS FAIL PASS Tone_Tests PASS PASS PASS PASS 01/01/96 02:31:35 BIM_ACIM_L ink Link Up Link Down ------Link Down ACIM_DIU _Link Link Down ------------------ACIM_E2 PASS -------------------
Slot
The TDM slot assignment of the TBIM. p

Type
The circuit type of the ASTRO TBIM p

Sys
The console-trunked system ID the TBIM is assigned to p

SoundOff
PASS indicates that this module is sounding off, otherwise dashes are printed. p
Tone-Tests
The PASS/FAIL status of the modules tone test.
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Error messages
BIM_ACIM_Link ACIM_DIU_Link
The status of these links can be Link Up, Link Down, or dashes, indicating the status is unknown. p
ACIM_E2
The status of the EEPROM on the ACIM board. The status can be either PASS, FAIL, or dashes, indicating that the status is unknown.
CIMI system fault maintenance

This message displays the status of the CIMIs within the COIMs CEB. This message appears in non-Embassy systems only. An example of this message is shown below.
CIMI System I.D. = 00 Active system = MAIN
01/01/96 00:00:12
Main Subsystem - Main CIMI = 00 Main Subsystem - Alt CIMI = 01
Active Standby
Alt Subsystem - Main CIMI = 03 Alt Subsystem - Alt CIMI = 04
Standby Standby
CIMI System I.D. = 0
This is the CIMI system ID used within the CEB. p

Active system - MAIN
This indicates which subsystem is active Main or Alt. The next lines display which CIMI is the Main or Alt in each subsystem, the TDM slot assignment of the CIMI and the current operating status of the CIMI. Only one of the four possible CIMIs can be active at the same time.The CIMI will have one of the following statuses:
Active Standby No Link No sound off activity
This CIMI is currently in control of communications with the CAD. This CIMI is ready to move to the Active state if the currently active CIMI fails. The link between the CIMI and CAD is inoperative, or the CAD is not sending data on the link. The CIMI is not sounding off as a TDM console slot user, and therefore is considered failed.
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Local 12V restored

In the event that the 12 V regulator on the COIM has failed, no message can be directed to the external device to report this error, since the COIM requires 12 V in order to operate. This message appears at the external device when the error clears (12 V restored). A lack of 12 V power also breaks the link between the COIM and the operator console (LD appears on the clock display of Classic Buttons and LEDs and Classic CRT consoles).
New slot user(s) = xx yy . . .

This message occurs whenever a new module is inserted into the system and begins sending sound off messages. Tone continuity tests execute at an accelerated rate and the new module tone status is sent to the external device. If more than one slot user is inserted into the system before the tone test status is printed, only the most recent new slot user tone status is printed.
No ack from RCP

This message indicates a problem with the link from the COIM to the operator position Radio Control Panel.
No Sys Timer maint. switch

This message indicates that the switch to the redundant system timer module, scheduled to occur once every 24 hours (usually around midnight), did not occur. The vote/status circuitry which controls the switch is located on system timer module A. If all operator positions report this error, this vote/status circuit is faulty. However, if this error is reported by only one operator position, then the status circuitry on the associated COIM is faulty. During normal system operation all COIMs vote for the same system timer module. As a result, the vote signal should always be either a logic high or logic low rather than at half supply voltage.
If active System Timer Module is...
The Vote Signal is... And Status Signal is...
A
high low
B
low high
This message can also occur if the time of day clocks at each operator position are not synchronized, such as in a system without a Level I Supervisor COIM.
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Error messages
No 10 Hz clock
This message indicates that the time base located on the system timer module used for generating the real time clock is malfunctioning. If all operator positions display this message, then the source of this problem is the 10 Hz clock circuitry located on the active system timer module. This type of failure alone does not cause the system to switch to the redundant system timer module. When the scheduled switch to the redundant module occurs, the error clears. If only one operator position displays this error, the source of the problem is the input circuitry located on the COIM which reported the error. If all COIMs report the error, the active (green LED) system timer module is defective and must be replaced. The problem can be immediately remedied by removing this module from the CEB (the redundant system timer module takes over immediately). Replace the defective module as soon as possible, so that the system has a functional redundant timer.
RF signaling modem status

This message displays the status of the link between the BIM and modem for signaling modules within the COIMs CEB. It also displays the status of the signaling modules self test and EEPROM. An example of this message is shown below.
RF signaling Modem Status slot 06 07 0E sys S00 S00 S00
09/20/95 13:01:36 Link state Link Up Link Up Link Up EEPROM Status PASS PASS PASS self test PASS Not Executed PASS
p p p
slot The TDM slot assignment of the signaling module. Sys An S followed by the system ID of the slot. link state The status of the BIM/modem link can be one of the following: Link Up The BIM/modem and modem/external device link (if applicable) are up Ext Device Link Down The modem/external device link is down. Bim/Modem link is down The modem/external device link status is unknown No BIM Sound off The BIM is not sounding off as a TDM console slot user, and therefore is considered failed.
self test The status of the self test run on the signaling modem can be PASS, FAIL, or Not Executed.
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EEPROM status The status of the EEPROM or the signaling modem can be PASS, FAIL, or ------(unknown).
Slot assignment
This message displays the slot assignments within the COIMs CEB. This display shows the TDM slot assignment, the type of module and the status of the module. Dashed lines indicate the module is inactive in the system. A sample slot assignment message is shown below.
Slot Assignment 02 07 0B 0F 13 5E SGB SGB SGB SGB SGB AIM -----Active ---------------Active 03 08 0C 10 14 5F SGB SGB SGB SGB BIM AIM -------------------------Active 05 09 0D 11 16 SGB SGB SGB SGB TOM --------------------Active 06 0A 0E 12 17 SGB SGB SGB SGB TOM Active -----Active -----Active
Slot receiver status

This message gives the pass/fail status of all slot receivers in use by a COIM. The pass/fail data is obtained as part of the tone continuity loop testing. The slot receivers are used in listening to the TDM bus and converting the digitized tone to analog form for detection by the tone detector. Slot receiver 00-01 will never be used. p p p Slot receivers 02-04 are located on the COIM. Slot receivers 05-07 are located on the first audio expansion interface module (if used). Slot receivers 08-10 are located on the second audio expansion interface module (if used).
A sample slot receiver status printout is shown below. Status possibilities are as follows:
** PASS FAIL NTEX Slot receiver does not exist Test executed successfully. Test executed unsuccessfully. Test could not be executed.
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Error messages
Sl ot rec eiver statu s 09 /20/9 5 13: 01:3 7
00 **
01 **
02 PASS
03 NTEX
04 NTEX
05 **
06 **
07 **
08 **
09 **
0A **
0B **
0C **
0D **
0E **
0F **
10 **
11 **
12 **
13 **
14 **
15 **
16 **
17 **
18 **
19 **
System power supply failure

The CEB has a redundant power supply operating in hot standby. A power sense lead from each supply is wire ORed and routed to each COIM. Should a failure occur in one of these supplies, the power sense lead changes state and causes this error message. All COIMs should experience this error if a power supply has indeed failed. Only one COIM reporting this error indicates a fault local to the COIM.
System power supply restored

This message occurs when a system power supply fault is cleared.
System timer maintenance switch

This message is normally printed once per day just after midnight and indicates that the system timer modules have switched.
Tone continuity test status

This message precedes the tone continuity status of modules in the system. Upon initialization of a COIM, all modules are evaluated within a few minutes (depending on system size) and results printed to the external device. See the Tone Loop Tests section for a description of the tone loop tests performed. As new modules are installed, their status is printed. Since tone failures are not catastrophic errors (modules may still retain some
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functionality), those modules do not three-state (green LED still lit), but should be replaced. Status possibilities are:
**** NTEX PASS FAIL FC This test is not applicable for this module. Test could not be executed. Module was transmitting, receiving, or had received audio within the last 30 seconds. Test executed successfully. Test executed unsuccessfully. Test failed with contingency.
DR modules appear as two consecutive slots on the printout, though only one module (at the even address) exists in the CEB. The status of the COIM slot receiver should be verified as OK before replacing modules. Failure with contingency is rare, and indicates that there was insufficient information available to determine whether a module had failed or the COIMs own slot receiver had failed. If the failure is seen at only one COIM, the slot receiver associated with that TDM slot is the likely failure.
NOTE Jumpering on the BIM and DR modules is critical. Make sure the module is jumpered properly before replacing it. An improperly jumpered module may also cause another module to fail its tone tests. For example, a module at address 26 (hex) jumpered for MUX bus 1 would place its audio on top of the audio from the module in address 06, and no audio in its correct slot. Both modules would probably fail tone tests.
Tone cont inui ty test statu s
Tone continuity test status ************Tone tests************ slot 06 07 0E 16 17 5E type SGB SGB SGB TOM TOM AIM sys S00 S00 S00 mux gt PASS NTEX PASS PASS PASS **** **** tdm lp PASS NTEX PASS **** **** **** **** micro gt PASS NTEX PASS **** **** **** **** ph xfrm PASS NTEX PASS **** **** **** ****
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SmartNet trunking system status

11/24/84 09:24:56 Trunking system I.D. = 00-3F Active Central - Main Trunking Central Switch Failure Trunking Main Subsystem - Main TIMI = 00 c Active Main Subsystem - Alt TIMI = 01 c Hot Standby Channel Availability = 19/20 Failsoft repeaters = 00 Alt Subsystems - Main TIMI = 03 Standby Alt Subsystem - Alt TIMI = 04 No sound off activity Channel Availability = No prior history Failsoft repeaters = 00
This message shows the current status of a SmartNet trunking system available to this COIM. p
Trunking system I.D. = 00-3F
The first two digits represent a console-trunked system ID. The console-trunked ID is used within the CEB and is not known by the Trunking Central Controller (TCC). The second two-digit hexadecimal number is the last two digits of the trunking system ID. The trunking system ID is known by the TCC. Multiple trunking systems connected to the CEB have unique console-trunked IDs, but the second two digits of the trunking system ID may be the same. p
Active Central - MAIN
This message indicates the subsystem that the trunking fault maintenance system thinks is active (main or alternate). In a system with only one TCC, MAIN is always displayed. When a switch between centrals occurs, a change in status is sent from the TCC to the CEB. p
Trunking Central Switch Failure
This message indicates that an attempt to switch between Main and Alternate trunking subsystems has failed. In this case, there are several points of possible malfunction: m The BIM which invokes the switch has failed m The link between the BIM and switch mechanism has failed m The subsystem switching mechanism has failed m An operator has invoked a switch which bypasses COIM redundancy firmware. No message is displayed if the switch is successful.
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Trunking
This message represents the current console operating status for this trunking system. The message can be one of the following formats:
Trunking Failsoft Idle The console is operating successfully in a trunking environment. The TCC is inoperative, but the console is operating in a conventional manner (non-trunked mode). The console is neither in trunking nor failsoft mode for this trunking system.
Timi Status
The next lines indicate which TIMI is the Main or Alt in each subsystem, the TIMIs TDM slot address, and its current operating status. Only one of the possible four TIMIs can be active at any one time. A TIMI can have the following status:
Active No link Hot Standby Standby The TIMI is currently communicating with the TCC(TCC) regarding channel assignments. The data link between the TIMI and the TCC is inoperative. This TIMI is ready to accept the active state without loss of call status in the event that the now Active TIMI fails. This TIMI is mapped to the idling TCC. In the event that the now active subsystem fails, this TIMI is ready to accept the ACTIVE state upon switching to this subsystem and having the TCC lock onto a control channel. All call status is lost on switching between subsystems. This subsystem has no TBIMs presently sounding off in the CEB. This implies that all channels are disabled at the TCC, thereby rendering the system inoperative. To avoid this, the TIMIs mapped to this subsystem disable themselves at the TCC, causing the TCC to make mobile channel assignments independent of console disability. This TIMI is not sounding off as a TDM console slot user, and therefore is considered failed. Consequently, it cannot be used in this trunking system.
Disabled
No sound off activity
NOTE The character c that appears after the TIMI TDM slot address indicates that the TCC has locked onto a control channel. This signifies that the system can begin trunking. When this information is received by the COIMs, a TIMI is selected and placed in the ACTIVE state so that the console operator positions can begin communicating over the trunking system.
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Channel Availability = 019/020
For the given subsystem there are a total of 20 channels, of which 19 are currently available for channel assignment. If this availability drops below the customer designated value stored in memory, a switch to the idling subsystem results, if the CEB is configured with automatic switching and there are redundant TCCs.
Channel Availability = No prior history If the trunking system is configured with two TCCs sharing repeaters, channel availability can only be determined on the active subsystem. When the idling subsystem becomes active, channel availability is calculated for this subsystem. The channel availability on the formerly active, now idle, subsystem is frozen. The No prior history message is not applicable in a system with two TCCs, each with unique repeaters. If an F appears after the channel availability print-out, the subsystem is considered to be in failsoft mode. The trunking fault maintenance system does not switch to this TIMI unless a data message from the TCC negates the failsoft status, or diagnostic 17 followed by the console-trunked system ID is entered through the RCP keypad.
Channel Availability yyy/xxx F
Failsoft Repeaters = 000
This message gives the number of repeaters currently not being controlled by the TCC. Unless the system is in failsoft, these repeaters cannot be assigned for voice transmission. As a result, these repeaters are in a failsoft mode of operation.
SmartZone trunking system status

Tr unki ng s ystem I.D . = 00 - 03 Tr unki ng
This message shows the current status of a SmartZone trunking system available to this COIM. p
Trunking System ID=00-3F
The first two digits represent a console-trunked system ID. The console-trunked ID is used within the CEB and is not known by the Zone controller. The second two-digit hexadecimal number is the last two digits of the trunking system I.D. The trunking system I.D. is known by the zone controller. Multiple trunking systems connected to the CEB have unique console-trunked I.D.s, but the second two digits of the trunking system I.D. may be the same. p
Trunking
This message represents the current console operating status for this trunking system. The message can be one of the following formats:
Trunking Idle The console is operating successfully in a trunking environment. The console is neither in trunking nor failsoft mode for this trunking system.
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Maintenance and Diagnostics Diagnostics
Diagnostics
Running diagnostics from the operator position
Several diagnostic routines can be executed at the console operator position.
Classic Buttons and LEDs operator position

1. 2.
Press and hold , then D. dIAG appears on the display. Enter the two-digit diagnostic code on the keypad and again press .
To exit the diagnostic mode, press and hold the shift key and then D. If after 35 seconds, the system senses absence of keypad activity it will exit the diagnostic mode automatically.
Classic CRT operator position

1. 2. 3.
Click on the Special button. Click on the Diagnostics selection. Do one of the following:
3.1 3.2
enter a valid diagnostic code and click on Enter. Select one of the diagnostic selections from the display, then click on Perform.
Gold Series Elite operator position
NOTE These routines are not currently available on an Elite operator position.
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The following table describes the two-digit diagnostic codes available.

Diagnostic 00 Diagnostic 01 Diagnostic 02 Diagnostic 03 Diagnostic 04 Diagnostic 05 Diagnostic 06 Diagnostic 07 Diagnostic 08 Diagnostic 09 Diagnostic10 Diagnostic 11 Diagnostic 12 Diagnostic 13 Diagnostic 14 Diagnostic 15 Diagnostic 16 Diagnostic 17 Diagnostic 18 Diagnostic 19 Diagnostic 20 Diagnostic 21 Diagnostic 22 Recall last displayed error. Display active System Timer module Tone continuity module status Slot receiver status Display system errors Display memory contents Personality PROM- Module address definition Not applicable for CENTRACOM Gold Series consoles Initiate phone line transformer loop test Operator interface high impedance state errors Internal tone test status Display system status to external device Clear clock decimal points Execute unique module loop tests System power supply status LED/switch/potentiometer check Data bus packet traffic monitor Clear history of trunking subsystems Not applicable for CENTRACOM Gold Series consoles Not applicable for CENTRACOM Gold Series consoles Not applicable for CENTRACOM Gold Series consoles Memory diagnostics MSEL/paging regroupability
Diagnostic 00 Recall last displayed error

One of the display formats described in this section is displayed, or one of the following diagnostic codes:
duP xx
Where duP indicates duplicate module assignment, and xx is module address; range: 00-5F hexadecimal, 00-20 hexadecimal for Embassy systems. A duplicate module assignment message generally occurs at system initialization, or when a new module is inserted into an active system. This message indicates that two modules have the same address. Either module or both modules are three-stated (red LED). A DR module occupies two slots (addresses) on the TDM bus. The DIP switch address on the DR module is programmed on an even boundary. As a result, this hardware address + 1 automatically defines the second slot address. Therefore, addressing another module at any DR address + 1 results in a duplicate address error message.
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r CrC
Receive CrC (cyclic redundancy check) errors. Indicates that three or more data messages received in a five-second interval failed integrity checks. In most cases other diagnostic action follows. When a new module is plugged into the system an r CrC may be the only message received if the module consistently fails to send a complete data message. As a result, this module is never recognized by the rest of the system. After approximately two minutes, the module is three-stated and isolated from the rest of the system.
NO CLOC
The radio control panel clock is not keeping accurate time. If all operator positions display this message, the source of this problem is the 10Hz clock circuitry located on the active system timer module. This type of failure alone does not cause the system to switch to the redundant system timer module. When the scheduled time of day switch to the redundant module occurs, the error clears. If only one operator position displays this error, the source of the problem is the input circuitry located on the COIM board which reads this signal.
AdCOn xx
AdCOn indicates an address conflict, and xx is the hardware or DIP switch address read by the microprocessor. At system power-up, each module reads its assigned address as programmed on the DIP switches. The programmed DIP switch address is referred to as the hardware address. The assigned address is also stored in memory (RAM) and continually compared to the hardware address for a match. If a match does not occur due to either a memory or hardware failure, the module sends a message to all COIMs with both addresses contained in the message packet. The hardware address read by the faulty module is displayed on the clock. This address is not necessarily the correct DIP switch address, since the failure could be in the hardware associated with the DIP switches. After sending the message, the module enters the high impedance state. Since the module is now effectively isolated from the system, other diagnostic action follows indicating that this slot is missing. This type of failure occurs if the DIP switches are intentionally changed while the module is active in the system. If this type of failure occurs on a COIM, no message is sent and the COIM does not three-state. A FAILEd message is displayed on the clock. The consequence of the COIM not going into the high impedance state is that its digital audio may move into another slot on the TDM bus. Audio from both channels is lost, and increased difficulty is experienced in identifying the faulty module since the module is not three-stated (red LED).
ArnGE xx
Indicates an address out of range. xx is the address of the module. This error occurs on system power-up or when a new module is inserted into an active system. The problem is caused by DIP switches programmed for an address greater than the maximum allowable. All modules, with the exception of COIMs, send a message packet containing the address to all system COIMs, and then go into the high impedance state (red LED). Since this module was never logged into the
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system, no further diagnostic action occurs. If this error occurs on a COIM the message FAILEd appears on the clock display. The valid address range is 00-5F hexadecimal. In an Embassy system the valid address range is 00-20 hexadecimal.
10d FAIL
A Scheduled switch to the redundant system timer module did not occur. If all operator positions report a 10d FAIL, the vote/status circuitry located on system timer module A is faulty. However, if this error is displayed at only one operator position, the status circuitry on the COIM at this operator position is faulty. During normal system operation (no error presently being serviced) all COIMs vote for the same system timer module. As a result, VOTE is always a logic high or logic low. If system timer module A is active, VOTE is high and STATUS is low. If system timer module B is active, VOTE is low and STATUS is high. p
FAILEd
The COIM controlling this operator position is three-stated. Refer to diagnostic 09 for further information. p
OOPS
A system error has occurred and is presently being serviced. When the error servicing routine has completed execution, real time (time of day) is restored to the clock display. Refer to diagnostic 04 for further information. p
Means no errors have occurred.
Diagnostic 01 Display active System Timer module

The display has the following format:
CA r d - x
where x is the active system timer module A or b.
Diagnostic 02 Tone continuity module status

Six loops are provided in the system for tone continuity checks. There are four such loops on a BIM, and one loop on both the COIM and DR modules. No loops exist on data only modules. After entering diagnostic 02, a prompt Addr is displayed. Enter a two-digit active module address within the range 00-5F hexadecimal (00-20 hexadecimal in an Embassy system). If an out of range address is entered, the lowest active module address is returned. If the address entered is not active, the next highest active module address is returned. The following information is displayed in an eight-digit format (digit 1 is the left-most digit):
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Digits 1-2: module address
Range: 00-5F hexadecimal 00-20 hexadecimal in an Embassy system p

Digits 3-4: module type
Values:
Ir dr dA GO GI GR LO IC CI AI Sr -
BIM DR module data only module COIM trunking interface module - TIMI TBIM LORI intercom interface module CAD interface module - CIMI Ambassador Interface Module - AIMI Signaling BIM not assigned
Digits 5-8: module status
Values:
P F n -
passed test failed test not executed yet test not applicable
To advance to the next highest address, choose 1. To advance to the next lowest address, choose 0. Data modules, TIMIs and CIMIs do not use their assigned time slots on the TDM bus to transmit data to other modules, they use the data bus only. As a result, no tone tests are executed on these modules. The module status represents the pass/fail data for a specific loop test as defined below: p
Digit 5: System Timer Guard Tone Loop (MUX GT)
The tone source for this test is the guard tone generated on the system timer module. This is the same tone used to key base stations in a tone controlled system. The BIM and DR module gate the guard tone into transmit filters and route the output of the filters into the DLM(S) (digital level memory). The DLM output is applied to an encoding/decoding chip, which converts the analog audio to PCM (pulse code modulation) audio and inserts it into the correct time slot on the TDM bus. The COIM then detects this particular slot and converts the tone back to analog form via its slot receiver. The analog tone is then routed to a tone detector. See page 5-8 and page 5-12 for diagrams of this test for a BIM and a DR, respectively. A COIM follows the same procedure outlined above, with the exception that no DLM exists on this module. See page 5-7 for a diagram of this loop test.
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Digit 6: TDM Tone Loop
Refer to page 5-9 for a figure illustrating this test, which is applicable to BIMs only. The tone source for this test is provided by the COIM controlling the tone polling process. The COIM receives guard tone from the system timer module, digitizes it, and inserts it onto the assigned TDM bus slot. The specific BIM being polled listens to the COIM slot, and after converting the guard tone to analog form, gates it into the transmit filter, and routes the output of the filters into the DLM(s). The DLM output is applied to an encoding/decoding chip, which converts the analog audio to PCM (pulse code modulation) audio and inserts it into the correct time slot on the TDM bus. The COIM then detects this particular slot and converts the tone back to analog form via its slot receiver. The analog tone is then routed to a tone detector. p
Digit 7: Micro Generated Tone Loop (MICRO GT)
Refer to page 5-10 for a figure illustrating this test, which is applicable to BIMs only. The tone source for this test is the BIM microprocessor. The guard tone is routed into the DLM. The DLM output is applied to an encoding/decoding chip, which converts the analog audio to PCM (pulse code modulation) audio and inserts it into the correct time slot on the TDM bus. The COIM then detects this particular slot and converts the tone back to analog form via its slot receiver. The analog tone is then routed to a tone detector. p
Digit 8: Phone Line Transformer Tone Loop (PH XFRM)
Refer to page 5-11 for a figure illustrating this test, which is applicable to BIMs only. The tone source for this test is the guard tone generated on the system timer module. In this test the guard tone is routed to the phone line transformer and looped back on the tertiary of the transformer to the DLM. The DLM output is applied to an encoding/decoding chip, which converts the analog audio to PCM (pulse code modulation) audio and inserts it into the correct time slot on the TDM bus. The COIM then detects this particular slot and converts the tone back to analog form via its slot receiver. The analog tone is then routed to a tone detector. Refer to diagnostic 08 for further information on this tone loop test.
Diagnostic 03 Slot receiver status

This test displays the pass/fail status of all slot receivers in use by a COIM. The pass/fail data is obtained as part of the tone continuity loop testing. The slot receivers listen to the TDM bus and convert the digitized tone to analog form for detection by the tone detector. Each COIM and each AEI module has three slot receivers. After entering diagnostic 03, the status for the slot receiver at address 01 is displayed. Also included in the display format is MUX bus to slot receiver mapping. Each of the three MUX buses in the system has a capacity of 32 addresses, for a total system capacity of 96 addresses or slots. To advance to the next highest address, press 1. To advance to the next lowest address, press 0. The display format is as follows (digit 1 is the left-most digit): p p p p 5-42 Digits 1-2: slot receiver address range: 01-19 (hexadecimal) Digit 3 blank Digits 4-5 MUX bus assignment; range 01-03 Digit 6 blank
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Digits 7-8 slot receiver status: P F FC n pass fail contingency failure not executed not assigned
If a module fails to have its tone detected during a tone loop polling process, both the polled module and the slot receiver which listened for the tone may be faulty. If the next module polled on this slot receiver does have its tone detected, then this slot receiver is no longer suspected of being faulty. If one or more slot receivers are still suspected of being faulty after all modules are polled under a given test number, then a secondary poll is initiated to resolve these uncertainties. This secondary poll is executed by the COIM with the potential slot receiver failure(s). All other COIMs passively wait for this module to resolve these uncertainties. If, during this secondary poll, all modules mapped to a given slot receiver fail to have their tone detected, then this slot receiver has failed. If fewer than three modules are available on this slot receiver, then the modules have failed and the slot receiver may also have failed.
Diagnostic 04 Display system errors

Diagnostic 04 detects the cause of the OOPS error message. If, after entering diagnostic 04, the display contains ----, then no system errors have occurred and there is nothing in memory to display. After entering this diagnostic, the keypad digits 0 and 1 allow you to scroll through the data. Diagnostic 04 allows you to compare system errors before and after a system timer switch (if it occurs). The display format is as follows (digit 1 is the left-most digit): p Digit 1: Current or Past Data If an A is displayed, this indicates that the remaining display digits are displaying data after the system timer module switch. If a b is displayed, this indicates that the remaining digits are displaying data before the system timer module switch. p Digit 2: Error Categories The sequence values 0, 1, 2, or 3 are displayed. A b0 displayed in digits 1 and 2 represents test data before the system timer module switch, and A0 represents data after the system timer module switch. Similarly, b1 is compared to A1, b2 is compared to A2, etc. With this comparison information, you can observe the effect that the new system timer module has on system integrity. If the remaining digits (3-8) are blank, the switch to the redundant system timer module did not occur. p p Digit 3: blank Digit 4: System Timer Module Identification If the letter b is displayed in digit 1 (representing errors before the system timer switch) and the letter A is displayed in digit 4, then system timer module A was active before the error occurred.
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Digits 5-8: Pass/Fail Status Digits 5-8 display the pass/fail data of particular system tests. The test data appears as P or F, for pass or fail respectively. The number of digits displayed in digit locations 5-8 and the test data they represent is dependent upon the error category, as displayed in digits 1 and 2. The following is a detailed explanation of the test data given by digits 5 - 8.
CASE 1: Digits 1 & 2 are A0 or b0: p p p Digit 5: blank Digit 6: blank Digit 7: Sound Off Activity A failure indication in digit 7 indicates that all modules in the system failed to send a data message over the data bus during the previous 5.0 second sound off interval. p Digit 8: Cyclic Redundancy Check (CRC) Errors. When a COIM formats a data message, it calculates a two-byte CRC which appears at the end of the data message. The CRC assures the integrity of the whole data message. When transmitting its own data message, the COIM reads the last two bytes of its data message to verify correctness. This verifies: m the integrity of the data arbiter on the system timer module m that no module is misusing the data bus. CASE 2: Digits 1& 2 are A1 or b1: p Digit 5: Data Grant Interrupt Failure A failure indication in digit 5 is associated with the inability of a COIM to transmit on the data bus. The module is still capable of listening to the bus (detecting sound off activity from other modules). If this failure occurs, either the hardware circuitry on the COIM did not send a data request to the system timer module (indicates that this COIM has a failure) or the system timer module failed to recognize the data request (indicates that all COIMs exhibit this failure). p Digit 6: Data Slot Interrupt Failure A failure indication in digit 6 indicates that synchronization signal A4, used to notify the module that it is time to transmit or receive the next data byte, did not occur. This signal originates on the system timer module and appears on the COIM on pin 92 of the edge connector. As in digit 5, isolating the failure depends on whether all or only one COIM detects the error. p Digit 7: Data Busy Interrupt Failure A failure indication in digit 7 indicates that the module failed to detect the beginning of a data message transmission, whether its own or from another module. This signal (DBSY) originates on the system timer module and changes state when the data arbiter grants a new module use of the data bus. As in digit 5, isolating the failure depends on whether all or only one COIM detects the error.
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Digit 8: Data Message (Packet) Failure A failure indication in digit 8 indicates that the module was unable to transmit a data message during the previous sound off interval with correct CRC. In general, this failure flag is overlapped by the other errors already described above. That is, if any failures occur in digits 5 - 7, a failure in digit 8 may or may not indicate a CRC error. If digits 5 - 7 do not show any failures and digit 8 does, a CRC error does exist.
CASE 3: Digits 1 & 2 are A2 or b2 : p p Digits 5-7: blank Digit 8: System Timer Guard Tone Failure Between module-to-module tone continuity loop tests, each COIM performs an internal tone check. The internal tone check is used to verify that the system timer module is generating guard tone and that the tone detector located on the COIM detects the presence of the guard tone. The guard tone is not digitized during this test. A failure to detect guard tone in this manner is indicated by digit 8. Isolating the failure depends on whether all or only one COIM detects the error. CASE 4: Digits 1 & 2 are A3 or b3 : p Sound Off Integrity Check If a sound off integrity failure occurs, digits 5 and 6 contain either a module address or a numerical value representing the total number of slots which failed to sound off during the previous sound off interval. m If digit positions 7 and 8 contain a P, then digits 5 and 6 are blank. m If digit position 7 contains a P and digit position 8 contains an F, two or more modules failed to sound off during the previous sound off interval. Digits 5 and 6 contain the total number of missing modules. m If digit position 7 contains an F and digit position 8 contains a P, only one module failed to sound off. The slot address of the failed module is contained in digits 5 and 6. m If digit position 7 contains an F and digit position 8 contains an F, two or more modules failed to sound off during the previous sound off interval. The total number of modules not sounding off are contained in digits 5 and 6. Any occurrence of an error as described for diagnostic 04 results in the COIM voting for a switch to the redundant system timer module. If after the system timer switch, the errors as described in A0, A1, or A3 (two or more missing modules only) are still present, this COIM votes a second time for a switch to the original system timer module. If the switch to the original system timer module occurs, indicating that the majority of modules are experiencing the same failure modes, a recovery sequence immediately follows.
Diagnostic 05 Display memory contents

After entering diagnostic 05, the console display prompts you to enter the eight-digit address of the desired location in mapped memory (RAM or ROM). Unmapped memory or memory addresses mapped to peripherals are not displayed. Instead, the display shows the contents of the next highest mapped memory location. To advance to the next highest address, press 1. To reread the same location, press 0.
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Digit positions 1-6 of the display contain the six least significant digits of the address of the memory location being displayed (digit 1 is the left-most digit). Digit positions 7 and 8 contain the hexadecimal value of the data stored in that memory location.
Diagnostic 06 Personality PROM - Module address definition

Diagnostic 06 displays the module type as defined in the personality PROM. It also indicates whether the slot address displayed is active or not. After entering diagnostic 06, a prompt (Addr) is displayed. Enter a two-digit module address within the range 00-5F hexadecimal. To advance to the next highest address, press 1. To advance to the next lowest address, press 0. The following format is displayed (digit 1 is the left-most digit): p p p Digits 1-2: module address; range 00-5F hexadecimal, 00-20 hexadecimal in an Embassy system Digit 3: blank Digits 4-5: module type: Ir dr dA GO GI BIM DR module data only module COIM TIMI
GR TBIM LO LORI IC CI AI Sr p p intercom interface module CAD interface module - CIMI Ambassador Interface Module - AIMI Signaling BIM not assigned
Digit 6: blank Digits 7-8: module status: AC module active EP empty/no activity
Diagnostic 07
Not applicable for CENTRACOM Gold Series consoles.
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Diagnostic 08 Initiate phone line transformer loop test

Diagnostic 08 initiates a microcomputer generated loop test and a phone line loop test to the transformer on a BIM. Refer to page 5-11 for a figure illustrating this test. This test is automatically executed when a COIM becomes active, and once a day when the system timer modules switch. When this test is executed, guard tone is heard in parallel remotes or desk sets which do not have guard tone notch filters. After entering diagnostic 08, a prompt (Addr) is displayed. Enter the address (range: 00-5F, 00-20 for Embassy systems) of the BIM to be tested. If it is desirable to test all BIMs, enter FF. No action is taken if you enter the address of any other type of module. Use diagnostic 02 to observe results of the test if the system does not have an external printer.
Diagnostic 09 Operator interface high impedance state errors

Diagnostic 09 determines the cause of a FAILEd message (indicating COIM is three-stated) on the display. The following is an explanation of the display once diagnostic 09 is entered (digit 1 is the left-most digit): p p Digit 1-2: E1 where E1 is an identifying label. Digit 3: P Or F Module Address Out Of Range Upon power-up the COIM reads its module address as programmed on the hardware DIP switches and verifies that it is within the valid address range 00 - 5F hexadecimal or 00-20 hexadecimal for Embassy systems. If it is not within this range it immediately goes to the high impedance state (red LED). p Digit 4: P Or F 2nd System Timer Switch Failure & Data Errors A second system timer switch failure indicates that this COIM voted for a recovery sequence, but the majority of the COIMs did not agree. In addition, this COIM experienced data errors, which include a lack of sound off activity, data transmit/ receive interrupts, or CRC errors. As an example of this type of failure, assume that a COIM is able to transmit on the data bus but cannot receive data packets. The COIM, recognizing that it no longer is receiving sound off activity from other modules, purposely stops transmitting sound off messages, causing other COIMs to vote for a switch to the redundant system timer module. Since the error is internal to the COIM, the switch to the redundant system timer module does not clear the problem, so this COIM again votes for a system timer switch because it assumes that this problem is affecting the entire system. At this point the other COIMs recognize that only one COIM is no longer sounding off. The other COIMs transmit a reset message to the failed COIM. However, since the COIM cannot receive data packets due to the nature of the failure, it times out and goes into the high impedance state (red LED).
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Digit 5: P Or F 1st System Timer Switch Failure & Data Errors This indicates that the COIM voted for a system timer switch because it detected data errors, but the switch to the redundant system timer module did not occur. These data errors include a lack of sound off activity, data transmit/receive interrupts, or CRC errors. As an example of this type of failure, assume that a COIM can receive data messages, but cannot transmit data messages. The COIM is therefore able to receive the reset message from the other COIMs and reinitializes itself. However, if the error does not clear, the COIM votes for another switch to the redundant system timer module. Since a switch had already taken place, all other COIMs recognize that this COIM cannot sound off and so delete it from their list of active modules. The failed COIM goes to the high impedance state (red LED).
Digit 6: Recovery Interrogation Failure A recovery interrogation failure indicates that a recovery sequence occurred and a COIM did not successfully pass all the tests. The tests include transmitting and receiving over the data bus, and receiving guard tone into the slot assigned to the COIM on the TDM bus. The specific nature of this failure and the complete interrogation results of other modules is available on a printer or terminal, if the system is so equipped.
Digit 7: P Or F RAM/ROM Address Mismatch At system power-up, each COIM reads its hardware address, as programmed on the DIP switches. The hardware address is also stored in memory (RAM) and the stored version is continually compared to the hardware address for a match. If a match does not occur due to either a memory or hardware failure, this COIM goes into the high impedance state (red LED). Since this COIM is now missing from the system, diagnostic action follows from the other COIMs in the system.
Digit 8: P Or F Duplicate Module Address Assignment A duplicate module address indicates that a COIM detected another module transmitting data packets with the same module address as itself.
Diagnostic 10 Internal tone test status

Between every individual tone loop test, each COIM executes an internal tone loop test in which analog guard tone is routed directly into the tone detector. Refer to page 5-6 for a figure illustrating this test. This checks the tone detectors ability to: p p p reset properly detect analog guard tone independent of other modules and digitization circuitry indicate a NO DETECT when guard tone is not routed into the tone detector (falsing).
The display format is as follows (digit 1 is the leftmost digit): p p p p Digits 1-4 Digit 5 Digit 6 Digit 7 lOnE indicates tone blank P or F Tone Detector Falsing P or F Guard Tone Failure (on system timer module or tone detector)
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Digit 8
P or F Tone Detector Reset Failure
If an error occurs in digit 7 (an F appears), the error is isolated by observing whether the error is unique to this module or common to all COIMs. If the error is unique to one COIM, then that module alone is at fault. If the fault is common to all COIMs, the system timer module is at fault and a switch to the redundant system timer module occurs.
Diagnostic 11 Display system status to external device

For systems equipped with an external display this diagnostic mode sends the following system parameters to the display. See Other system status and error messages on page 5-26 for further explanation of the displayed data. p p p p p p p p tone continuity status slot receiver status current module users system status dump
After entering diagnostic 11, a prompt (Addr) is displayed. Enter one of the following: FF for tone continuity status & slot receiver status FE for active module addresses FD for slot receiver status only A0 for system status dump The COIM with the external device (printer or terminal) connected to its option slot sends its status to the external device. The COIM then begins to interrogate other COIMs for their status, which it also directs to the external device. p p p A1 initiates/continues system status dump, but does not interrogate other COIMs for tone continuity status A2 continues system status dump, and prints tone continuity test status of all interrogated COIMs (which had been turned off by Addr Al). B0 halt (abort) system status dump
Diagnostic 12 Clear clock decimal points

Diagnostic 12 clears the clock display decimal points on Classic Buttons and LEDs operator positions and the holding buffer which contains the last displayed error. This mode should not be entered unless it is certain that the last fault is cleared. After executing diagnostic 12, subsequent calls to diagnostic 00 and diagnostic 04 display - - - - - - - -. During the execution of diagnostic 12, enter an address when prompted. At this point enter password AB, which allows the diagnostic to be performed. If diagnostic 12 is performed at the supervisor position, it is then performed automatically at all other operator positions in the system.
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Diagnostic 13 Execute unique module loop tests

Diagnostic 13 executes all applicable tone continuity loop tests on a unique module. After entering diagnostic 13, Addr is displayed. Enter a two digit module address within the range 00-5F hexadecimal or 00-20 hexadecimal for an Embassy system. If the module address entered is not an assigned address (currently sounding off), ErrOr is displayed. Once diagnostic 13 is entered and a valid module address is given, the display format is the same as for diagnostic 02, with all tests indicating a not executed condition (n). Tone continuity status for this module is erased at all parallel operator positions. The diagnostic firmware attempts to execute all applicable tone continuity loop tests for this module, completing the testing in approximately 15 seconds. While the tests are executing, the display is updated with the pass/fail status. When executing diagnostic 13 on a signaling BIM module, two messages appear. The first message may look like:
[03 Sr PP P]
Where Sr means signaling T/R. Then the system displays a second message, such as:
[03 SG U P]
Where SG U = signaling modem = link is up or: D=link is down N=BIM is not sounding off P = self test passed or: F=self test failed N=self test did not execute After the second display times out, the diagnostic ends. The modem self test result is forced to Not Execute when this diagnostic begins, as are the BIM tests results.
Diagnostic 14 System power supply status

The CEB has a redundant power supply operating in hot standby. A power supply sense lead from each supply is wired ORed and routed to each COIM. Should a failure occur to one of these supplies, the sense lead changes state and an error message is displayed at the operator position. All operator positions display this message when a power supply error occurs. An error message occurring at only one operator position indicates a fault local to the COIM. The system power supply status can be checked at any time using this diagnostic.
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The display format is as follows (digit 1 is the left-most digit): p p p Digit 1-3 Digit 4-7 Digit 8 PSS power supply status blank P or F pass or fail data
Diagnostic 15 LED/switch/potentiometer check

This diagnostic allows you to check the integrity of the console LEDs, switches and potentiometers on Classic Buttons and LEDs operator positions. This diagnostic will also display various system configuration parameters as shown in the following table. When this diagnostic is invoked, the switches and LEDs do not function in their normal manner. To end Diagnostic 15, press the shift key on the keypad. When the diagnostic is entered, the clock display shows:
88888 888
To verify the operation of all components of the operator position, do the following: Press each console control module (CCM) switch. Verify that its LEDs flash, verifying that they work, and causes the display to show information about the switchs function in the console. Releasing the switch results in the display:
LE d C HE C
Press each key on the keypad and verify that the display shows:
diS PL X
where X denotes the key you pressed. Press the keypad transmit switch and verify that the display shows:
dIS PL br
Press the keypad monitor switch and verify that the display shows:
dIS PL CS
Adjust each volume potentiometer and verify that the display shows:
LE VEL X
where X is a number in the range of 0 to 7, and represents the volume setting of the potentiometer. Adjust the potentiometer and verify that the full range is displayed. Pressing a switch located on a display console control module (DCCM) causes every dot on the DCCMs display to light. Press the transmit bar switch and verify that the display shows:
dIS PL BR
Without releasing the transmit bar, pressing other switches causes information about the corresponding channel to be displayed. The information displayed for each type of switch is described below.
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The same information, except for patch select, can be displayed on a Classic CRT console. Press and hold the middle mouse button (general transmit). While keeping it pressed, do one of the following: p Move the cursor to the desired Channel Control Window (CCW). Press the left mouse button to display SELECT switch information or press the right mouse button to display Instant Transmit Switch information. Move the cursor to the Main/Alt status line of a CCW. Press the left mouse button to display Main/Alt Switch information. Move the cursor to the Aux I/O line of a CCW or Auxiliary Control Window. Press the left mouse button in order to display Aux I/O information.
p p
Switch
CCM
Type
Non-Embassy
Embassy
Information
Display Format Select Instant Transmit Select Instant Transmit Select Instant Transmit Select Instant Transmit Conventional Conventional +TRK+ +TRK+ -TRK-TRK-TRK-TRK----Type I Type I Type II Type II In - SS Out- SS In - SS Out- SS F-AACCSS I tttt F-AACCSS ITTTiiii AA-CC-SS AA-CC-SS AA-CC-SS AA-CC-SS FI tttt FITTTiiii SS SS Rcv slot Xmit slit Rcv slot Xmit slot Failsoft slot System ID/trunking ID Failsoft slot System ID/ talkgroup/ individual ID In patch group ## at this console Patched at another console
Patch select Patch select
Patched at this OP Patched at parallel OP
---
PCH ## PCH BUSY
PCH ## PCH BUSY
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Switch
Patch select Main/Alt
CCM
Not patched anywhere Conventional ---
Type
Non-Embassy
PCH -SS
Embassy
PCH -AA-CC-SS
Information
Not patched anywhere TDM slot information of the other BIM in the Main/Alternate configuration Individual ID Location and type of Aux I/O
Instant Transmit Aux I/O

-- = any AA = AEB ID CC = CEB ID
Private Call
iiii SS-YZZ
iiii CCSS-YZZ
SS = Board TDM slot address ## = patch group index I = trunking system ID tttt = trunking ID iiii = individual ID TTT = talk group (no T bits) +TRK+ = trunking with repeater assigned -TRK- trunking without repeater assigned Y=Auxio number (hex) ZZ=Auxio type
Diagnostic 16 Data bus packet traffic monitor

Diagnostic 16 gives statistics about traffic on the CEB data bus. Enter diagnostic 16, when the Addr prompt is displayed, enter: 00 to display the maximum number of packets which passed on the data bus during a one second interval since the occurrence of: m last console reset m 02 input during execution of diagnostic 16. The display is updated every second. 01 02 to display the number of packets which passed on the data bus during the last one-second interval. The display is updated after each second. resets the maximum packet traffic value which is shown in diagnostic 16, address 00.
The display format is PAC xxx where xxx is the packets per second value.
Diagnostic 17 Clear history of trunking subsystems

This diagnostic is used when a redundant trunking system has been configured for automatic switching. This diagnostic will clear the trunking history of the idle subsystem, allowing for an automatic switch. The automatic switch will occur when either:
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Loss of both TIMI-TCI data links to the same trunking central controller fails. Besides an actual failure of the links, this can also indicate a malfunction of the TCC or the loss of all control channels or the loss of all voice channels.
p p
Loss of 50% of the maximum number of channels ever available And the following minimum capabilities are met by the idling subsystem m TIMI-TCI link established m The idling subsystem is NOT indicating Failsoft m Channel availability is either NO PRIOR HISTORY or, greater than 50% of maximum channels ever available or, less than 50% of maximum channels but greater than the active subsystem.
Enter diagnostic 17. When the SYS ID prompt is displayed, enter the two-digit system ID of the trunking system whose history is to be updated. If a non-existent trunking system ID is entered an error message will be displayed. An example of the effects of Diagnostic 17 are shown below. Before Diagnostic 17 is invoked:
Sys tem ID = 00 - 1F Ac tive Ce ntr al - Ma in Tr unki ng Main subs ystem - Ma in TIMI = 00 c A cti ve Main Sub syst em - Al t TIMI = 01 No Li nk Ch annel Avai labi lit y = 15/20 Fai lsof t r ep eater s = 000 Al t s ubsys tem - Mai n T IMI = 03 Stand by Al t S ubs ystem - Al t T IMI = 04 No Lin k Ch annel Avai labi lit y = 18/20 Fai lsof t r ep eater s = 000 f
After Diagnostic 17 is invoked:

Sys tem ID = 00 - 1F Ac tive Ce ntr al - Ma in Tr unki ng Main subs ystem - Ma in TIMI = 00 c A cti ve Main Sub syst em - Al t TIMI = 01 No Li nk Ch annel Avai labi lit y = 15/15 Fai lsof t r ep eater s = 000 Al t s ubsys tem - Mai n T IMI = 03 Stand by Al t S ubs ystem - Al t T IMI = 04 No Lin k Ch annel Avai labi lit y = No pr ior h isto ry
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Fai lsof t r ep eater s = 000
In this example, the maximum channels available is updated to the current channel availability on the active (main) subsystem (15/15). This can be done only if a link is established between the TCI and the TIMI. Channel availability ion the idle (alternate) subsystem is assumed to be one greater than the active (main) subsystem. The printout reflects this with the message no prior history. Failsoft status on the idle subsystem is negated. Should the link drop on the main subsystem, an automatic switch to the alternate subsystem will occur.
Diagnostics 18 to 20
Not applicable for CENTRACOM Gold Series consoles.
Diagnostic 21 Memory diagnostics

This diagnostic is used to access various memory locations used to examine the current state of the console. Enter diagnostic 21. When the Addr prompt is displayed, enter a digit to perform the function desired.The functions available are shown in the following table and described in the following paragraphs.
NOTE The information displayed with 0-5 can also be displayed on an external printer or readout device. See ESC DR on page 5-63.
Switch
0 1 2 3 4 5 Shift 0 6 7 8
Function
Display console freeze information Display console reset information Display analog mux claims Display timing message information Display heap status information Display infinite loop reset information Clear all above tables Display CEB mode (local, global, or undef if Embassy or NO AEB if non-Embassy) Display this consoles address/op number (toggle) Display this CEBs AIMI link info (toggles between main/alt AIMIs, NO AEB if non-Embassy)
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0 console freeze information A console may reset through a freeze or reset condition. After a freeze occurs, the console status is stored before the console resumes operation. The status may be read through diagnostic 21 by entering 0. The display shows:
CC CC EE AA
where CCCC is the error code, EE is the executive task running (in hex), and AA is the application task running (in hex). p 1 Console reset information A console may reset through a freeze or reset condition. After a reset occurs, the console status is stored before the console resumes operation. The status may be read through diagnostic 21 by entering 1. The display shows:
C CC CE EA A
where CCCC is the error code, EE is the executive task running (in hex), and AA is the application task running (in hex). p 2 Analog mux claims Several tasks can claim the console microphone. The status of the claims can be read by scrolling through this table. The table may be read through diagnostic 21 by entering 2. This causes the first task with a claim to the microphone to be displayed in the following format:
AA N NN N NN
where AA is the application task (in hex) and NNNNNN is the number of claims this task has on the microphone. NNNNNN should be 0 if this operator position is not using the microphone (not keying a channel or using selective intercom) The next application task in the table is displayed by entering 2 again. p 3 Timing messages The console has a watchdog timer which is used to reset the console if a task takes too much time. If the console misses strobing the watchdog timer eight times, the watchdog resets the console. The console firmware detects when it thinks the watchdog has made a count. This number can be read through diagnostic 21 by entering 3. The display shows the following:
C WWW
where WWW is the current watchdog count in decimal. A timing message is logged every time a task takes longer than 150 msec. If 3 is entered when the watchdog count is displayed then the timing messages are displayed. Entering 3 again scrolls through the table. Each timing message is displayed as:
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C CC E E A A
where CCC is the time that passed (hundredths of a second, decimal) EE is the executive task (in hex) and AA is the application task (in hex). The first timing message displayed is the last one that occurred, the next one is the one previous to that and the last one displayed is the oldest message. There is room for four messages in the table. After displaying all four, the first one is displayed again. p 4 Heap status The heap is the free memory available for system use. If the console resets due to heap overflow the heap status is stored in the heap table. The table can be read through diagnostic 21 by entering 4. The first message displayed is the number of bytes available to the system when the heap overflowed. The display shows the following: A BBBBB where BBBBB is the number of bytes available to the system in decimal. If 4 is entered when the heap size is displayed, then the heap status for each heap partition is displayed. Entering 4 again scrolls through the heap status table. For each heap partition the following is displayed:
B BB AS SS S
where BBB is the partition size being displayed (in decimal). A is E if this partition was being extended (getting more memory from the general pool) when the console reset, otherwise A is blank. SSSS is the number of blocks the system was using from this partition (in decimal) when the console reset. p 5 last task status If the COIM resets because of an infinite loop it will display the last task running before the reset occurred. When the COIM powers up it checks RAM before it is cleared, to get the last tasks running. If this was the first time the COIM was powered up the tasks are set to FF, FF. If the board reset, the task code of the last executive task and last application task are stored. The values can be read through diagnostic 21 by entering 5. The display shows:
L EE AA
where EE is the executive task code in hex and AA is the application task code in hex. p Shift 0: clear the tables Since the purpose of diagnostic 21 is to determine the cause of a console reset, resetting the console will not clear these tables. They must be manually cleared by entering diagnostic 21 and then entering shift 0. This same function can be performed using an external print or readout device. See ESC ID on page 5-63. This function can be performed on a classic CRT console. Once in Diagnostic 21, press the left mouse button. While keeping it depressed, press key 0 from the PC keyboard.
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6 Display CEB mode The display shows: LOCAL if this is an Embassy system in local mode GLOBAL if this is an Embassy system in global mode UNDEF if this is an Embassy system in undetermined mode NO AEB if this is not an Embassy system.
7 Display this consoles address/op num. Press N to toggle between the two displays.
Not Embassy
SL-SS OP-OMM
Embassy
AA-CC-SS OP-OMM
Info
AA = AEB ID, CC = CEB ID, SS = Board TDM slot address OMM = OP ID (MID)
8 Display this CEBs AIMI link info (toggle between main/alt AIMIs Display NO AEB if non-Embassy, otherwise display T AAQQ S T = type of AIMI (1 = main, 2 = alt) AA = AIMI CEB slot QQ = link quality (FF = null quality, 00 = no link, 05 = good quality. Anything else indicates a hardware problem) S = link state (A = active, d = down)
Diagnostic 22 MSEL/paging regroupability

The regrouping status of the three multi-select groups and the paging group as stored in EEPROM can be viewed and changed using this diagnostic. Exercise care when using this diagnostic, since by inhibiting the regrouping feature of multi-select and paging, you are using a trunking repeater for every subfleet in your MSel group. If there are more than a few subfleets in your MSel group, you could easily tie up all the repeaters in the system, inhibiting any other transmissions for the duration of your call. Choosing not to regroup the MSel groups is useful during installation of a new trunked system. The new trunked subfleets can be put in MSel groups with the old conventional channels and key up without the regrouping delay. Enter the diagnostic. The current regrouping status for MSEL1 group is displayed in the format SEL1 r or SEL1 n, where r = regroupable and n = nonregroupable. Press the 1 key to change the status. Press the 0 key to store the status for MSEL1. After you have stored the status for MSEL1, the status for MSEL2 is displayed. Press 1 to toggle the status and 0 to store it. Similarly, regroup status for MSEL3 and paging groups can be modified.
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Diagnostic 23 System repeater setup for fixed frequency paging

This diagnostic programs the system repeater switches with a specific trunking BIM (TBIM) slot address for fixed frequency trunked pages. The address is used when the operator sends pages to pagers that are on a specific repeater frequency used by the trunking system. Perform the following procedure.
1. 2.
Enter diagnostic 23. A SEL. . . prompt appears. Press the System Repeater switch you wish to program. A SYS ID prompt appears on the display. If the System Repeater switch was already programmed, the display shows SYSIDxx , where xx is the system ID previously programmed.
3.
Enter the two character console /trunked system ID of the trunking system to which the repeater that will be sent the pages is a member. Press the shift key to go to the next prompt. The display shows the ID.... prompt. If the System Repeater switch was already programmed, the display shows IDxxxxxx , where xxxxxx is the trunking ID previously programmed. Enter the six-digit decimal Trunking ID. The Trunking ID must be a valid ID in the trunking system that was chosen above. Duplicates of IDs already in use will be rejected.
4.
5.
6.
Press the shift key to advance to the next prompt. The display shows the Addr... prompt. If the System Repeater switch was already programmed, the display shows
ADDRxx , where xx is the address previously programmed.
7.
Enter the two-digit hex slot address ($00 - $5F) of the TBIM which is connected to the repeater which will be sent the pages. Press the shift key to advance to the next prompt. The display shows the SEL... prompt again.
8.
The system repeater switch is now programmed. You can now program another switch if desired.
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Running diagnostics from an external printer or readout device

Diagnostic status can also be directed to an external terminal or printer by entering commands at the keyboard. To invoke the commands, press the escape key, followed by the two letters identifying each diagnostic command. For information on connecting the external printer or readout device refer to Error messages on page 5-13.
Fault maintenance diagnostics

Each COIM in the system assesses various aspects of system integrity. Only one COIM has to have an external printer or readout device connected in order to obtain diagnostic system status. The COIM connected to the external device dumps its status when prompted by the operator. This COIM then interrogates all other system COIMS and similarly dumps their status to the external device. This section describes the fault maintenance diagnostics available for the COIM only. p
ESC RD
Initiates print-out of diagnostic system status. Includes a poll of other system COIMs for their diagnostic status. p
ESC SD
This escape sequence is a toggle print-out function it temporarily stops and restarts the print-out of diagnostic system status at the printer resident to this COIM. If the ESC SD function is used to temporarily halt the printing of diagnostic data, be sure to restart the print-out or use the ESC ZX function to end the system dump. Otherwise output to the external device is suspended indefinitely. p
ESC ZX
Discontinues the diagnostic print-out either in progress or temporarily this COIM. p

ESC RT
halted at
Initiates/continues print-out of diagnostic system status, only printing out tone continuity test status for the resident COIM. This is helpful if a large system is being tested and a lengthy print-out including tone information from all COIMs is not needed. p
ESC RR
Resumes the printing of tone continuity test status for COIMs yet to be prompted for their diagnostic data. This escape sequence is to be used after ESC RT to resume printing tone continuity status. p
ESC RUxx
Where xx is the hexadecimal slot address of a COIM. This escape sequence prints diagnostic information gathered only from the COIM residing at slot xx. The resident COIM slot number is used if diagnostic information is desired only from the resident COIM.
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ESC RPxx
Where xx is the hexadecimal slot address of a COIM. This escape sequence causes diagnostic system status from every COIM in the system to be printed out on the terminal/printer which is connected to the COIM residing at slot address xx.
Other diagnostics
The following diagnostics are also available to display various system information. Listed after each command are the boards it is applicable to. p
ESC Al
Displays TIMIs TDM address and repeater/call related information. Boards available: TIMI p
ESC Al< >
Displays audio related information. Enter one of the following options: <o> = options <CR> (default): Print only TDM slots with audio activity. 'C': Print only TDM slots assigned to channels at this COIM. 'F': Print ALL TDM slots known by this COIM. Boards available: COIM p
ESC AS
Displays AIMI System Fault Maintenance information. See Other system status and error messages on page 5-26. Boards available: COIM p
ESC BRxxxx
Change the printer/terminal baud rate stored in the personality PROM. It is changed by entering ESC BRxxxx from the diagnostic printer/terminal, Where xxxx is the desired 4-digit (use leading zero) baud rate. After entering ESC BRxxxx, change the diagnostic printer/terminal to the new baud rate. The last digit entered is not displayed as it is sent to the diagnostic printer/terminal at the new baud rate.
NOTE This routine does not change the baud rate of the modem. If a modem is used with the diagnostic printer/ terminal it must be changed manually after the baud rate is changed on the diagnostic printer/ terminal. To switch from 300 baud to 1200 baud on a 212A modem, press the HS switch, then toggle power to the modem.
Boards available: AIMI, CIMI, COIM, LOMI, TIMI
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ESC CS
Displays CIMI System Fault Maintenance information. See Other system status and error messages on page 5-26. Boards available: COIM p
ESC CK
Displays <circuit type (hex)> <TDM slot (hex)> <CEB ID (dec)> <AEB ID (dec)> for the current board. Possible values for circuit type: 06 = COIM 07 = TIMI 08 = LOMI OA = CIMI OC = AIMI Boards available: AIMI, CIMI, COIM,LOMI, TIMI p
ESC DA
Displays assignment data for this COIM. Boards available: COIM p

ESC DL
Enables data Logger display. To change to a fault maintenance display use ESC FM. See Printing call data in selective signaling systems on page 5-65. Boards available: COIM p
ESC DL
Enable/Disable TIMI activity Logging. Boards available: TIMI
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ESC DR
Displays the DEBUG RAM information for this board. This information includes: Console Freeze Information Console Reset Information Timing Message Information Heap Status (Ram usage) Information Last Tasks running before a reset occurred Claims to the Microphone In a stable system, if errors are displayed this could indicate a software problem. Save the data and contact System Support Center for further information. The information is cleared with ESC ID. Boards available: AIMI, CIMI, COIM, LOMI, TIMI p
ESC FM
Enables fault maintenance display. To change to a data Logger display use ESC DL. See Printing call data in selective signaling systems on page 5-65. Boards available: COIM p
ESC HP
Displays the current amount of heap (RAM) in use. Boards available: AIMI, CIMI, COIM, LOMI, TIMI p
ESC ID
Clears DEBUG RAM information for this board. See ESC DR. Boards available: AIMI, CIMI, COIM, LOMI, TIMI p
ESC LA
Displays ASTRO TBIM ACIM Link status information. See Other system status and error messages on page 5-26. Boards available: COIM p
ESC LMx
Enables/Disables the CIMI/CAD Link monitor display. x = O to disable x = l to enable When the display is enabled a message will print on the external device when the CIMI/CAD Link goes up or down. Boards available: CIMI
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ESC PT
Displays AIMI internal diagnostic link test results. Boards available: AIMI p
ESC RF
Displays the COIM RF crossmute table. Boards available: COIM p

ESC TR
Displays Trunking System Fault Maintenance information. See Other system status and error messages on page 5-26. Boards available: COIM
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Printing call data in selective signaling systems

Systems with signaling capability also have the ability to record and print call data. This section describes how to configure the system to print the call data and describes how to interpret the call data. For this functionality an external printer or readout device is connected to a COIM. For information on connecting the external printer or readout device, refer to Error messages on page 5-13. For information on programming the COIMs to print call data refer to the CENTRACOM Gold Series Console Database Manager Users Guide (68-81094E45).
Printer capacity and data rate

The information is printed out for each received or transmitted call and can be routed and printed on one printer, or it can be split among multiple printers, depending on system requirements. Each COIM printer port has a buffer that can handle 200 calls. Once this buffer is filled, the oldest calls are lost. Therefore, if the system is busy enough to consistently exceed the parameters listed below, it should be partitioned among two or more printers. p p p At 300 baud, an average of 20 messages per minute can be handled. At 1200 baud, an average of 75 messages can be handled. At 9600 baud, an average of 600 messages per minute can be handled.
Printer segmentation can be done by channel. Assume that there is a two operator position, six-channel MDC-1200 signaling system. At system setup, the system could be segmented to print out as follows: p p One printer logs all calls One printer logs all calls for channels 1 and 2, while a second printer logs all calls for channels 3 through 6.
Printer baud rate

The COIM defaults to 300 baud. The baud rate can be changed using the ESC BR sequence. Refer to Running diagnostics from an external printer or readout device on page 5-60.
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Converting from Fault Maintenance to Data Logger
NOTE The data logger continues logging messages while it is printing fault maintenance data. The stored data will be printed when the data logger is re-enabled.
The printer is initially a data logger or fault maintenance terminal based on whether the COIM has been programmed to log data. If the COIM has been assigned channels to log, the COIM initializes as a data logger. If not, the COIM initializes as a fault maintenance terminal. p p To change the external printer or readout device from fault maintenance to data logger, enter ESC DL. To change from a data logger to a fault maintenance terminal, enter ESC FM.
Data Logger Example and Description

p p p p p p Each line of information printed on the Data Logger is followed by a carriage return and a line feed. The maximum line length, including carriage return and Line Feed, is 82 characters. Sixty-six lines per page are printed. The carriage return and line feed from the last line on a page will advance to the next page. When the printer cable is first plugged in, a form feed command is issued to start the printout at the top of a new page. At the top of the first page of data logger information, header information is printed that shows the COIM firmware version,the MID code and TDM slot address of the COIM, and the BID code and TDM slot address of all channels logged by this COIM. An example of the header information is shown below.
CENTRACOM Gold Series System Data Logger Copyrighted by Motorola, Inc. 1994 ver214.tomi.exp.92.12.02 MID Code 00; AEB_ID, CEB_ID, TDM Slot Address. :01 01 05 Channels Logged: AEB 01 CEB 01 BID 01 TDM 01 AEB 02 CEB 03 BID 02 * * * AEB 06 CEB 02 BID 07 TDM 03Code B01; TDM Slot Address 02 TDM 02
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Following the general system information, the Data Column Header is printed and repeated at the top of each subsequent page. An example of the data logging information, including the Data Column Header, is shown below.
1 | CALL TYPE PTT_ID CALL ALERT SELECT CALL USER STS USER MSG VEH STS EMRG ALARM RADIO CHK STS REQ CALL ALERT SELECT CALL | 01 01 01 01 01 01 01 01 01 01 01 2 | AEB CEB 01 01 01 01 01 01 01 01 01 01 01 3 | BID B03 B01 B03 B03 B01 B03 B02 B01 B01 B02 B01 4 | SYS S00 S00 S00 S00 S00 S00 S00 S00 S00 S00 S00 5 | FMT 6 | DIR 7 | CALLER 0010077 0013023 0042175 0012075 0012144 0062067 0061023 0078001 0078001 0078001 0078001 TGID 0000 0000 0000 0000 0000 0000 0002 0000 0000 0001 0002 CALLEE 0078001 0078012 0078021 0078021 0078021 0078021 0078001 0012075 0012144 0061023 0062067 INFO 00 00 00 07 05 03 00 00 00 00 00 RAC 00 00 00 00 00 00 00 00 00 00 00 DATE 930122 930122 930122 930112 930112 930112 930112 930112 930112 930112 930112 TIME 00:05:39<NL><CR> 00:06:56<NL><CR> 00:07:29<NL><CR> 00:11:22<NL><CR> 00:12:17<NL><CR> 00:12:49<NL><CR> 00:13:49<NL><CR> 00:04:03<NL><CR> 00:04:22<NL><CR> 00:04:59<NL><CR> 00:05:17<NL><CR> 8
12345678901234567890123456789012345678901234567890123456789012345678901234567890
MDC IN MDC IN MDC IN MDC IN MDC IN MDC IN AST IN MDC OUT MDC OUT AST OUT MDC OUT
Other messages that may appear are listed below.

NO SYSTEM ACTIVITY
One hour has elapsed with no calls. This message appears to show that the printer is still working. This message appears if the printer buffers capacity of 200 calls has been exceeded. The oldest messages will be lost. Prints if the modem receives a valid data message that it does not recognize. Prints if the modem receives a valid data message that it cannot decode due to a problem with its EEPROM data.
WARNING: DATA MESSAGES LOST
WARNING: UNRECOGNIZED DATA MESSAGE
p p
WARNING: MODEM EEPROM ERROR
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Replacing boards
Replacing boards
Removing a board
To remove a circuit board from the CEB, simply pull the board straight out to disengage it from the backplane card edge connector. Never pull two modules from the card cage within a 30 second period of time. If an active module is pulled from the card cage an OOPS message is sent to the console operator. The Fault Maintenance system activates an alternate module (if applicable) within 20 seconds.
Addressing and jumpering a board

When installing a replacement board in the CEB, refer to its chapter in this manual and verify that its DIP switch settings and jumper configurations are exactly the same as on the board being replaced. If not, make the necessary corrections. When replacing a COIM, remove the personality PROM (code plug-U44) from the old board and place it in the new one.
Inserting a board
To install the replacement board, place the edges of the board in the card cage guides and gently push until the board is seated in the backplane card cage edge connector.
NOTE To prevent degrading system rf interference specifications, DO NOT insert the System Timer Module into card cage slot 6. Slot 6 is just to the right of the metal center brace.
Make sure that the DIP switch, Berg jumpers, and all resistor jumpers are set exactly in the new module as they were in the old one. Refer to the appropriate chapters for details. Make sure that the correct PROMs are in the new module. If necessary, place the PROMs from the defective module in the new module. Never attempt to insert a BIM or DR into slots 5 or 6 of the card cage. These slots are keyed to accept COIMs only. System Timer Modules can be placed in slot 5.
p p
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6 6 Hybrid
Troubleshooting
About this chapter

This chapter provides information on troubleshooting all hybrid circuits in the CEB. They are located in the BIM and the DR. Troubleshooting for the bus driver circuits that drive the digital pulses throughout the system is also included.
Hybrids covered
The following Hybrids are covered in this chapter:
Module
BIM DR Bus Driver hybrids
Hybrid
Z1 through Z3 Z1 through Z6 Throughout the system

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Chapter 6
Hybrid Troubleshooting
Introduction
Introduction
Within the CENTRACOM Gold Series system, there are a number of signal processing functions common to several modules. These functions are incorporated into hybrid circuit units which are placed throughout the system. Procedures are provided in this section to isolate malfunctioning hybrids. Faulty hybrids are non-repairable and must be replaced. The following hybrids are covered in this section: p p p p p Digital Level Memory Hybrids Low Pass Filter Hybrid Notch Filter Hybrid Line Driver Hybrid Bus Driver Hybrids
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Chapter 6

Table 6-1 lists test equipment recommended for use in the fault isolation procedures.
Table 6-1

Test Equipment Recommended Model
Motorola R-1029 Motorola 1053 Hewlett-Packard 3312
20 MHz Dual Trace Oscilloscope AC Voltmeter Function Generator
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Digital Level Memory description
Digital Level Memory description

In the CENTRACOM Gold Series system, transmit and receive audio is digitized, encoded into a Pulse Code Modulation (PCM) format, placed on a Time Division Multiplexed (TDM) bus and passed through the system. The audio signal is then converted back into analog form before it is either routed to the console speakers, or placed on the telephone lines to be sent to the base station. Prior to the A/D conversion, however, the analog signal is passed through a signal conditioning circuit called Digital Level Memory (DLM). The DLM circuits in the CEB are located on the Base Interface Module (BIM), the Dual Receive Interface Module (DR), and the Radio Control Board (RCB). The DLM circuits are virtually identical on all of these modules, differing only in the level at which the signal is received and the gain or attenuation provided. One purpose of the DLM circuitry is to eliminate the need for a level setting potentiometer in the audio path. The gain provided by the DLM is determined by the magnitude of the audio signal being processed. During a voice transmission, the DLM gain constantly adjusts to the incoming signal level. During a pause in the voice transmission, the DLM senses the absence of voice and holds the gain at the level of the last voice signal. When the voice transmission resumes, the gain once again responds to the magnitude of the incoming signal. In this manner, noise present during pauses is not amplified as it would be in a conventional AGC circuit. The DLM circuit consists primarily of three hybrids which are supported by a number of discrete on-board components. The diagrams detailing the location and value of the components comprising the DLM on the RCB, DR, and BIM modules are located in the appropriate sections. A listing of the hybrids found on each module and the corresponding troubleshooting tables in this section are given in the next paragraphs. These troubleshooting charts are to be used with the diagrams for the hybrid in questions.
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Hybrid troubleshooting procedures

Hybrids are non-repairable due to the fabrication methods used in their manufacture. Troubleshooting procedures are provided in this section to isolate a faulty hybrid. If a hybrid is malfunctioning, it must be replaced. Do not attempt to replace or repair any part or component located on the hybrid.
Base Interface Module hybrids

This section provides troubleshooting procedures for the following hybrids located on the BIM: p DLM Hybrids: m DLM Gain Hybrid m DLM Comparator Hybrid m DLM R-2R Hybrid p p Low Pass Filter Hybrid Line Driver Hybrid
DLM Hybrids
Refer to table 6-2. This procedure covers DLM Gain Hybrid (Z2), DLM Comparator Hybrid (Z3), and DLM R-2R Hybrid (Z1). Refer to Base Interface Module chapter (68P81090E19).
Table 6-2
Test procedure for DLM hybrids Base Interface Module Input Wave
1 kHz Sinewave at -10 dBm
Hybrid Under Test

Z2-DLM Gain Hybrids Step 1
Input Points
Card Edge Pins 57-58 Card Edge Pins 59-60
Output Wave
1 kHz Sinewave at 0 dBm (2.25 V p-p) at -180. 1 kHz Sinewave at -18 dBm (275 mV p-p) at -180. 1 kHz Sinewave at 2.1 dBm (2.8 V p-p) at -180.
Output Points
Pin 11 of Z2 Same
Comments
If correct waveform is present, proceed to test procedure for Z3. If the output is not correct, check supply voltages. If still wrong, proceed to Step 2.
Z2-Step 2
Same
Same Same
Pin 1 of U206 Pin 7 of U206
If correct waveform is present, proceed to Step 3. If incorrect, check associated components. If the output of Z2 is still incorrect, proceed to Step 3.
Z2-Step 3
Same
Same Same
Pin 1 of Z2 Same
If this is correct, check positive side of C217, expecting 1 volt dc. If this voltage is present, check the associated components. If the problem persists, replace Hybrid Z2 and verify its correct components.
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Table 6-2
Test procedure for DLM hybrids Base Interface Module Input Wave
Same
Hybrid Under Test

Z3 DLM Comparator Hybrid Step 1
Input Points
Same Same
Output Wave
1 kHz Sinewave at 2.1 dBm (2.8 V p-p) at -180. 0V
Output Points
Pin 12 of Z3 Same
Comments
If the correct waveform is present, proceed to Step 2. If incorrect, refer back to Step 1 of Hybrid Z2 test procedure.
Z3-Step 2
Same Same 1 kHz Sinewave at -35 dBm (39 mV p-p) Same Same
Pin 20 of Z3 Same
12 V dc
Pin 20 of Z3 Same
If the correct dc voltage is not present, check pin 16 which is normally at 6.5 V dc. If problem persists, replace Hybrid Z5 and/or Z6 and verify correct operation. If voltage is correct, proceed to Step 3. If the squarewave is present, increase input frequency to 2 kHz and verify that the output frequency follows that of the input. If incorrect waveform, check supply voltages. If still incorrect, check output clock at pin 4 (16 Hz). If correct, proceed to Step 4. If incorrect, check clock frequency (16 Hz). If problem persists, replace Hybrid and verify correct operation. If correct, check collector of transistor Q207. With no input, this point should be at 5 V. If the output at Z3, pin 10 is correct but the 5 volts is not present at Q207, check U203-205 and associated components. If incorrect, check supply voltages (pins 2, 5, 11, 13 = 12). Regardless of output, proceed to Step 2.
Z3-Step 3
1 kHz Sinewave at -10 dBm (695 mV p-p)
Same Same
1 kHz Square wave at 12 V.
Pin 10 of Z3
Z3-Step 4
No Input
No Input No Input
Pin 10 of Z3
Z1-DLM R-2R Hybrid Step 1
1 kHz Sinewave at -10 dBm (695 mV p-p) No Input
Card Edge Pins 57-58 Card Edge Pins 59-60 No Input Card Edge Pins 57-58 Card Edge Pins 59-60 No Input
12 V dc
Pin 4 Z1
0V 2.4 Vdc
Pin 4 Z1 Pin 13 of Z1
If incorrect, check U203 and U205. If correct, proceed to Step 3. Proceed
Z1-Step 2
4.5 Vdc
Pin 13 of Z1
If incorrect, replace Hybrid Z1.
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Low Pass Filter and Line Driver Hybrids

Refer to Table 6-3. This procedure covers the Low Pass Filter and Line Driver Hybrids on the BIM. Refer to diagrams in the BIM chapter (68P81090E19).
Table 6-3
LPF Procedure
Input Point
Card Edge Pin 98
Input Signal
2175 Hz Squarewave at 12 V Same
Output Signal
2175 Squarewave at 12 V 2175 Hz Sinewave at 0 dBm (2.2 V p-p)
Output Point
U9C-3 U31-4
Comments
Same
Pin 13 of LPF Hybrid
If correct waveform does not appear, check supply voltages and associated discrete components. If problem persists, replace the hybrid and verify correct operation. If correct waveform is present, proceed to Line Driver test procedure.
Dual Receive Module hybrids

Refer to Table 1-4. This section provides troubleshooting procedures for the DLM hybrids located on the Dual Receive (DR) Module. Refer to the diagram in the Dual Receive Interface Module chapter (68P81091E03).
Table 6-4
Test procedure for DLM hybrids Dual Receive Interface Module Input Wave
1 kHz Sinewave at -10 dBm
Hybrid Under Test

Z1 and Z2-DLM Gain Hybrids Step 1
Input Points
Card Edge Pins 57-58 Card Edge Pins 59-60 Same Same
Output Wave
1 kHz Sinewave at 0 dBm (2.25 V p-p). 1 kHz Sinewave at -18 dBm (275 mV p-p) 1 kHz Sinewave at 2.1 dBm (2.8 V p-p) at -180.
Output Points
Pin 11 of Z1 Pin 11 of Z2
Comments
If correct waveform is present, proceed to test procedure for Z5 and Z6. If the output is not correct, check supply voltages. If still wrong, proceed to Step 2. If correct waveform is present, proceed to Step 3. If incorrect, check associated components. If the output of Z2 is still incorrect, proceed to Step 3. If this is correct, check positive side of C107 (for ZI) and C207 (Z2), expecting 1 volt dc. If this voltage is incorrect, check the associated components. If the problem persists, check the supply voltages. If these are correct, replace Hybrid Z1 and/or Z2 and verify correct operation. If the correct waveform is present, proceed to Step 2. If incorrect, refer back to -Step 1 of Hybrid Z1/Z2 test procedure.
Z1/Z2-Step 2
Same
Drain of FET Q103 Drain of FET Q203 Pin 1 of Z1 Pin 1 of Z2
Z1/Z2-Step 3
Same
Same Same
Z5 and Z6 DLM Comparator Hybrid Step 1
Same
Same Same
1 kHz Sinewave at 2.1 dBm (2.8 V p-p)
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Table 6-4
Test procedure for DLM hybrids Dual Receive Interface Module (continued) Input Wave
Same
Hybrid Under Test

Z3-Step 2
Input Points
Same Same
Output Wave
0V
Output Points
Pin 20 of Z3 Same
Comments
If the correct dc voltage is not present, check pin 16 which is normally at 6.5 V dc. If problem persists, replace Hybrid Z5 and/or Z6 and verify correct operation. If voltage is correct, proceed to Step 3.
1 kHz Sinewave at -35 dBm (39 mV p-p) Z3-Step 3 1 kHz Sinewave at -10 dBm (695 mV p-p)
Same Same
12 V dc
Same Same
If the squarewave is present, increase input frequency to 2 kHz and verify that the output frequency follows that of the input. If incorrect waveform, check supply voltages. If still incorrect, replace Z5 and Z6. If correct, proceed to Step 4. If incorrect, replace Hybrid Z5 and/or Z6 and verify correct operation. If correct, check collector of transistor Q102/Q202. With no input, this point should be at 5 V. If the output at Z5/Z6, pin 10 is correct but the 5 volts is not present at Q202/QIO2, check U203-5 and associated components. If incorrect, check supply voltages. Regardless of output, proceed to Step 2.
Z3-Step 4
No Input
No Input No Input
Z3/Z4 DLM R-2R Hybrid Step 1
Card Edge Pins 57-58 Card Edge Pins 59-60 No Input No Input
12 V dc
Pin 4 Z3
0V 0V 2.4 Vdc
Pin 4 Z3 Pin 4 Z4 Pin 13 of Z3 Pin 13 of Z4
If incorrect, check U27 and U29/U28 and U29. If correct, proceed to Step 3. If incorrect, replace Hybrid Z3 and/or Z4.
Z3/Z4-Step 2
Card Edge Pins 57-58 Card Edge Pins 59-60 No Input
4.5 Vdc
Bus driver hybrids

These hybrids, located throughout the system, serve to drive digital pulses between various data nodes. Each driver is configured as an emitter follower. To verify the correct operation of these components, expect a diode voltage drop (approximately 0.7 volts) from the input to the output. Rather than supply an arbitrary voltage, check the voltage at the input and verify that the output is at the appropriate level. If the proper level is not present, replace the hybrid and verify correct operation. To initiate this test, first ground pin 1 of Latch U32. Ignore the effect this produces in the LEDS, Also, ground pin 5 of NAND gate U31 Line driver procedure. To initiate this test, leave the LPF test set up in place, verifying the presence of the prescribed waveform at pin 13 of LPF hybrid. Perform the following steps:
1.
Ground Pin 5 of inverter U12.
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Chapter 6
2. 3. 4.
Attach scope or meter to Pin 3 of line driver hybrid. Adjust potentiometer R 113 until the signal at Pin 3 is at -10 dBm (695 mV p-p). When this waveform is present at the correct level, connect a 600 ohm load across card edge pins 57 and 58. The output across this load should be a sinewave at 1.5 dBm (2.4 V p-p). If the correct output is not present, check supply voltages and associated discrete components. If problems persist, replace the line driver hybrid and verify correct operation.
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7 7 CEB Card Cage
Interconnect Board
About this chapter

Section
Introduction Description Extender boards BLN1141A Main Extender Board Parts List BLN1142A Option Extender Board Parts List BLN6648A Backplane Parts List
Page
7-116 7-119 7-127 7-31 7-32 7-33
Models covered
The following CEB card cage interconnect board models are covered in this chapter:
Model
BHN1006A BLN6648A BLN6652A BLN6653A CEB card cage Interconnect board Main extender board Option extender board
Description

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Chapter 7
CEB Card Cage Interconnect Board
Introduction
Introduction
The CEB (Central Electronics Bank) interconnect board can host up to 10 CEB modules (interface boards) and 10 option boards installed in the CEB card cage. The interconnect board provides power and signal busing to all modules plugged into it. Connection to telephone lines are also provided through card edge connections. Usually the term interconnect board infers that all positions are wired in parallel and are virtually identical. This is not true of the CENTRACOM Gold Series interconnect board. The positions on this board have been divided into two groups: p p Boards interfacing with external lines and equipment Boards interfacing with operator positions
The center two positions, (card slots 5 and 6), interface to the operator positions, while the outer board slots, (1-4 and 7-10), interface with external equipment and phone lines. The board slots are numbered one through 10 (from left to right), looking at the component side of the interconnect board with the power connector at the bottom. It is not required that all slots be filled with a board. A card cage is filled as needed. If required, additional card cages can be added by daisy-chaining from daisy-chain card edge ports supplied on each interconnect board (see Figure 7-1). This chapter also describes the two extender boards used when troubleshooting or testing boards installed in the card cage.
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CEB Card Cage Interconnect Board Introduction
STATION CABLES FOR OPTIONS OPERATOR POSITION A CABLE BASE STATION CABLE OPERATOR P4 POSITION B CABLE P2 P5
P1
P3
MULTIPLE CARD CAGE DAISY CHAIN CABLE CONNECTIONS P8 (TOP) AND P7 (BOTTOM) OPTION BOARDS (RS-232, AUX1, AUX2)
POWER CONNECTION P6 (NOT SHOWN)
4 OTHERS (BIM, DR, SYS TIMER OR AUDIO EXPANSION INTERFACE) 2 OPERATOR INTERFACE MODULES CEB CARD CAGE
CEB MODULES (INTERFACE BOARDS)
4 OTHERS (BIM, DR, SYS TIMER OR AUDIO EXPANSION INTERFACE)
CEN140 021496JNM
Figure 7-1
Typical card cage mounting
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Chapter 7
Description
Description
Power distribution
Power for the interconnect board is connected via a six conductor cable to a power distribution manifold. The connector carries the following signals at its six pins: p p p p p p Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 + 9V DC 9 V GND +15 V DC 15 V GND 60 HZ CLK PF (POWER FAIL DETECT)
The numbering of the connector is from left to right when viewed from the component side. Refer to the schematic diagram for more detail.
Interconnect board compatibility

Table 7-1 shows the types of CEB modules intended for use in the card cage.
Table 7-1
CEB modules
Definition
The system timer may reside in any slot as it has no external I/O. The preferred placement of an OMI/COIM module is in the center two card slots. In these positions, the cable interfacing the OMI/COIM module to its respective operator position terminates on a TELCO connector, which is hard wired to one of these two center slots. If the OMI/COIM is used in any of the other slots, a special option board must be used directly above the OMI/COIM to provide the TELCO connector interface. The BIM and DR modules may occupy any position in the card cage EXCEPT the center two. Positions 1- 4 and 7- 10 route audio and logging recorder lines over dedicated connections on the interconnect board to the main phone line TELCO connector (P2). The center two slots do not have this interface, since they have dedicated connections for an operator position interface. The preferred placement for an AEI is in slots 1-4 or 7-10. An AEI module is usually present only when an OMI is also present in the card cage. Up to two AEIs may accompany each OMI module. AEls are placed in slots 1-4 to accompany an OMI in slot 5, and placed in slots 7-10 to accompany an OMI in slot 6.
Module
SYSTEM TIMER OMI/COIM
BIM & DR
AEI
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CEB Card Cage Interconnect Board Description
Card edge pin definitions

Each of the ten card slots uses a 100-pin card edge connector. The card cage is configured to allow both a module and an option board to plug into the same card edge connector simultaneously. The card cage provides the correct alignment to ensure that both boards enter the card edge connection correctly. In the pin descriptions (refer to Table 7-2), three signal names are given for a signal pin in several cases. The name of a signal depends on the module placed in the slot. Therefore, signal names are given in case an COIM, BIM or DR occupies a given slot. If another type of board occupies a slot, these signal names may be disregarded.
Console interface terminations

There are two possible console interface TELCO terminations on the CEB interconnect board: p p P4 interfaces with the OMI/COIM in card slot 5 P5 interfaces with the OMI/COIM in card slot 6
Each of the two slots routes 14 signals to its TELCO connector. These signals and their corresponding point of origin on the plug-in module are listed in Table 7-3.
Phone line terminations

Six lines are routed from slots 1-4 and 7-10 to TELCO connector P2 on the CEB interconnect board. This connector is cabled directly to the punch block, which interfaces with the commercial telephone system. Signal origins and destinations are given in Table 7-4 for a representative BIM module. For a DR module, the CHANNEL 1 lines are the same as 2-WIRE and the CHANNEL 2 lines are the same as 4-WIRE. The numbers in parentheses indicate the pin numbers on the CEB interconnect board where the signal originates. Two numbers are given for each signal as each signal is (the signal is actually on two separate pins) connected to the option board area and to the interface board area of each slot.
Option I/O terminations

Slots 1-4 and 7-10 also route options I/O signals to one of the two option TELCO connectors on the CEB interconnect board. Slots 1-4 route a total of 48 option signals to options TELCO P1 on the CEB interconnect board. Slots 7-10 route a total of 48 option signals to options TELCO P3 on the CEB interconnect board. The six single pairs that originate in each slot, are actually taken from the option boards which plug in over the plug-in modules. The unused pins (pins 25,26) are tied to option buses 1 and 2, respectively. Option buses are generic buses running only in the option area. Option buses are routed to all 10 of the option boards on the CEB interconnect board and are connected to P2-38 and P2-13. Table 7-5 contains the pin definitions of the 12
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Chapter 7
Description
option I/O signals that interface with each option board. The number in parentheses is the pin number on the CEB interconnect board where a given signal originates.
Table 7-2
Card edge pin definitions
Option boards Pin # 1 3 5 7 9 11 13 OMI 15 17 CONS SRCE DATA+ OMI SOURCE AUX I/O 3 DATA+ MONITOR AUDIO 1 MONITOR AUDIO 2 UNSELECT AUDIO Solder side signal OPTIONS I/O 1 OPTIONS I/O 3 OPTIONS I/O 5 OPTIONS I/O 7 OPTIONS I/O 9 OPTIONS I/O 11 15 V DC BIM AUX I/O 5 D/R AUX IN 5 OMI CONS SRCE DATAAUX I/O 4 DATA MONITOR AUDIO 1 MONITOR AUDIO 2 UNSELECT AUDIO Component side signal OPTIONS I/O 2 OPTIONS I/O 4 OPTIONS I/O 6 OPTIONS I/O 8 OPTIONS I/O 10 OPTIONS I/O 12 15 V DC BIM Aux I/O 6 D/R AUX IN 6 16 Pin # 2 4 6 8 10 12 14
AUX IN 3 AUX I/O 1 LOGGING RECORDER AUX MUTE OPTIONS BUS 1 LOGIC GROUND
OMI source AUX IN 1
AUX IN 4 AUX I/O 2 LOGGING RECORDER AUX AUDIO OPTIONS BUS 2 LOGIC GROUND AUX IN 2
18 20 22 24 26 28 CHANNEL 2 CHANNEL 1 30 32 34 36
19 21 23 25 27 29 31 33 35
SELECT AUDIO TRANSMIT AUDIO
4 WIRE 2 WIRE RS232 RECEIVE DATA NO CONNECT
CHANNEL 2 CHANNEL 1
SELECT AUDIO TRANSMIT AUDIO
4 WIRE 2 WIRE
RS232 TRANSMIT DATA RS232 DATA TERMINAL READY
Interface boards (CEB modules) Pin # 45 47 49 51 53 55 OMI Solder side signal AUXILIARY BUS 1 AUXILIARY BUS 3 AUXILIARY BUS 5 AUXILIARY BUS 7 AUXILIARY BUS 9 RS232 RECIEVE DATA BIM D/R OMI Component side signal AUXILIARY BUS 2 AUXILIARY BUS 4 AUXILIARY BUS 6 AUXILIARY BUS 8 RS232 DATA TERMINAL READY RS232 TRANSMIT DATA BIM D/R Pin # 46 48 50 52 54 56
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Table 7-2
57 59 61 63 65 67
Card edge pin definitions (continued)

TRANSMIT AUDIO SELECT AUDIO UNSELECT AUDIO MONITOR AUDIO 2 MONITOR AUDIO 1 OMI SOURCE AUX I/O 3 DATA+ CONS SRCE DATA+ 2 WIRE 4 WIRE AUX MUTE LOGGING RECORDER AUX I/O 1 CHANNEL 1 CHANNEL 2 UNSELECT MONITOR AUX IN 1 TRANSMIT AUDIO SELECT AUDIO AUX AUDIO AUDIO LOGGING AUDIO 2 MONITOR AUDIO 1 AUX I/O 4 DATACONS SRCE DATA RECORDER AUX I/O 2 AUX IN 2 2 WIRE 4 WIRE CHANNEL 1 CHANNEL 2 58 60 62 64 66 68 AUX IN 3 AUX I/O 5 SPARE BUS 1 MUX BUS 1 +15.0 V MUX BUS 2 STATIC GROUND MUX BUS 3 +9.0 V CLOCK SPARE BUS 3 AUDIO/LOGIC GROUND A3 ADDRESS CODE DATA READY A/B VOTE DATA CLOCK 10 HZ CLOCK OMI SOURCE AUX IN 5 AUX IN 4 AUX I/O 6 SPARE BUS 2 BUSY BUS 1 +15.0 V BUSY BUS 2 STATIC GROUND BUSY BUS 3 +9.0 V DATA POWER FAIL AUDIO/LOGIC GROUND A4 ADDRESS DECODE DATA BUSY A/B STATUS GUARD TONE 60 HZ SYNC AUX IN 6 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
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Description
Table 7-3
Slot 5 signals CONSOLE SOURCE DATA + CONSOLE SOURCE DATA OMI SOURCE DATA + OMI SOURCE DATA UNSELECT AUDIO UNSELECT AUDIO TRANSMIT AUDIO TRANSMIT AUDIO MONITOR AUDIO 1 MONITOR AUDIO 1 MONITOR AUDIO 2 MONITOR AUDIO 2 Pin (69) (70) (67) (68) (61) (62) (57) (58) (65) (66) (63) (64)
Console interface terminations

P4 8 1 9 2 12 5 14 7 10 3 11 4 Slot 6 signals CONSOLE SOURCE DATA + CONSOLE SOURCE DATA OMI SOURCE DATA + OMI SOURCE DATA UNSELECT AUDIO UNSELECT AUDIO SELECT AUDIO SELECT AUDIO TRANSMIT AUDIO TRANSMIT AUDIO MONITOR AUDIO 1 MONITOR AUDIO 1 MONITOR AUDIO 2 MONITOR AUDIO 2 Pin (69) (70) (67) (68) (61) (62) (59) (60) (57) (58) (65) (66) (63) (64) P5 8 1 9 2 12 5 13 6 14 7 10 3 11 4
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Table 7-4
Slot 1 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 2 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 3 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 4 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64)
Phone line terminations

P2 23 48 24 49 50 25 P2 20 45 21 46 47 22 P2 17 42 18 43 44 19 P2 14 39 15 40 41 16 Slot 7 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 8 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 9 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Slot 10 function 2 WIRE 2 WIRE 4 WIRE 4 WIRE LOGGING RECORDER LOGGING RECORDER Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) Pins (31,57) (32,58) (29,59) (30,60) (21,63) (22,64) P2 12 37 11 36 35 10 P2 9 34 8 33 32 7 P2 6 31 5 30 29 4 P2 3 28 2 27 26 1
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Table 7-5
Slot 1 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 Slot 2 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I//O 8 OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 Slot 3 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS 1I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10)
Option I/O terminations

P1 24 49 23 48 22 47 21 46 20 45 19 44 P1 13 38 14 39 15 40 16 41 17 42 18 43 P1 7 32 8 33 9 34 10 35 11 36 Slot 7 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 Slot 8 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I//O OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 Slot 9 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) P3 24 49 23 48 22 47 21 46 20 45 19 44 P3 13 38 14 39 15 40 16 41 17 42 18 43 P3 7 32 8 33 9 34 10 35 11 36
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Table 7-5
OPTIONS I/O 1 OPTIONS I/O 12 Slot 4 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12)
Option I/O terminations (continued)

12 37 P1 1 26 2 27 3 28 4 29 5 30 6 31 OPTIONS I/O 11 OPTIONS I/O 12 Slot 10 options signals OPTIONS I/O 1 OPTIONS I/O 2 OPTIONS I/O 3 OPTIONS I/O 4 OPTIONS I/O 5 OPTIONS I/O 6 OPTIONS I/O 7 OPTIONS I/O 8 OPTIONS I/O 9 OPTIONS I/O 10 OPTIONS I/O 11 OPTIONS I/O 12 (11) (12) Pin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) 12 37 P3 1 26 2 27 3 28 4 29 5 30 6 31
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Chapter 7
Extender boards
Extender boards
Main extender board
The main extender board (BLN6652A)provides a means of testing a CEB board by extending it out of the card cage. The board to be tested is removed from the card cage. The extender board is inserted into the card cage in place of the board to be tested. The questionable board is then plugged into the extender board. A test point is accessible for each of the card cage signals, and for 9 V, 15 V and ground. The signal names are screened on the extender board next to each of the test points. Forty of these signals are routed through DIP switches on the main extender board so that the board under test can be isolated from any combination of system buses if necessary. If the signal routes to a DIP switch, the DIP switch number is screened in parentheses next to the signal name. When the DIP switch is in the ON position, the switch is closed and the bus signal can reach the board under test. When the switch is in the OFF position, the bus signal is isolated from the system.
Option extender board

The option extender board (BLN6653A) is used for testing option boards in the CEB. With the exception of the DIP switches, it is used in the same manner as the main extender board. The option extender board contains test points for 2-wire and 4-wire audio monitoring when installed above a base interface module.
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Chapter 7
CEB Card Cage Interconnect Board BLN6648A Overlay
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Chapter 7
CEB Card Cage Interconnect Board BLN6648A Schematic
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CENTRACOM Gold Series Central Electronics Bank Maintenace Manual
Chapter 7 - CEB Card Cage Interconnect Board BLN1141A Main Extender Board Parts List
BLN1141A Main Extender Board Parts List

Reference Part Number Description Reference Part Number Description
Consisting of BLN6646A:
non-referenced items:
0210971A16 0310907A19 0400007683 0784847N01 0784847N02 4682069K02 5484497M87 5584647M02 NUT, HEX: 3 X 0.5MM (4 USED) SCREW, MACHINE: M3X0.5X8 (4 USED) WASHER, LOCK: NO. 4, INTERNAL TOOTH (4 USED) BRKT EXT CARD BRKT EXT CARD GUIDE CARD (2 USED) LABEL, ID: 7/8 X 1/4" (2 USED) HNDL EXT CARD
and BLN6652A:
switch:
S1 thru 4 4083849F05 SWITCH ROCKER DIP 10 POSTN
0210971A16 0310907A19 0400007683 0784847N01 0784847N02 0982060P04 2884957N01 2884957N03 4682069K02 5484497M29 5484497M87 NUTMCH M3X0.5 HEX STLCAD (4 USED) SCRMCH M3X0.5X8 INTSTARPAN STL (4 USED) WSHRLCK 4 INT STL CAD (4 USED) BRKT EXT CARD BRKT EXT CARD RECP CKT BD EDGE 60 CONT PLUG CKT BD 4 PIN PLUG CKT BD 14 PIN (4 USED) GUIDE CARD (2 USED) LBL ADH1/2X11/32 BK YL (1) LABEL ID 7/8 X 1/4 (2 USED)
6 8P 81 0 9 5 E5 0 -A 1 /1 8 / 0 1
7-21
Chapter 8 Base Interface Module BLN1142A Option Extender Board Parts List
BLN1142A Option Extender Board Parts List

Reference Part Number Description Reference Part Number Description
Consisting of BLN6647A:
0210971A16 0310907A19 0400007683 0784848N01 0784848N02 4682069K02 5484497M87 5584849N01 NUT, HEX: 3 X 0.5MM (4 USED) SCREW, MACHINE: M3X0.5X8 (4 USED) WASHER, LOCK: NO. 4, INTERNAL TOOTH (4 USED) BRKT OPTION EXT CARD BRKT OPTION EXT CARD GUIDE CARD (2 USED) LABEL, ID: 7/8 X 1/4" (2 USED) HNDL OPTION EXT CARD
and BLN6653A:
0982060P05 2884957N01 5484497M29 RECP CKT BD EDGE 44 CONT PLUG CKT BD 4 PIN LABEL: 1/2X11/32", BLACK-YELLOW (1)
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Chapter 7 - CEB Card Cage Interconnect Board BLN6648A Backplane Parts List
BLN6648A Backplane Parts List

Part Number Part Number
Reference
Description
Reference
Description
capacitor, fixed:
C1 THRU 4 C5 C5 C6 THRU 8 0884637L50 0884637L22 2182372C01 0884637L22 2700 PF, 10%; 630V 0.22 UF, 10%; 100V 0.1 UF, +80%/-20%; 25V 0.22 UF, 10%; 100V P1 THRU 3 P4,5 P6 0984009P02 0984009P05 2883315P01
connector:
RECEPTACLE: 50-CONTACT RECEPTACLE: 14-CONTACT PLUG PWR 6 PIN
non-referenced items: connector:

J1 thru 4 J5,6 J7 thru 10 0983406P02 0983406P01 0983406P02 RECP CKT BD EDGE 100 CONT RECP CKT BD EDGE 100 CONT RECP CKT BD EDGE 100 CONT 0210971A16 0310907A22 0400007683 4283552P01 NUT, HEX: 3 X 0.5MM (10 USED) SCREW, MACHINE: M3X0.5X16 (10 USED) WASHER, LOCK: NO. 4, INTERNAL TOOTH (10 USED) STRAP, CONNECTOR RETAINER (3 USED) LABEL, FCC LABEL: 1/2X11/32", BLACK-YELLOW (1)
jumper:
JU1 THRU 18 0611009B23 0 OHM, 5%; 1/4 W 5482184N01 5484497M29
inductor:
L1 THRU 4 L5 2483977B06 2412015A30 2-1/2 TURNS CHOKE RF AXIAL A/I 27.0UH
6 8P 81 0 9 5 E5 0 -A 1 /1 8 / 0 1
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Chapter 8 Base Interface Module BLN6648A Backplane Parts List
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8 8 Base Interface
Module
About this chapter

Section
Introduction Theory BLN6654D Parts List
Page
8-2 8-3 8-69
Models covered
The following models of the Base Interface Module (BIM) are covered in this chapter:
Model
BLN6654D
Description
Base Interface Module

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Chapter 8
Introduction
Introduction
The BIM interfaces a base station to multiple operator positions at the console site. The BIM performs the following functions:
p p p p
Receives analog audio from the base station, digitizes it, and routes it to all operator positions in the system Receives digital audio from any operator position, converts it to analog, and sends it to the base station Generates the proper tones or dc levels necessary to control the base station. Sends data to the operator positions to acknowledge commands and to report its status
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Chapter 8
Base Interface Module Theory
Theory
The BIM consists of the following circuits:
p p p p p p p p p p p p
Receive audio Transmit audio DLM audio processing Microprocessor system Microprocessor reset and watchdog timer Module address programming Receive/transmit data communications Auxiliary input/output Tone generation Guard tone gating and low pass filter hybrid three-state control Logging recorder output
Theory and troubleshooting charts for the DLM hybrid, the line driver, and the low pass filter hybrids are included in Chapter 6.
Receive audio
The BIM digitizes audio from the base station and places it in the proper slot on the Time Division Multiplexed (TDM) bus for routing to various parts of the system. This audio signal enters the BIM through card edge connector pins 57 and 58 if a 2-wire configuration is employed, and through pins 59 and 60 if a 4-wire system is used. Since the signal is analog, the BIM must convert it to the Pulse Code Modulation (PCM) format used in the TDM busing scheme. Before the analog receive audio is processed in the A/D circuitry, it is first routed into the Digital Level Memory (DLM) circuit block. This block provides special level conditioning to the analog signal. Similar circuit blocks are located on various modules throughout the CENTRACOM system. The DLM circuitry is discussed in the DLM Audio Processing paragraph. The analog audio output of the DLM (Receive Audio) is routed to the +TX input of the CODEC (U16-3), where it is converted into the PCM format. Aside from the A/D and D/ A converters, U16 also contains the anti-aliasing filters required to avoid degradation of the signal upon reconstruction. To ensure that the digitized audio is placed in the proper slot on the TDM bus, U16 is controlled by Time Slot Assigner (TSAC) U5. Eight bits of digital audio are clocked out of the TDD output of U16-11 when a logic high is received at the Transmit Data Enable pin, U16-10. This signal comes from U5 when the slot assigned to the BIM occurs on the
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TDM bus. The TSAC is itself programmed by microprocessor U1 to sense the correct slot as selected by DIP switch S2 on the BIM. To stay synchronized with the TDM bus, the TSAC uses the A4 signal. This 7.75 kHz signal is generated on the system timer module and bused throughout the system. 7.75 kHz is the period of one frame on the TDM bus. A falling edge on the A4 signal indicates the start of a new frame. The A4 signal enters the BIM at card edge connector pin 92 and is latched into U15A. On the rising edge of the CLK signal, A4 is clocked through U15A, allowing the complement A4 to appear at the Q output (pin 2). This signal is presented to the FSR and FST inputs of the TSAC (pins 10 and 9, respectively). The rising edge of CLK also sets U15B, resulting in a logic high at the Q output (U15B-13). This pulse is used as the clock signal for the CODEC and TSAC, entering those chips at the leads labeled RDC and TDC (pins 13 and 12 on the CODEC, pins 15 and 12 on the TSAC). Since the delays in U15A and U15B are essentially equal (approximately one clock cycle), the CLK and A4 signals arrive at the CODEC and TSAC at virtually the same time. When CLK goes low, the set condition on U15B is removed and the flip-flop is reset by a pullup on the reset lead. The result is that the Q output of U15B follows the CLK signal with a slight propagation delay through U15B. Whenever a rising edge occurs on the A4 line, the TSAC assumes that the next eight bits are the contents of slot 0 in the TDM frame. In reality, due to the manner in which the signal is generated on the system timer module, the A4 signal is two clock periods ahead of the data on the TDM bus. After the A4 signal is clocked through U15A, however, it is only one bit ahead of data on the TDM bus. At this point, the digital audio from the CODEC is one clock cycle ahead of the TDM bus. When the TSAC recognizes that the correct slot is present on the TDM bus, the TSAC TXE output (Transmit Enable, U5-14) goes high, allowing CODEC U16 to serially clock PCM-encoded audio out of its TDD output (U16-11). Since A4 is still one clock cycle behind the digital audio, that data is latched into U14 through the D4 input. The synchronized output is applied to three-state buffer U33A. On the next rising edge of CLK, a logic low is clocked to the D5 input of U14 (pin 15). This pulse enables U33D, allowing the output at Q4 (eight bits of digital audio) to be clocked onto the TDM slot that the module has been assigned to.
Transmit audio
In order to perform the transmit function, the BIM must be capable of accessing any slot on any one of the three TDM buses. It must then convert that data to an analog voltage and send it over phone lines to a base station. Unlike other modules in the system where the board is jumpered to receive one of the TDM buses, all three of these lines enter the BIM (card edge connector pins 73, 77 and 81). A transmission is initiated when microprocessor U1 receives a data packet from the operator position, instructing it to transmit the audio contained in a certain slot on one of the three TDM buses. In order to select the proper slot, the microprocessor writes to the TSAC, programming it to place a logic high on its RXE lead (pin 13) when the appropriate time slot occurs. This pulse is passed through latch U26, ultimately reaching the RCE input of CODEC U16 (pin 14) from the Q3 output of U26.
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Chapter 8
To select the proper TDM bus, the microprocessor produces two control signals, MBE0 and MBE1. These signals are applied to the A and B address inputs of U27, a 4-channel multiplexer (pins 14 and 2). The digital data on the three TDM buses, as well as the CT (Companded Tones) signal, are continuously latched into U28. Depending on the address contained in the control signals, either MB1, MB2, MB3, or CT is selected by U27. The appropriate data exits the multiplexer from the X output (pin 7) and is presented to the RDD input of the CODEC to be converted to an analog voltage and sent to the base station for transmission. As an example, assume that the module is to transmit slot 21 from TDM bus 2 (MB2). The microprocessor programs the TSAC to put out an RXE signal when slot 21 comes around. It also sets bits MBE0 to 1 and MBE1 to 0, to present the control inputs of U27 a binary address of 10 (or decimal 2). This address allows the digitized audio from MB2 (TDM bus 2) to appear at the X output of U27. After processing in the CODEC, the analog audio signal is routed to the lowpass filter hybrid (Z4) before going into the line driver circuit and out onto the telephone lines to the base station.
DLM audio processing

The audio signals received from the base station are passed through phone lines to the CEB and are first processed by the BIM. These signals appear at card edge pins 57-60 and are transformer-coupled into the Digital Level Memory (DLM) circuits. The DLM provides two main functions:
p p
Adjusts the gain of the DLM circuit so that there is a constant audio output level of 0 dBm at Z2-10 whenever voice audio at transformer T1 or T2 is -25 to +10 dBm, which is selected by JU1 and JU2 Holds the gain of the DLM hybrid Z2 at the level set by the last voice input signal that was present just prior to a pause in the voice input signal
During normal voice operation, audio mute gate Q201 is on. Input voice audio is applied to the DLM gain hybrid Z2-4. A feedback amplifier inside the Z1 hybrid adjusts the gain to provide a constant audio output of 0 dBm at Z2-10. For systems using separate wire pairs for transmit and receive audio, transmit audio leaves the board at card edge connector pins 57 and 58. Receive audio enters the BIM at card edge connector pins 59 and 60. In this case, receive audio is buffered by U206B, passed by FET Q203, and is summed into Z2 at pin 5. The AGC circuit connected between Z2-1 and -2 has fast attack and slow release times. AGC-controlled audio is applied to DLM comparator hybrid Z3-10, where it is compared to a noise signal (16 kHz). The output of Z3-8 is always switching high and low. If the audio input signal is voice, the switching rate is less than 1200 Hz. If the audio input signal is noise, the signal rate is greater than 1280 Hz. Counter U205 is reset (by LCLK = 80 Hz) every 12.5 milliseconds. If voice is present in the audio channel, U205 does not reach full count before reset and the output (U205-10) remains low. If noise is present in the audio channel, U205 does reach full count before reset and the output at U205-11 goes high. U205-11 output is clocked into U203 and provides a voice noise indication at U203 Q output.
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During voice pauses, Z3-16 goes high, indicating noise is present in the audio channel. This causes C235 to charge up, which, through NOR gate U31, turns the squelch gate (Q212) off to mute the audio going to the speaker. A high on Z3-16 also causes the Q output (U203-12) to go low. This enables a counter located on the DLM R-2R hybrid (Z1) to begin counting up. The count is converted to an analog voltage ramp at Z1-10. The ramp voltage increases as the counter increases. This voltage is applied to Z3-4 and is compared to the DLM gain hybrid control voltage applied to Z3-3. When the voltages are equal, the output of a comparator on Z3 changes state, causing Z3-7 to go high, disabling the counter on Z1. This latches the gain setting of the DLM gain hybrid (Z2) to the level set by the last voice input signal that was present just prior to the pause. Test tones are periodically looped through the DLM circuitry to verify audio path integrity. When a test is to be performed, the microprocessor outputs a 2W MUTE and a 4W MUTE signal. This turns off gates Q201 and Q203 to prevent 2-wire and 4-wire receive audio from interfering with the test tone. The microprocessor also causes the DLM HOLD signal to go low during test tones. This is done so that the tone test does not inadvertently cause a change in the gain setting that was latched when the last voice signal was present. The test tones are gated into Z2-5, and are routed from Z2-10 to other circuitry on the BIM. The DLM HOLD signal also causes gate Q212 to turn on, allowing the test tones to reach the CODEC (U16). Whenever voice is present in the audio channel, Z3-16 is pulled low and U203 is reset. The low on Z3-16 of causes C235 to discharge, which causes squelch gate Q212 to turn on, allowing audio to reach the CODEC. Reset of U203 causes Q208 to turn on, making U206-14 go high, turning on Q207, causing CALL to go low. This low signal is detected by the microprocessor, which in turn sends a message to the Console Operator Interface Module (COIM). The COIM then instructs the radio control board to generate the appropriate call indicator display at the operator position. When the voice stops, Q208 turns off, and capacitor C213 begins to charge. When the inverting input to U206 becomes sufficiently high, U206 output goes low and the call indication display stops. Jumpers JU5 and JU6 allow various call indication delays to be used. The output of the DLM circuit is routed to the CODEC (coding/decoding) integrated circuit, which converts the analog audio to a Pulse Code Modulation (PCM) format and provides the anti-aliasing filters required for accurate replication.
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Chapter 8
Microprocessor system
The MC6803 microprocessor and its support circuits have three major functions on the BIM:
p p p
Control logic generation for other BIM subcircuits System data bus access control Interpretation of input signals
The microprocessor system includes microprocessor U1; 16k X 8 EPROM U4 (which contains the control program for the microprocessor); octal transparent latch U2; data bus buffer U35; octal latches U7 and U32; address decoder U3; and 32k x 8 RAM U34. Octal latch U2 captures the lower eight address bits present on the data bus during the first half of each microprocessor machine cycle. These address bits are latched in to U2 by an Address Strobe signal (AS, pin 39) from the microprocessor. The data bus then serves as a true data bus for the remainder of the machine cycle. Address decoder U3 provides a logic low on one of eight outputs, depending upon the address the microprocessor is currently outputting to the address bus. This enables the microprocessor to select devices by merely outputting the appropriate device address. The address decoder provides eight control signals for device selection and control. These control signals are discussed further in subsequent paragraphs. Data bus transceiver U35 provides extra drive for the microprocessor data bus, compensating for loading due to the large number of devices connected to the data bus. The outputs of latch U32 are controlled by the microprocessor and are used to enable functions in various subcircuits of the board. The functions controlled by these outputs are:
p p p p p p
High guard enable and guard tone enable in tone control systems Mute of 2-wire receive audio and mute of transmit audio Enable of the dc generator board (in dc control systems) Disabling of the DLM activity checker circuit Control of test tone circuitry Muting of 4-wire receive audio
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Microprocessor reset and watchdog timer

The watchdog timer consists of binary counters U18A and B and associated components. This circuit provides a reset of the microprocessor during power up, and then monitors activity on one of the microprocessors outputs. If the watchdog does not periodically sense activity on this output, it attempts to reset the microprocessor. If the microprocessor is successfully reset, operation continues as normal. If the microprocessor does not reset properly, the module is three-stated and isolated from the system buses. When power is first applied to the BIM, U18A and B both power up randomly. If U18A, for example, powers up with the Q3 output low (pin 6), then the enable input at U18B (pin 10) is held low, preventing that counter from incrementing. Meanwhile, U18A begins to count LCLK pulses that occur at the E input (pin 2). (LCLK is a 77 Hz clock generated in the DLM circuitry.) When the count advances so that the Q3 output of U18A goes high, this counter is inhibited due to the appearance of that logic high on its clock input (pin 1). The same high signal appears at the enable input of U18B (pin 10), allowing that counter to begin incrementing. U18B continues to count up until its Q3 output goes high. When this occurs, both inputs to NAND gate U9C are high, causing the output to go low, turning transistor Q11 off. This causes RESET (U1-6) to go high, releasing the microprocessor from reset. In the event that U18A powers up with its Q3 output high, U18A is disabled due to the high appearing on its clock input. U18B increments at the LCLK rate until its Q3 output goes high, allowing the microprocessor to come out of reset as before. After being reset, if the microprocessor is performing correctly, it toggles the port 2 output (pin 10) approximately once every 10 ms. This square wave is inverted and level-shifted by U37-F and differentiated by capacitor C38, producing an impulse that resets U18A. Only negative transitions of the square wave from the microprocessor result in reset pulses. This means that U18A is reset about once every 20 ms. If it does not get reset, the Q3 output of U18A goes high after 103 ms. This enables U18B to begin counting. After counting for 103 ms, the Q3 output of U18B goes low. This causes RESET on the microprocessor to go low. Another 103 ms later, the Q3 output of U18B returns high, causing Q11 to turn off, allowing the microprocessor to come out of reset. If the microprocessor is not able to come out of reset, or if it is unable to reset U18A, the signal at U1-6 is a square wave with a period of about 200 ms. If the BIM is performing correctly, that RESET pin is at a steady 5 V level. The microprocessor is able to voluntarily power the BIM down by setting the signal labeled PD (U1-13) high. This signal appears at the cathode of CR26, turning on transistor Q7, but turning off Q9. This sequence causes the green LED (DS2) to turn off and the red LED (DS1) to turn on. Table 8-1 shows the LED status for various operating conditions of the BIM.
Table 8-1
BIM LED status operating conditions Condition Red LED

OFF ON FLASH FLASH OFF ON
Green LED
OFF OFF OFF OFF
Normal operation Microprocessor powerdown Insane microprocessor Fail ROM/RAM check Lose 12 V
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Chapter 8
Module address programming

Each BIM is assigned a fixed slot on the TDM bus. The BIM receives analog audio from the base station, digitizes it and inserts it into this slot. The slot is defined on the BIM by DIP switch S2, which is programmed for the correct binary word. Switches A0-A4 define a binary number corresponding to the TM slot into which the base station audio is to be inserted. Switches A5 and A6 select one of the three possible TDM buses. The microprocessor reads the DIP switch selection by writing address $7B on the address bus. This causes the Q3 output of address decoder U3 (an active low signal) to go low. The eight bits programmed by the DIP switch then appear on the data bus. After reading the data bus, the microprocessor sends the appropriate information to TSAC U5 through three outputs. The first two (pins 15 and 16) are connected to the CS (Chip Select-pin 4) and DI (Data Input-pin 3) leads of U5. The other signal exits from pin 9 of U1 and is labeled TCLK (TSAC Clock). This line connects to the CLK lead of the TSAC (pin 2). The information on these lines programs the TSAC to place the base station audio into the slot that has been selected by the DIP switch. For example, if the DIP switch contains the following bit pattern:
TDM bus number A7
1 (TBIM) 0 (Conven tional)
Slot number A4
1
A6
0
A5
0
A3
0
A2
1
A1
0
A0
1
The base station audio would then appear in slot number 21 (10101) of TDM bus number 1 (00).
Each board in the Central Electronics Bank that passes audio and/or data via the TDM bus structure requires a unique fixed slot number, e.g. TDM 05. The address is assigned using switch positions A0-A6 on the board TDM dip switch. In special cases involving the BIM and the COIM, dip switch position A7 (MSB) is used to define functionality such as on the BIM making it a Trunking BIM or "TBIM" and with the COIM whether Elite or Classic CRT console. Switch Position Open/Off (1) Closed/On (0) BIM TBIM BIM COIM Elite Classic
See the following page for examples.
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Chapter 8 Theory
If A7 is set incorrectly it may result in: 1. Incomplete COIM to Op download. 2. Will remain in continuous Download loop.
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Chapter 8
Data communications
Within the CENTRACOM Gold Series system, all of the modules are linked together by a data bus, controlled by the System Timer Module (STM). A detailed discussion of data bus arbitration and data packet protocol is presented in the System Timer Module chapter. The BIM can receive data from other modules in the system and write data to them.
Receive data
The information exchanged between the BIM and the other modules in the system enters and exits the BIM through the same card edge connector pin (pin 86-labeled DB). Data is continuously received here and passed to microprocessor U1 from serial-in/parallel-out shift register U11. Data from the bus is always available to the microprocessor at the parallel outputs. The movement of all data on the data bus is clocked by a signal generated on the system timer module labeled DC (Data Clock). This signal is active during slots 0 and 1 of the TDM bus. DC enters the BIM at card edge connector pin 97, and is clocked into latch U14 at the D1 input (pin 4) before being inverted and level-shifted by U17. DC is then used to clock data into U11. The bit stream on the data bus is gated through two Schmitt inverters (U12A and B) and downshifted by U17E before it is clocked into U11. After eight data clock cycles have occurred, a byte of data is available, in parallel, at the outputs of U11. These outputs are connected to the BIM internal data bus but are normally held in a three-state mode. When the microprocessor is to read in the data, it writes address $7D. This causes the MDR output of address decoder U3 (Q5-pin 10) to go low. This low is applied to the output enable pin of U11 (OE2-pin 3), allowing the outputs of U11 to be placed on the data bus and read by the microprocessor. The BIM microprocessor does not read the outputs of U11 unless it is first informed that there is information on the system data bus. It is alerted when DBSY (DATA BUSY) goes high. This bus is also controlled by the system timer module and is set high whenever a data source has been given control of the system data bus. DBSY connects to the BIM through card edge connector pin 94. When there is activity on the data bus, a high signal on that line is clocked into latch U14 at the D2 input (pin 6). The signal exits U14 at Q2 (pin 7), is inverted through NAND gate U9B and applied to one input of U31A. The other input to this gate is tied to the TS1 signal, so that the microprocessor NMI interrupts are masked when TS1 is low. If TS1 is low, as it normally is, DBSY passes through U9B and is inverted by U31A and U17F, signaling an interrupt, alerting the microprocessor that there is activity on the system data bus. The microprocessor is able to mask the DBSY interrupts by setting pin 20 high. This causes open collector gate U37E to pull low, grounding the input to U9B. The result is that the output of U9B is always high, in turn keeping the output of U31A low. This low is inverted and level shifted by U17F, forcing NMI high, disallowing DBSY interrupts.
DBSY interrupts are also not permitted when the module is three-stated because of a failure in some aspect of the circuitry. In this case, it is the TS1 signal at the input of U31A
which causes a high at the NMI input of the microprocessor. The net result is that a faulty BIM is not permitted access to the system data bus.
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Another microprocessor interrupt, IRQ (U1-5), synchronizes the microprocessor to the start of a new frame on the TDM bus. The microprocessor can externally mask these interrupts because there are occasions when the microprocessor must not be interrupted. If it must mask frame sync interrupts, the microprocessor writes to address $7C. This address is decoded by U3 and causes the Q4 output of that chip (pin 11) to go low. When this low is combined with a low on the R/W line (from U1-38), a logic low is clocked through to the Q output of U21A (pin 5). This signal is, in turn, applied to the D input of U21B (pin 12). At the start of the TDM frame, the system frame synchronization signal, A4, goes low. This negative transition is seen as a rising edge at the Q output of D flip-flop U15A (pin 2). This signal, which also synchronizes TSAC U5, is level-shifted to 5 V by U17D and U17E, and is used to clock U21B. As long as pin 12 of U21B is low, only logic highs are clocked out of the Q output of that chip and the microprocessor is not interrupted. To unmask frame sync interrupts, the microprocessor performs a read of address $7C. This again causes the Q4 output of U3 (pin 11) to go low. In this case, however, the D input of U21A is high (pin 2), clocking a high through to the Q output of U21A. A low at Q of U12B is then clocked to the IRQ lead on the transition of A4, interrupting the microprocessor. This interrupt is a signal to the microprocessor that new data is being clocked into U11. The microprocessor reads the data by accessing address $7D, initiating the sequence described above. When the Q5 output of U3 (pin 10) goes low at the end of the data loading sequence, it also resets U21B so that the interrupt to the microprocessor is cleared. Once the DBSY pulse is received and an NMI interrupt is initiated, the microprocessor allows the first three bytes of the 13-byte data packet to be latched onto its data bus on successive TDM frames. The third byte of the packet contains the address of the module the data is intended for (destination byte). The microprocessor then checks whether this address matches the one assigned to it, a binary number programmed into the DIP switch located on the module. There are special cases in which a data packet is addressed to all the modules and, though this packet does not contain the BIM address, the microprocessor recognizes and receives this data. If the data is intended for the BIM, the data is continuously placed, byte by byte, onto the module data bus, and synchronized by successive IRQ interrupts. If the packet is addressed to another module, the microprocessor masks frame sync IRQ and ignores the rest of the data packet. The sequence in which data is received proceeds as follows: First, DBSY goes high, indicating that there will be data on the data bus during the next 13 frames. The data happens to be coincident with time slots 0 and 1 on the TDM bus. DBSY causes an NMI interrupt in the microprocessor. The microprocessor immediately unmasks the frame sync interrupts IRQ and reads the data that has been clocked into U11. After reading the first three bytes of data, the microprocessor has determined whether the data is intended for the BIM. If the data is intended for another module, it masks the frame sync interrupts and goes on to other tasks. Otherwise, it leaves frame sync interrupts unmasked so that it is interrupted each time a new byte of data is ready to be released from the output of U11 onto the data bus.
Transmit data
When the BIM microprocessor needs to use the system data bus to transmit data packets, it must first be granted control of that line. While all modules in the system receive data at
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Chapter 8
all times, only one module at a time may transmit data. All the modules that have access to the data bus share control of it according to their respective slot numbers. If a module assigned to slot 0 has control of the data bus, when it is finished sending data, the module assigned to slot 1 will get a chance to use the data bus. If it has not requested use of the data bus, the module assigned to slot 2 will get a chance. This continues to slot 31 and then starts over again at slot 0. The System Timer Module (STM) functions as the arbiter of the data bus. Data bus status is indicated by the busy bus (BSY), a line controlled by the STM. This bus is low when the data bus is not available and toggles at a rate of two pulses per slot when the data bus is available. These pulses occur at the first and fifth bits of each slot. This clocking constitutes a polling sequence for all boards in the system. There is one BSY bus corresponding to each of the three TDM buses. A board that is jumpered for TDM bus 1 will also be jumpered for BSY1. The same applies to TDM bus 2 and BSY2, and TDM bus 3 and BSY3. These lines enter the BIM at card edge connector pins 74, 78 and 82, with jumpers inserted according to which TDM bus the module is assigned to. The selected line is connected to the D0 input of U14 (pin 3). When the BIM requires use of the data bus, the microprocessor initiates a data request by writing address $7F on the module address bus. This address is decoded by U3, causing the Q7 output, DR, of that chip to go low. This low is inverted and level shifted to 12 V by U37D, clocking a low to the Q output of U20A. This low does not reach the next stage of the data request circuit until the SN signal goes low. This signal, derived from the TXE output of TSAC U5 through NOR inverter U19A, goes low whenever the time slot assigned to the module is valid on the TDM bus. The appearance SN enables three-state buffer U25C to apply DR (from U3-7) to the D input of U20B (pin 9). Meanwhile, the BSY signal, consisting of the pulses at bits one and five, is continuously clocked into latch U14. These pulses are then applied to the clock input of U20B (pin 11), clocking the low signal originating from U3-7. The net result is a high at the Q output of U20B (pin 12), which is then buffered by U25D and bus driver circuitry and placed on the DRDY (DATA READY) line, exiting the board at card edge connector pin 83. This signal is only allowed through to that line as SN goes low, (when the time slot assigned to the BIM occurs). The high-going transition on DRDY signals the data bus arbiter on the STM that the BIM requires access to the data bus. The arbiter then halts the polling sequence, forcing the BSY lines low, preventing any other modules from gaining access to the data bus. The Q output of U20B is also applied to the reset pin of U20A (pin 4), cancelling the data request by forcing the Q output of U20A high. At the same time that the microprocessor requests use of the data bus, it also writes out the first byte of its data packet, the start-of-text byte, to parallel-to-serial shift register U10 through the module data bus. U10 serially clocks data onto the system data bus only if the BIM has a data grant (the Q output of U20B is high). The microprocessor writes data into U10 by writing to location $7E. This address is decoded by U3, causing the Q6 (MDW) output of that chip (pin 9) to go low. This signal, together with the R/W signal from U1, appear at the inputs of NOR gate U22B. When both of these signals go low, a high appears at one input of U13C which, combined with a high pulse from the E clock (microprocessor synchronization clock), causes the PL input of U10 to go low, latching data from the microprocessor data bus into latch U10.
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When the BIM has a data grant (DG), buffer U25F is enabled by a low on the Q (DG) output of U20B (pin 13), allowing the data clock (DC) to reach U10. The data is then serially clocked onto the system data bus. The outgoing bit stream is up-shifted by U24A and passes through buffer U25E and bus driver circuitry on its way to the data bus. As with U25F, buffer U25E is enabled only when the BIM has a data grant. To this point, the microprocessor has issued a data bus request and has written the first byte of the data packet (the start-of-text byte) into U10. Even when the module has been granted control of the bus, the microprocessor must verify it. So, when the next frame sync interrupt occurs, the microprocessor latches the second byte of the packet (the data source byte in this case, its own slot address) into U10. In the next frame, the microprocessor latches the third byte of data into U10 (the destination address byte) and reads the data that was placed on the data bus during the previous frame (the source address byte). If that data contains its own slot address, the microprocessor knows that it has control of the data bus. It then continues to write data into U10 for 13 frames (a complete message packet). If the slot address contained in the second byte does not match that of the BIM, the microprocessor knows that it does not have control of the data bus. The microprocessor then re-latches the start-of-text byte into U10 and waits for the next DBSY to occur, repeating the process described above until it gains control. Once the microprocessor does gain control of the data bus, the module outputs data in 13 consecutive frames. During each frame when it has control, the module sends a DRDY pulse to the STM. Since the BIM has control of the data bus for 13 frames, 13 such pulses will be generated. These pulses are counted on the STM and after 13 pulses have been counted, the STM forces the busy bus to begin polling again. In order to prevent a module from capturing the data bus for consecutive data transmissions, during the fourteenth frame, the STM outputs only one pulse during the time slot assigned to the module which just finished transmitting data. This single pulse appears at the fifth bit of that slot. The consequence is that a rising edge will appear on the appropriate BSY bus, which will clock a logic high into U20B. This causes the Q output of that device to go low, removing the data grant from the module. Normal polling (two pulses per slot) then resumes during the next slot. The data transmission sequence proceeds as follows: First, the microprocessor generates a DRDY pulse which is routed to the STM, indicating that the BIM requires use of the data bus. DRDY is enabled only when the time slot assigned to the BIM occurs on the TDM bus. The microprocessor also latches the first byte of the data packet (start-of-text) into U10. Next, the STM halts the polling sequence on the BSY lines and a DBSY pulse initiates an NMI interrupt to the microprocessor, indicating that some activity is present on the data bus. The microprocessor then assumes it has control of the data bus, loading the second and third bytes of the packet into latch U10 in successive TDM frames. It then reads back the second byte (the source address byte) to verify that the data currently on the bus indeed originated from itself. If this address matches that programmed in the BIM DIP switch, the microprocessor continues to place the data packet on the bus until the message is complete (13 bytes). On the fourteenth byte, the data grant is removed from the board and normal polling resumes during the next slot on the TDM bus. If the address does not match, the BIM has not captured the bus and must continue the request sequence until it gains control.
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Chapter 8
Auxiliary input/output
The BIM has six card edge connector pins (65-70) that are brought out to the termination panel and can be used as auxiliary inputs or outputs. The I/Os are connected to the BIM internal data bus through three-state buffer U6. The I/O lines are pulled up, making their normal state a logic high (5 V). The microprocessor periodically reads the I/O bits and sends their status over the system data bus to the main microprocessor on the COIM. The COIM microprocessor interprets the I/O bits and take the necessary actions. When reading the I/O bits, the BIM microprocessor also reads the status of the CALL and IRQ inputs to U8. The status of the CALL line is sent to the operator position to control a call indicator display. The IRQ information is used by the BIM microprocessor as a synchronizing signal when it is generating tones. The BIM microprocessor can write to the I/O lines as well. To accomplish this, it writes to latch U7. That data is applied to driver U29, which contains seven open-collector Darlington drivers. The driver outputs are connected to the I/O card edge connectors, giving the microprocessor the ability to pull the I/O lines low.
Tone generation
Sometimes the BIM must generate and transmit tones to the base station. The BIM microprocessor generates these tones by looking up the required data in a ROM table, which is based on the JU13 setting. This is done by placing the binary number, byte by byte, on the internal data bus and then routing it to the same circuits that process the digital audio signals for transmission to the base station. This data is labeled CT (Companded Tones) and appears at pin 2 of U24A. In order to allow CT to reach the D/A circuitry, the microprocessor initiates a tone enable procedure. For synchronization, it programs TSAC U5 to output a high RXE signal during slot 0 of the TDM bus. RXE is latched into U26 through the D0 input (pin 3). It exits through the Q0 output (pin 2) and is labeled DRXE . Whenever the BIM does not have control of the data bus, the DG signal is high, resulting in a high at the Y output of U27 (pin 9, labeled TONE ENA). This signal appears, together with DRXE, at the inputs of NAND gate U9D (pins 12 and 13). Whenever slot 0 occurs, the output of U9D (pin 11) goes low for one slot, enabling three-state gate U33E to pass CLK pulses through to the C2 input of U10 (pin 15). This allows eight bits of serial tone data to be clocked out of U10 at the system bit rate (2 MHz). The BIM is incapable of sending data on the system data bus at the same time that it is generating tones, since the output of U25E is three-stated. The tone data (CT) is level-shifted by U24A and clocked into latch U28, appearing there at the D3 input (pin 14). The microprocessor writes a binary 0 to multiplexer U27 through MBE0 and MBE1. This binary number appears at the A and B control lines of U27, instructing it to gate CT from latch U28 to the X output of the multiplexer (pin 7 of U27). From this point, the tone data is treated as normal transmit audio. When selected, the data is then applied to the CODEC. At the next occurrence of time slot 0, eight new bits are sent by the microprocessor to latch U10 and another sample of the tone is processed by the CODEC.
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From the CODEC, the tones (now in analog form) are applied to low pass filter hybrid Z4. If the tones being generated are function tones, they are simply low-pass filtered and applied to the line driver hybrid. If the tones are to be transmitted by the base over the air, they must first be de-emphasized. This is done so that all tone frequencies are transmitted with the same deviation after being pre-emphasized by the base, ensuring that they will be received at the same level. To de-emphasize the tones, pin 17 of the microprocessor is set to logic 0. This low is inverted by U37C, (labeled DEMP ) and applied to pin 3 of the low pass filter hybrid. This high switches in a de-emphasis network in the hybrid, causing de-emphasized tones to be sent to the base station.
Guard tone gating and low pass filter hybrid

One important function of the BIM is to mix the transmit audio which it passes to the base station with the guard tone to key the transmit function. The guard tone is generated on the system timer module by dividing the main clock frequency of 3.9672 MHz down to 2175 Hz, by selecting JU13. This square wave is passed to the CEB interconnect board and routed throughout the system. The Guard Tone (labeled GT) enters the BIM at card edge connector pin 98 and appears at the input of NAND gate U9A (pin 1). The other input to this gate is derived from the Q1 output of latch U32 (pin 5). When the microprocessor sets this bit low, it is inverted and level shifted through U24E and labeled GTE (Guard Tone Enable), resulting in a logic low at U9A (pin 2). The 2175 Hz square wave is then applied to a resistor attenuator on the low pass filter hybrid, entering at pin 12. When applied to this lead, the signal appears at a point in the circuit that provides the degree of attenuation necessary to produce a guard tone level approximately 30 dB lower than the high guard tone level. This provides the low guard tone to the base station. When the microprocessor must send high guard tone, it sets the Q0 output of U32 (pin 2) high. This signal is level shifted and inverted by U24F and is labeled HGE (High Guard Enable). The resulting low appears as one input to U31B. The consequence is that the 2175 Hz is now applied to pin 11 of the low pass filter. This lead is connected to a point in the resistor network where the attenuation provided is 30 dB higher than the low guard tone level. At this time, both high guard and low guard tones are being generated but the high guard tone dominates. In either case, the tone is routed through a three-stage, five-pole low-pass filter inside the hybrid. It then appears at the input to the line driver hybrid (Z5-2, 3) to be placed on telephone lines connected to the base station.
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Chapter 8
Three-state control
The BIM has specialized bus drivers for driving the DRDY bus, the data bus and the TDM bus. These drivers are designed to be fail-safe in that the board cannot short circuit any of them. To accomplish this goal, power and ground are switched to the drivers. When power and ground are switched off, the bus drivers are in a three-stated mode, and appear as a high impedance to the buses they drive. By virtue of the switched power and ground, the drivers are normally held in this high impedance state and are enabled only when it is required that they drive their respective buses. The driver consisting of Q21 and Q22 drives the DRDY bus; the driver consisting of Q19 and Q20 drives the system data bus; and the driver consisting of Q23 and Q24 drives the TDM bus. In the event of a board failure, the bus drivers are also held in three-state, so that the board is isolated from the rest of the system. The bus drivers are enabled through NOR gates U19A, U19B, and U19C. The output of U19A is passed through latch U14 (D5) where it is labeled SN. This signal goes low whenever the TDM slot assigned to the BIM becomes valid and is used to synchronize the functions of the BIM with the occurrence of the module time slot. This low transition appears also at the input of U19B (pin 9), causing the output of that gate to go high. This high is inverted by U19C which turns off transistor Q6, allowing Q18 and Q4 to turn on, feeding switched power to the bus drivers. The switched power in turn saturates Q3 and Q5, providing switched ground to the bus drivers. When the output of U19A returns high, the output of U19C goes high, turning on Q6. This turns Q18 and Q4 off, also shutting down Q3 and Q5 through CR34. During normal operation, transistor Q9 is saturated and the green LED is on. Should a failure occur, Q9 turns off. This allows one of the inputs of U19B (pin 8) to be pulled high, forcing a low at the output regardless of the state of the other input. The results is that the bus drivers are disabled and the BIM is three-stated off of the system buses.
Logging recorder output

The BIM supports an optional logging recorder that records transmit and receive audio for future playback. U30 sums transmit and receive audio and drives transformer T3, which places the audio on LOG OUT pins 63 and 64 of edge connector P1. This audio is passed to P2 on the CEB interconnect board for connection to the logging recorder. The BIM performs routine audio diagnostic testing during normal operation by periodically injecting 2175 Hz bursts into its audio paths. Q214 mutes these tones to prevent inappropriate logging recorder activation. Prior to the test tones being sent, the BIM microprocessor writes a word to octal latch U7. This causes U7-9 to go high (+5 V). This signal is passed to level shifter/inverter U29, and then to inverter U12. U12-8 drives the gate of an N-channel JFET (Q214) placed across the output and inverting terminals of operational amplifier U30. When the JFET gate voltage is positive relative to its source terminal, (as in the case when test tones are being muted) the JFET is on (has low resistance between source and drain). Low JFET resistance causes U30 to have low gain so that it cannot drive transformer T3, thus muting the test tones. Conversely, if the JFET gate voltage is negative relative to its source terminal, the JFET is off and audio passes to the logging recorder unimpeded.
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Table 8-2
Pin definitions for BIM connector P2

Connected to/Function
Aux audio in from P1-62 or TXI from codec via JU19 Ground Spare bus 1 on motherboard from P1-72 (has a feed-thru) Aux IO5 from P1-69 2W DC negative input to T1-1 Aux IO6 from P1-70 2W DC positive input to T1-4 Processor port U1-8 2W audio from P1-58 2W audio from P1-57 4W audio from P1-60 4W audio from P1-59 Aux IO latch U7-19 (goes active during all tone tests) Processor serial port U1-16 (data to TSAC) Fused 15 volts Processor port U1-9 (TCLK signal to TSAC) Processor port U1-17 DLMed audio from z2 via JU28/29 Q4 output of data latch U32-12 5 volts
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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Chapter 8
Table 8-3
Integrated Circuit Description + 12 V

1 10 8 14 16 8 8 10 8 14 7 8 10 14 7 7 16 14 16 8 16 14 14 8 7 7 7 7 10 7 16 16 16 16 8 8 8 8 8 8 14 7 10 16 14 8 28 10 7 20 14 20 4 14 14 20 14 1 8 7 8 14 16 20 16 20 16
Reference Designation
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36
Logic Ground
7 20 16 28
+5V
Analog Ground
Description
Microcomputer 3-State Octal Latch 3-Line to 8-line Decoder 16k X 8 EPROM Time Slot Assigner 3-State Hex Buffer Latch 3-State Hex Buffer Quad 2-input NAND Gate 8-Bit Shift Register 8-Bit Shift/Storage Register Hex Schmitt Trigger Quad 2-Input NAND Gate Hex D-Type Flip-Flop Dual D-Type Flip-Flop PCM Mono Circuit Hex Inverter Dual Binary Up Counter Quad 2-Input NOR Gate Dual D-Type Flip-Flop Dual D-Type Flip-Flop Quad 2-Input NOR Gate Octal Line Driver/Buffer Hex Inverter w/Open Collector Outputs 3-State Hex Buffer Hex D-Type Flip-Flop Dual 4-Channel Data Selector Hex D-Type Flip-Flop 5V to 15V Interface Driver Dual Operational Amplifier Quad 2-Input NOR Gate Latch 3-State Hex Buffer 16k X 8 RAM or 32k X 8 RAM Transceiver Triple 3-Input NAND Gate
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Chapter 8 Theory
Table 8-3
Integrated Circuit Description (continued) + 12 V

7 14 16 16 4 7 8 8 11
U37 U203 U204 U205 U206
Logic Ground
14
+5V
Analog Ground
Description
Hex Inverter Dual D-Type Flip-Flop 4-Bit Divide by N Counter Dual Binary Up Counter Quad Operational Amplifier
Table 8-4
Master BIM Jumper Table

Position
"2D" "2I" OUT -25 dBm (US) -35 dBm (international) -40 dBm 4-Wire receive sensitivity: "4D" "4I" OUT -25 dBm (US) -35 dBm (international) -40 dBm Normal operation Special applications only DLM/AGC operation Call LED dropout delay Call LED dropout delay Call LED activation (voice or activity) Normal operation Special applications only
Jumper
JU1
Function
2-Wire receive sensitivity:
JU2
JU3
IN OUT
JU4 JU5 JU6 JU7 JU8
See Table 8-5 See Table 8-6 See Table 8-6 See Table 8-7 OUT IN
JU9 JU10 JU11 JU12
SeeTable 8-5 -See Table 8-7
DLM/AGC operation Not used Call LED activation (voice or activity) 4-Wire receive termination:
IN OUT JU13 JU14 JU15 JU16 See Tables 8-8 and 8-9 See Table 8-10 See Table 8-11 See Table 8-11
600 ohm 10k ohm System clock and guard tone frequencies 2-Wire and 4-Wire muting 2-Wire transmit termination 2-Wire transmit termination
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Table 8-4
Master BIM Jumper Table (continued)

Position
IN OUT 1k ohm 10k ohm Normal operation Special applications only Not used Not used Not used 2-Wire transmit max output level: "D" "I" +11 dBm (US) - 10 dBm (international) Busy bus selection: "B1" "B2" "B3" Busy bus 1 Busy bus 2 Busy bus 3 Mux bus selection: "M1" "M2" "M3" Mux bus 1 Mux bus 2 Mux bus 3 2-Wire and 4-Wire muting 2-Wire and 4-Wire muting 2-Wire and 4-Wire muting Receive audio routing Receive audio routing Firmware PROM size selection: "8K" "16K" 8k 16k or 32k Not used Not used Receive squelch gate selection: "ENBL" "DSBL" Enabled Disabled Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only
Jumper
JU17
Function
Logging recorder output termination:
JU18
IN OUT
JU19 JU20 JU21 JU22
----
JU23
JU24
JU25 JU26 JU27 JU28 JU29 JU30
See Table 8-10 See Table 8-10 See Table 8-10 See Table 8-12 See Table 8-12
JU31 JU32 JU33
---
JU34
IN OUT
JU35
IN OUT
JU36
IN OUT
JU37
IN OUT
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Table 8-4

Position
IN OUT Normal operation Special applications only
Jumper
JU38
Function
JU39
IN OUT
Normal operation Special applications only
JU40 "NORM" "TEST" JU41 "NORM" "TEST" JU42 "BIM" "SPI/DPI" JUA IN OUT JUB OUT IN JUC IN OUT
Codec (U16) loopback test: Normal operation Test mode Codec (U16) loopback test: Normal operation Test mode Logging recorder mute control: Board used as a BIM Board used as an SPI or DPI Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only
JUD
OUT IN
Normal operation Special applications only Normal operation Special applications only
JUE
OUT IN
Table 8-5
DLM or AGC Operation

JU4 JU9
IN OUT DLM operation AGC operation
IN OUT
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Table 8-6
JU5 IN OUT OUT
Call LED Dropout Delay

JU6 IN IN OUT 0.6 second 1.1 second 1.9 second
Table 8-7
JU7 IN OUT
Call LED Activation

JU11 IN or OUT IN Call LED responds to voice Call LED responds to activity
Table 8-8
JU13
System Clock Frequencies

JU13 Position A2 IN IN OUT OUT System Timer Module Crystal Frequency 3.6450 MHz (note 1) 3.9672 MHz (notes 2 and 3) 3.9672 MHz (notes 2 and 3) 4.0960 MHz (note 4)
Position A3 OUT IN OUT IN
Note 1: International non-Embassy/non-SmartZone Operation Note 2: Either configuration may be used for 3.9672 MHz Note 3: US non-Embassy/non-SmartZone operation Note 4: Embassy/SmartZone operation
Table 8-9
JU13
Guard Tone Frequencies

JU13 Position A0 IN OUT OUT IN System Timer Module Guard Tone Frequency 2100 Hz 2175 Hz 2325 Hz 2432 Hz
Position A1 IN OUT IN OUT
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Table 8-10
2-Wire and 4-Wire Receive Audio Muting JU25

OUT OUT IN OUT IN OUT
JU14
OUT OUT OUT
JU26
OUT OUT OUT
JU27
Normal non-signaling BIM (muting controlled by uP) Normal non-signaling BIM (muting controlled by uP) Full duplex signaling - 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). Simplex or half-duplex signaling - 2W and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). External high speed mute (simplex) - 2W muted when switched ground at pin 68 of card edge connector (Aux I/O 4). External high speed mute (duplex) - 2W and 4W muted when switched ground at pin 68 of card edge connector (Aux I/O 4). Full duplex signaling with parallel console - 2W muted when switched ground at pin 68 of card edge connector (Aux I/O 4) and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). Signaling and external high speed mute - 2W and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3) or when switched ground at pin 68 of card edge connector (Aux I/O 4). Allows BIM uP to mute both 2W and 4W with the 2W mute control line.
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
Table 8-11
2-Wire Transmit Termination

JU16
"IN" "IN" "OUT" 600 ohm 900 ohm High Impedance
JU15
"IN" "OUT" "OUT"
Table 8-12
JU28 IN IN OUT

JU29 IN OUT IN Normal Operation (audio routed from DLM directly to squelch gate) Normal Operation (audio routed from DLM directly to squelch gate) TBIM with Dual LOBL (audio routed from DLM through Dual LOBL to squelch gate)
8-24
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Base Interface Module BLN6654D Overlay
68P81095E 50- A 11/30/ 2000
8-25
Chapter 8
8-26
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Base Interface Module BLN6654D Schematic

(Sheet 1 of 4)
68P81095E 50- A 11/30/ 2000
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Chapter 8
8-28
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Chapter 8

(Sheet 2 of 4)
68P81095E 50- A 11/30/ 2000
8-29
Chapter 8
8-30
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8

(Sheet 3 of 4)
68P81095E 50- A 11/30/ 2000
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Chapter 8
8-32
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8

(Sheet 4 of 4)
68P81095E 50- A 11/30/ 2000
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Chapter 8
8-34
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Chapter 8 Base Interface Module BLN6654D Parts List
BLN6654D Parts List

Reference
Description
Reference
Description
capacitor, fixed:
C1 thru 12 C13 C14 C15 thru 17 C18 C19 C20 thru 24 C25,26 C27 thru 29 C30 C31 C32 C33 thru 35 C36 C37 C38 C39,40 C41 C42 C43,44 C45 C46,47 C48 C49 C50 C51 C52 C53 C54 thru 93 C95,96 C97 thru 99 C100 C201 C202 C203 C204 C205 C206,207 C208 C209,210 C212 C213 C215 C216,217 C219 2113741B45 2313748G06 2313748G14 2113741B45 2313748G04 2113740B73 2113741B45 0811051A12 2313748G22 2113740B73 2313748G04 0884637L22 0811051A12 2113741B37 2113741B45 2113740B73 2113740B34 2313748G14 2313748G04 2313748G14 2113740B34 2313748G14 2113740B69 2313748G06 2113740B42 2113741B45 2382028P02 2313748G04 2113741B45 2113741B45 2113740B49 2313748G14 2113740B73 0811051A11 2113741B45 0811051A09 2313748G04 0884549T01 0811051A11 2113741B45 2113741B45 2313748G06 2113740B49 2313748G06 2313748G09 CAP CHIP CL2 X7R REEL 0.01 UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP ELEC 22 UF 35V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ELEC 1.0 UF 50V 20% CAP CHIP REEL CL1 30% 1000PF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .068 5 63V CAP ELEC 100 UF 25V 20% CAP CHIP REEL CL11000PF30% 50V CAP ELEC 1.0 UF 50V 20% CAP MTLZ POLYEST .22UF 10% 100V CAP MTLZ POLYEST .068UF 5% 63V CAP CHIP CL2 X7R REEL 4700PF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP REEL CL1 1000PF 30% 50V CAP CHIP REEL CL1 24PF 30% 50V CAP ELEC 22 UF 35V 20% CAP ELEC 1.0 UF 50V 20% CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 24PF 50V CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 680 CAP ELEC 4.7 UF 50V 20% CAP CHIP REEL CL1 30% 51PF 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ALU 1.0 20% 50V CAP ELEC 1.0 UF 50V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP REEL CL1 30% 100PF 50V CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 1000PF 50V CAP MTLZ POLYEST .047 5% 63V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .022 5% 63V CAP ELEC 1.0 UF 50V 20% CAPACITOR MYLAR BOXED 2.2UF 10% 250V CAP MTLZ POLYEST .047 5% 63V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP CHIP REEL CL1 30% 100 CAP ELEC 4.7 UF 50V 20% CAP ELEC 10 UF 35V 20%
C220 C221,222 C223,224 C226 C228 C235
2313748G04 2313748G22 2113741B45 0811051A12 2313748G04 2313748G05
CAP ELEC 1.0 UF 50V 20% CAP ELEC 100 UF 25V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .068 5% 63V CAP ELEC 1.0 UF 50V 20% CAP ELEC 2.2 UF 50V 20%
diode: (see note)

CR1 thru 6 CR7 thru 14 CR15 CR16 thru 19 CR20 CR22 thru 27 CR30,31 CR32,33 CR34 thru 36 CR37 CR38 thru 42 CR43 thru 48 CR50 CR51 thru 53 CR202 CR204 CR205,206 CR207 CR209 CR211 thru 213 CR215 thru 218 CR219 CR220 4882290T02 4813833C10 4882290T01 4813832A18 4813833C10 4813833C10 4813833C10 4813832A33 4813833C10 4813833C07 4813833C10 4813832A33 4813832A33 4813833C10 4813832A26 4813832A26 4813833C10 4813833C07 4813833C10 4813833C10 4813833C10 4882290T02 4813833C10 DIODE SI HOT CARRIER*HSMS2802* DIODE GEN PUR .1A 70V MMBD6050 DIODE SI HOT CAR HSMS-2800-31 6.8V TRANS SUP P6SMB6.8AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE 20V TRANS SUP P6SMB20AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE DUAL 100V 5C COMM ANO DIODE GEN PUR .1A 70V MMBD6050 DIODE 20V TRANS SUP P6SMB20AT3 DIODE 20V TRANS SUP P6SMB20AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE 13V TRANS SUP P6SMB13AT3 DIODE 13V TRANS SUP P6SMB13AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE DUAL 100V 5C COMM ANO DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE SI HOT CARRIER*HSMS2802* DIODE GEN PUR .1A 70V MMBD6050
light emitting diode: (see note)

DS1 DS2 4888245C24 4888245C22 DIODE LE 45C24 RED DIODE LE 45C22 GRN
fuse:
F1,2 6584539T12 FUSE SUBMIN AXL LD MCR3.5
jumper:
JU3 thru 7 JU9 JU11 JU12 JU17,18 JU26 JU28,29 JU34 thru 39 JUA0 JUC0 0611009B23 0611009B23 0611077A01 0611009B23 0611009B23 0611009B23 0611009B23 0611077A01 0611009B23 0611009B23 RES JUMPER RES JUMPER RES CHIP JUMPER RES JUMPER RES JUMPER RES JUMPER RES JUMPER RES CHIP JUMPER RES JUMPER RES JUMPER
68P81095E50-A 1/18/01
8-35
Reference
Part Number
Description
Reference
Part Number
Description
transistor: (see note)

Q1 Q2 Q3 thru 5 Q6 Q7 thru 9 Q10 Q11 Q12,13 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q201 Q202 Q203 Q204 Q205,206 Q207 Q208 Q209,210 Q211,212 Q213 Q214 4813824A12 4813823A04 4813824A12 4811043C02 4813824A12 4813824A06 4813824A12 4813824A18 4813824A18 4811043C02 4813824A09 4880141L03 4813824A09 4880141L03 4813824A09 4880141L03 4813823A04 4813824A18 4813823A04 4813824A18 4813824A11 4813824A12 4813824A18 4813824A12 4813823A04 4813824A18 4813823A04 XSTR NPN 40V .6A SW B=80 XSTR N-CH RF JFET MMBF5484LT1 XSTR NPN 40V .6A SW B=80 TSTR 48R00869570 A/I XSTR NPN 40V .6A SW B=80 XSTR NPN 30V DARLINGTON XSTR NPN 40V .6A SW B=80 XSTR PNP 40V .6A SW B=100 XSTR PNP 40V .6A SW B=100 TSTR 48R00869570 A/I XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR NPN 40V .6A GENP B=75 XSTR NPN 40V .6A SW B=80 XSTR PNP 40V .6A SW B=100 XSTR NPN 40V .6A SW B=80 XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR N-CH RF JFET MMBF5484LT1
resistor, fixed:
R1 thru 10 R17,18 R19 thru 24 R25,26 R27 R28 thru 35 R36 R37 R38 R39 thru 42 R43 R44,45 R46 R47 R48 R49 R50 R51 R52 thru 54 R55 R56 thru 59 R60 thru 64 R65 R66,67 R68 thru 76 R77 thru 80 R81 R82 thru 85 R86 R87 thru 90 R91 R92,93 R94 R95 thru 97 R98 R99 0611077A98 0611077A98 0611077B25 0611077B07 0611077A98 0611077A58 0611077A98 0611077A82 0611077B47 0611077B07 0611077A82 0611077B07 0611077A82 0611077B15 0611077A90 0611077B05 0611077A90 0611009A53 0611077B07 0611077A68 0611077A58 0611077A98 0611077A90 0611077B07 0611077B47 0611077A82 0611077B07 0611009A65 0611077A87 0611009A65 0611077A82 0611077A98 0611077A58 0611077A98 0611077A94 0611077A98 RES CHIP 10K 5%1/8W RES CHIP 10K 5% 1/8W RES CHIP 120K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 18K 5% 1/8W RES CHIP 4700 5% 1/8W RES FCF 1500 5% 1/4W RES CHIP 22K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES FCF 4700 5% 1/4W RES CHIP 3600 5% 1/8W RES FCF 4700 5% 1/W4 RES CHIP 2200 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 6800 5% 1/8W RES CHIP 10K 5% 1/8W
R100 R101 R102 R103 R104 R105 thru 109 R110 R111 R112 R113 R114 R115 thru 118 R119 R120 R121,122 R123 R124,125 R126 R127 R129,130 R131 R132 R133 R134 R135 R136 R137 thru 140 R141 R142,143 R144 thru 148 R149 R150 R151,152 R153 R154 thru 159 R160,161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 thru 179 R180 thru 185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195,196 R202 R203 R204 R205 R206 R207 R209 R210 R212 R214 R215
0611077A26 0611077A90 0611077B27 0611077A98 0611077B07 0611077B47 0611077B23 0611077A98 0611009A73 1883452F41 0611077B07 0611077A98 0611077A74 0611077A50 0611077B07 0611077A82 0611077B07 0611077A98 0611077A74 0611077A68 0611077A78 0611077A82 0611077A98 0611077A78 0611077A68 0611077A78 0611077A98 0611077A90 0611077B15 0611077A82 0611077A84 0611077B07 0611077A90 0611077B07 0611077A98 0611077A26 0611077A98 0611077A90 0611077A98 0611077B07 0611077A82 0611077B01 0611077A64 0611077A74 0611009A49 0611077A90 0611077A64 0611009A01 0611077A58 0611077A74 0611077A42 0611077A58 0611077A74 0611077A42 0611077A58 0611077A74 0611077A42 0611009A01 0611077A82 0611077B15 0611077B29 0611077B23 0611077B47 0611077B31 0611077A58 0611077B07 0611077A98 0611077B15 0611077B29
RES CHIP 10 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 150K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 10K 5% 1/8W RES FCF 10K 5% 1/4W POT BD CKT MOUNT A/I RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5%1/8W RES CHIP 100 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 2700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 10 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 12K 5% 1/8W RES CHIP 390 5% 1/8W RES CHIP 1000 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 4700 5% 1/8W RES CHIP 390 5% 1/8W RES FCF 10 5% 1/4W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES FCF 10 5% 1/4W RES CHIP 2200 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 180K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 180K 5% 1/8W
8-36
68P81095E50-A 1/18/01
Reference
Part Number
Description
Reference
Part Number
Description
R216 R217 R218 R219 R220 R222 R223 R224 R225 R226 R227 R228 R229 R230,231 R233 R234,235 R237 thru 239 R241 R243 thru 245 R247 R249 R250 R251 R252,253 R254 R255,256 R257,258 R259 R260 R261 R262 R263 R264 R265,266 R270 R271 R272 R273 R274 R276 R277 R278 R279 R300
0611077B23 0611077A82 0611077A74 0611077B47 0611077B23 0611077B23 0611077B07 0611077A98 0611077B37 0611077A98 0611077B37 0611077B25 0611077B47 0611077B07 0611077B37 0611077B31 0611077A98 0611077B23 0611077A98 0611077A68 0611077A56 0611077B31 0611077B15 0611077B13 0611077B29 0611077A98 0611077B07 0611077B15 0611077B47 0611077B07 0611077B11 0611077A80 0611077A74 0611009A49 0611077B47 0611077A98 0611077B07 0611077B47 0611077A98 0611077A74 0611077B23 0611077B15 0611077B47 0611077A58
RES CHIP 100K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 120K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 180 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 39K 5% 1/8W RES CHIP 180K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 33K 5% 1/8W RES CHIP 1800 5% 1/8W RES CHIP 1000 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 1 M 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 220 5% 1/8W
U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U203 U204 U205 U206
5184887K70 5184887K13 5113811D20 5184887K01 5184887K06 5184887K09 5184887K13 5184118K01 5184118K13 5184118K79 5184118K14 5184887K71 5184887K70 5184887K62 5184887K70 5183222M75 5184621K89 5184887K09 5184118K56 5184887K71 5184064F76 5184118K80 5184118K29 5184118K14 5184887K13 5184887K78 5184887K06 5113819D04
IC HEX D F/F_14174_ IC CMOS DUAL F/F __4013_ PCM CODEC/FLTR MONO-CIRCUIT IC CMOS HEX BUFFER __4049_ IC CMOS DUAL BIN CTR __4520__ IC CMOS QUAD NOR ___4001_ IC CMOS DUAL F/F __4013_ IC DL F/F D-TYPE _4LS74_ IC QUAD 2-INP NOR _4LS02_ IC OCT BFR 3-ST NONINV_4LS244_ IC TYPE 75LS05 IC HEX BFR 3-STATE NONINV_4503 IC HEX D F/F_14174_ IC DL 4 CHAN DATA SEL IC HEX D F/F_14174_ IC MONO AMP __1413_ IC DUAL OP AMP __3358_ IC CMOS QUAD NOR ___4001_ IC OCT D-TYPE F/F _4LS273_ IC HEX BFR 3-STATE NONINV_4503 IC CMOS SRAM (32KX8)_60256_ IC OCT BUS XCVR _4LS245_ IC 18K29 TTL LOGIC IC TYPE 75LS05 IC CMOS DUAL F/F __4013_ IC CTR BCD/4BIT BIN _4569_ IC CMOS DUAL BIN CTR __4520__ GEN PURPOSE 14 DIP MC3303P
voltage regulator: (see note)

VR1,2 VR3 5113816J03 5113816D01 IC 12V POSITIVE REG,100MA IC 5V POSITIVE RES. 1.0A
crystal: (see note)

Y1 4882611M15 4.9068 MHz CRYSTAL
network:
Z1 Z2 Z3 Z4 Z5 0182989R27 0182989R36 0182989R26 0182989R30 0182989R29 MODE HYBRID R 2R MODE HYBRID GAIN ALC MODE HYBRID CPTR ALC MODE HYBRID FLTR XMT MODE HYBRID DVR LINE
switch:
S1 S2 4084961N01 4083849F02 SW PB SPDT MOMENTARY SWITCH ROCKER DIP 8 POSTN
0310943J09 0982808R10 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 2683678T02 2880001R03 SCRTPG TT3X0.5X6 INTSTARPAN (2 used) SKT IC DIP 28 CONT (used with U4) SKT CONN (used with JU1) SKT CONN (used with JU2) SKT CONN (4 used with JU13) SKT CONN (used with JU15) SKT CONN (used with JU16) SKT CONN (used with JU22) SKT CONN (used with JU23) SKT CONN (used with JU24) SKT CONN (used with JU30) SKT CONN (used with JU33) SKT CONN (used with JU40) SKT CONN (used with JU41) SKT CONN (used with JU42) HEATSINK REGULATOR CON PCB HDR .1 GLD SR ST 3 POS (used with JU1)
transformer:
T1 T2,3 2583036L01 2584007C02 XFMR AF XMFR AF
integrated circuit: (see note)

U1 U2 U3 U5 U6 U7 U8 U9 U10 U11 U12 U13 5183625M66 5183539M01 5184118K34 5184704M45 5184887K71 5184118K56 5184118K27 5184887K08 5184118K35 5184810F64 5184887K52 5184118K06 IC BI IC 39M01 TTL LOGIC IC DCDR 3-TO-8 LINE _4LS138_ IC CMOS DGTL __14416_ IC HEX BFR 3-STATE NONINV_4503 IC OCT D-TYPE F/F _4LS273_ IC TYPE 74LS367 IC CMOS QUAD NAND __4011_ IC SHIFT RGTR 8-BIT _4LS165_ IC 8BIT SHIFT RGTR _4LS229_ IC MC14584BCP IC 74LS00 TTL LOGIC
68P81095E50-A 1/18/01
8-37
Reference
Part Number
Description
Reference
Part Number
Description
2880001R03 2880001R03 2880001R03 2880001R03
CON PCB HDR .1 GLD SR ST 3 POS (used with JU2) CON PCB HDR .1 GLD SR ST 3 POS (used with JU15) CON PCB HDR .1 GLD SR ST 3 POS (used with JU16) CON PCB HDR .1 GLD SR ST 3 POS (used with JU22)
2880001R03 2880001R03 2880001R03 2880001R03 2880001R03 2880001S03 2880001S03 2880001S04 2883290P04 5583323P01
CON PCB HDR .1 GLD SR ST 3 POS (used with JU30) CON PCB HDR .1 GLD SR ST 3 POS (used with JU33) CON PCB HDR .1 GLD SR ST 3 POS (used with JU40) CON PCB HDR .1 GLD SR ST 3 POS (used with JU41) CON PCB HDR .1 GLD SR ST 3 POS (used with JU42) CON PCB HDR 1 GOLD DR ST 6 POS (used with JU23) CON PCB HDR 1 GOLD DR ST 6 POS (used with JU24) CON PCB HDR 1 GOLD DR ST 8 POS (used with JU13) PLUG HEADER 20 PIN HNDL CKT BD
NOTE: For optimum performance, diodes, transistors, integrated circuits,

and crystals must be ordered by Motorola part number.
8-38
68P81095E50-A 1/18/01
8 8 Base Interface
Module
About this chapter

Section
Introduction Theory BLN6654D Parts List
Page
8-2 8-3 8-69
Models covered
The following models of the Base Interface Module (BIM) are covered in this chapter:
Model
BLN6654D
Description

68P81095E 50- A 11/30/ 2000-U P
8-1
Chapter 8
Introduction
Introduction
The BIM interfaces a base station to multiple operator positions at the console site. The BIM performs the following functions:
p p p p
Receives analog audio from the base station, digitizes it, and routes it to all operator positions in the system Receives digital audio from any operator position, converts it to analog, and sends it to the base station Generates the proper tones or dc levels necessary to control the base station. Sends data to the operator positions to acknowledge commands and to report its status
8-2
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Chapter 8
Theory
The BIM consists of the following circuits:
p p p p p p p p p p p p
Receive audio Transmit audio DLM audio processing Microprocessor system Microprocessor reset and watchdog timer Module address programming Receive/transmit data communications Auxiliary input/output Tone generation Guard tone gating and low pass filter hybrid three-state control Logging recorder output
Theory and troubleshooting charts for the DLM hybrid, the line driver, and the low pass filter hybrids are included in Chapter 6.
Receive audio
The BIM digitizes audio from the base station and places it in the proper slot on the Time Division Multiplexed (TDM) bus for routing to various parts of the system. This audio signal enters the BIM through card edge connector pins 57 and 58 if a 2-wire configuration is employed, and through pins 59 and 60 if a 4-wire system is used. Since the signal is analog, the BIM must convert it to the Pulse Code Modulation (PCM) format used in the TDM busing scheme. Before the analog receive audio is processed in the A/D circuitry, it is first routed into the Digital Level Memory (DLM) circuit block. This block provides special level conditioning to the analog signal. Similar circuit blocks are located on various modules throughout the CENTRACOM system. The DLM circuitry is discussed in the DLM Audio Processing paragraph. The analog audio output of the DLM (Receive Audio) is routed to the +TX input of the CODEC (U16-3), where it is converted into the PCM format. Aside from the A/D and D/ A converters, U16 also contains the anti-aliasing filters required to avoid degradation of the signal upon reconstruction. To ensure that the digitized audio is placed in the proper slot on the TDM bus, U16 is controlled by Time Slot Assigner (TSAC) U5. Eight bits of digital audio are clocked out of the TDD output of U16-11 when a logic high is received at the Transmit Data Enable pin, U16-10. This signal comes from U5 when the slot assigned to the BIM occurs on the
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TDM bus. The TSAC is itself programmed by microprocessor U1 to sense the correct slot as selected by DIP switch S2 on the BIM. To stay synchronized with the TDM bus, the TSAC uses the A4 signal. This 7.75 kHz signal is generated on the system timer module and bused throughout the system. 7.75 kHz is the period of one frame on the TDM bus. A falling edge on the A4 signal indicates the start of a new frame. The A4 signal enters the BIM at card edge connector pin 92 and is latched into U15A. On the rising edge of the CLK signal, A4 is clocked through U15A, allowing the complement A4 to appear at the Q output (pin 2). This signal is presented to the FSR and FST inputs of the TSAC (pins 10 and 9, respectively). The rising edge of CLK also sets U15B, resulting in a logic high at the Q output (U15B-13). This pulse is used as the clock signal for the CODEC and TSAC, entering those chips at the leads labeled RDC and TDC (pins 13 and 12 on the CODEC, pins 15 and 12 on the TSAC). Since the delays in U15A and U15B are essentially equal (approximately one clock cycle), the CLK and A4 signals arrive at the CODEC and TSAC at virtually the same time. When CLK goes low, the set condition on U15B is removed and the flip-flop is reset by a pullup on the reset lead. The result is that the Q output of U15B follows the CLK signal with a slight propagation delay through U15B. Whenever a rising edge occurs on the A4 line, the TSAC assumes that the next eight bits are the contents of slot 0 in the TDM frame. In reality, due to the manner in which the signal is generated on the system timer module, the A4 signal is two clock periods ahead of the data on the TDM bus. After the A4 signal is clocked through U15A, however, it is only one bit ahead of data on the TDM bus. At this point, the digital audio from the CODEC is one clock cycle ahead of the TDM bus. When the TSAC recognizes that the correct slot is present on the TDM bus, the TSAC TXE output (Transmit Enable, U5-14) goes high, allowing CODEC U16 to serially clock PCM-encoded audio out of its TDD output (U16-11). Since A4 is still one clock cycle behind the digital audio, that data is latched into U14 through the D4 input. The synchronized output is applied to three-state buffer U33A. On the next rising edge of CLK, a logic low is clocked to the D5 input of U14 (pin 15). This pulse enables U33D, allowing the output at Q4 (eight bits of digital audio) to be clocked onto the TDM slot that the module has been assigned to.
Transmit audio
In order to perform the transmit function, the BIM must be capable of accessing any slot on any one of the three TDM buses. It must then convert that data to an analog voltage and send it over phone lines to a base station. Unlike other modules in the system where the board is jumpered to receive one of the TDM buses, all three of these lines enter the BIM (card edge connector pins 73, 77 and 81). A transmission is initiated when microprocessor U1 receives a data packet from the operator position, instructing it to transmit the audio contained in a certain slot on one of the three TDM buses. In order to select the proper slot, the microprocessor writes to the TSAC, programming it to place a logic high on its RXE lead (pin 13) when the appropriate time slot occurs. This pulse is passed through latch U26, ultimately reaching the RCE input of CODEC U16 (pin 14) from the Q3 output of U26.
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To select the proper TDM bus, the microprocessor produces two control signals, MBE0 and MBE1. These signals are applied to the A and B address inputs of U27, a 4-channel multiplexer (pins 14 and 2). The digital data on the three TDM buses, as well as the CT (Companded Tones) signal, are continuously latched into U28. Depending on the address contained in the control signals, either MB1, MB2, MB3, or CT is selected by U27. The appropriate data exits the multiplexer from the X output (pin 7) and is presented to the RDD input of the CODEC to be converted to an analog voltage and sent to the base station for transmission. As an example, assume that the module is to transmit slot 21 from TDM bus 2 (MB2). The microprocessor programs the TSAC to put out an RXE signal when slot 21 comes around. It also sets bits MBE0 to 1 and MBE1 to 0, to present the control inputs of U27 a binary address of 10 (or decimal 2). This address allows the digitized audio from MB2 (TDM bus 2) to appear at the X output of U27. After processing in the CODEC, the analog audio signal is routed to the lowpass filter hybrid (Z4) before going into the line driver circuit and out onto the telephone lines to the base station.
DLM audio processing

The audio signals received from the base station are passed through phone lines to the CEB and are first processed by the BIM. These signals appear at card edge pins 57-60 and are transformer-coupled into the Digital Level Memory (DLM) circuits. The DLM provides two main functions:
p p
Adjusts the gain of the DLM circuit so that there is a constant audio output level of 0 dBm at Z2-10 whenever voice audio at transformer T1 or T2 is -25 to +10 dBm, which is selected by JU1 and JU2 Holds the gain of the DLM hybrid Z2 at the level set by the last voice input signal that was present just prior to a pause in the voice input signal
During normal voice operation, audio mute gate Q201 is on. Input voice audio is applied to the DLM gain hybrid Z2-4. A feedback amplifier inside the Z1 hybrid adjusts the gain to provide a constant audio output of 0 dBm at Z2-10. For systems using separate wire pairs for transmit and receive audio, transmit audio leaves the board at card edge connector pins 57 and 58. Receive audio enters the BIM at card edge connector pins 59 and 60. In this case, receive audio is buffered by U206B, passed by FET Q203, and is summed into Z2 at pin 5. The AGC circuit connected between Z2-1 and -2 has fast attack and slow release times. AGC-controlled audio is applied to DLM comparator hybrid Z3-10, where it is compared to a noise signal (16 kHz). The output of Z3-8 is always switching high and low. If the audio input signal is voice, the switching rate is less than 1200 Hz. If the audio input signal is noise, the signal rate is greater than 1280 Hz. Counter U205 is reset (by LCLK = 80 Hz) every 12.5 milliseconds. If voice is present in the audio channel, U205 does not reach full count before reset and the output (U205-10) remains low. If noise is present in the audio channel, U205 does reach full count before reset and the output at U205-11 goes high. U205-11 output is clocked into U203 and provides a voice noise indication at U203 Q output.
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During voice pauses, Z3-16 goes high, indicating noise is present in the audio channel. This causes C235 to charge up, which, through NOR gate U31, turns the squelch gate (Q212) off to mute the audio going to the speaker. A high on Z3-16 also causes the Q output (U203-12) to go low. This enables a counter located on the DLM R-2R hybrid (Z1) to begin counting up. The count is converted to an analog voltage ramp at Z1-10. The ramp voltage increases as the counter increases. This voltage is applied to Z3-4 and is compared to the DLM gain hybrid control voltage applied to Z3-3. When the voltages are equal, the output of a comparator on Z3 changes state, causing Z3-7 to go high, disabling the counter on Z1. This latches the gain setting of the DLM gain hybrid (Z2) to the level set by the last voice input signal that was present just prior to the pause. Test tones are periodically looped through the DLM circuitry to verify audio path integrity. When a test is to be performed, the microprocessor outputs a 2W MUTE and a 4W MUTE signal. This turns off gates Q201 and Q203 to prevent 2-wire and 4-wire receive audio from interfering with the test tone. The microprocessor also causes the DLM HOLD signal to go low during test tones. This is done so that the tone test does not inadvertently cause a change in the gain setting that was latched when the last voice signal was present. The test tones are gated into Z2-5, and are routed from Z2-10 to other circuitry on the BIM. The DLM HOLD signal also causes gate Q212 to turn on, allowing the test tones to reach the CODEC (U16). Whenever voice is present in the audio channel, Z3-16 is pulled low and U203 is reset. The low on Z3-16 of causes C235 to discharge, which causes squelch gate Q212 to turn on, allowing audio to reach the CODEC. Reset of U203 causes Q208 to turn on, making U206-14 go high, turning on Q207, causing CALL to go low. This low signal is detected by the microprocessor, which in turn sends a message to the Console Operator Interface Module (COIM). The COIM then instructs the radio control board to generate the appropriate call indicator display at the operator position. When the voice stops, Q208 turns off, and capacitor C213 begins to charge. When the inverting input to U206 becomes sufficiently high, U206 output goes low and the call indication display stops. Jumpers JU5 and JU6 allow various call indication delays to be used. The output of the DLM circuit is routed to the CODEC (coding/decoding) integrated circuit, which converts the analog audio to a Pulse Code Modulation (PCM) format and provides the anti-aliasing filters required for accurate replication.
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The MC6803 microprocessor and its support circuits have three major functions on the BIM:
p p p
Control logic generation for other BIM subcircuits System data bus access control Interpretation of input signals
The microprocessor system includes microprocessor U1; 16k X 8 EPROM U4 (which contains the control program for the microprocessor); octal transparent latch U2; data bus buffer U35; octal latches U7 and U32; address decoder U3; and 32k x 8 RAM U34. Octal latch U2 captures the lower eight address bits present on the data bus during the first half of each microprocessor machine cycle. These address bits are latched in to U2 by an Address Strobe signal (AS, pin 39) from the microprocessor. The data bus then serves as a true data bus for the remainder of the machine cycle. Address decoder U3 provides a logic low on one of eight outputs, depending upon the address the microprocessor is currently outputting to the address bus. This enables the microprocessor to select devices by merely outputting the appropriate device address. The address decoder provides eight control signals for device selection and control. These control signals are discussed further in subsequent paragraphs. Data bus transceiver U35 provides extra drive for the microprocessor data bus, compensating for loading due to the large number of devices connected to the data bus. The outputs of latch U32 are controlled by the microprocessor and are used to enable functions in various subcircuits of the board. The functions controlled by these outputs are:
p p p p p p
High guard enable and guard tone enable in tone control systems Mute of 2-wire receive audio and mute of transmit audio Enable of the dc generator board (in dc control systems) Disabling of the DLM activity checker circuit Control of test tone circuitry Muting of 4-wire receive audio
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Microprocessor reset and watchdog timer

The watchdog timer consists of binary counters U18A and B and associated components. This circuit provides a reset of the microprocessor during power up, and then monitors activity on one of the microprocessors outputs. If the watchdog does not periodically sense activity on this output, it attempts to reset the microprocessor. If the microprocessor is successfully reset, operation continues as normal. If the microprocessor does not reset properly, the module is three-stated and isolated from the system buses. When power is first applied to the BIM, U18A and B both power up randomly. If U18A, for example, powers up with the Q3 output low (pin 6), then the enable input at U18B (pin 10) is held low, preventing that counter from incrementing. Meanwhile, U18A begins to count LCLK pulses that occur at the E input (pin 2). (LCLK is a 77 Hz clock generated in the DLM circuitry.) When the count advances so that the Q3 output of U18A goes high, this counter is inhibited due to the appearance of that logic high on its clock input (pin 1). The same high signal appears at the enable input of U18B (pin 10), allowing that counter to begin incrementing. U18B continues to count up until its Q3 output goes high. When this occurs, both inputs to NAND gate U9C are high, causing the output to go low, turning transistor Q11 off. This causes RESET (U1-6) to go high, releasing the microprocessor from reset. In the event that U18A powers up with its Q3 output high, U18A is disabled due to the high appearing on its clock input. U18B increments at the LCLK rate until its Q3 output goes high, allowing the microprocessor to come out of reset as before. After being reset, if the microprocessor is performing correctly, it toggles the port 2 output (pin 10) approximately once every 10 ms. This square wave is inverted and level-shifted by U37-F and differentiated by capacitor C38, producing an impulse that resets U18A. Only negative transitions of the square wave from the microprocessor result in reset pulses. This means that U18A is reset about once every 20 ms. If it does not get reset, the Q3 output of U18A goes high after 103 ms. This enables U18B to begin counting. After counting for 103 ms, the Q3 output of U18B goes low. This causes RESET on the microprocessor to go low. Another 103 ms later, the Q3 output of U18B returns high, causing Q11 to turn off, allowing the microprocessor to come out of reset. If the microprocessor is not able to come out of reset, or if it is unable to reset U18A, the signal at U1-6 is a square wave with a period of about 200 ms. If the BIM is performing correctly, that RESET pin is at a steady 5 V level. The microprocessor is able to voluntarily power the BIM down by setting the signal labeled PD (U1-13) high. This signal appears at the cathode of CR26, turning on transistor Q7, but turning off Q9. This sequence causes the green LED (DS2) to turn off and the red LED (DS1) to turn on. Table 8-1 shows the LED status for various operating conditions of the BIM.
Table 8-1
BIM LED status operating conditions Condition Red LED

OFF ON FLASH FLASH OFF ON
Green LED
OFF OFF OFF OFF
Normal operation Microprocessor powerdown Insane microprocessor Fail ROM/RAM check Lose 12 V
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Chapter 8

Each BIM is assigned a fixed slot on the TDM bus. The BIM receives analog audio from the base station, digitizes it and inserts it into this slot. The slot is defined on the BIM by DIP switch S2, which is programmed for the correct binary word. Switches A0-A4 define a binary number corresponding to the TM slot into which the base station audio is to be inserted. Switches A5 and A6 select one of the three possible TDM buses. The microprocessor reads the DIP switch selection by writing address $7B on the address bus. This causes the Q3 output of address decoder U3 (an active low signal) to go low. The eight bits programmed by the DIP switch then appear on the data bus. After reading the data bus, the microprocessor sends the appropriate information to TSAC U5 through three outputs. The first two (pins 15 and 16) are connected to the CS (Chip Select-pin 4) and DI (Data Input-pin 3) leads of U5. The other signal exits from pin 9 of U1 and is labeled TCLK (TSAC Clock). This line connects to the CLK lead of the TSAC (pin 2). The information on these lines programs the TSAC to place the base station audio into the slot that has been selected by the DIP switch. For example, if the DIP switch contains the following bit pattern:
TDM bus number A7
1 (TBIM) 0 (Conven tional)
Slot number A4
1
A6
0
A5
0
A3
0
A2
1
A1
0
A0
1
The base station audio would then appear in slot number 21 (10101) of TDM bus number 1 (00).
Each board in the Central Electronics Bank that passes audio and/or data via the TDM bus structure requires a unique fixed slot number, e.g. TDM 05. The address is assigned using switch positions A0-A6 on the board TDM dip switch. In special cases involving the BIM and the COIM, dip switch position A7 (MSB) is used to define functionality such as on the BIM making it a Trunking BIM or "TBIM" and with the COIM whether Elite or Classic CRT console. Switch Position Open/Off (1) Closed/On (0) BIM TBIM BIM COIM Elite Classic
See the following page for examples.
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If A7 is set incorrectly it may result in: 1. Incomplete COIM to Op download. 2. Will remain in continuous Download loop.
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Data communications
Within the CENTRACOM Gold Series system, all of the modules are linked together by a data bus, controlled by the System Timer Module (STM). A detailed discussion of data bus arbitration and data packet protocol is presented in the System Timer Module chapter. The BIM can receive data from other modules in the system and write data to them.
Receive data
The information exchanged between the BIM and the other modules in the system enters and exits the BIM through the same card edge connector pin (pin 86-labeled DB). Data is continuously received here and passed to microprocessor U1 from serial-in/parallel-out shift register U11. Data from the bus is always available to the microprocessor at the parallel outputs. The movement of all data on the data bus is clocked by a signal generated on the system timer module labeled DC (Data Clock). This signal is active during slots 0 and 1 of the TDM bus. DC enters the BIM at card edge connector pin 97, and is clocked into latch U14 at the D1 input (pin 4) before being inverted and level-shifted by U17. DC is then used to clock data into U11. The bit stream on the data bus is gated through two Schmitt inverters (U12A and B) and downshifted by U17E before it is clocked into U11. After eight data clock cycles have occurred, a byte of data is available, in parallel, at the outputs of U11. These outputs are connected to the BIM internal data bus but are normally held in a three-state mode. When the microprocessor is to read in the data, it writes address $7D. This causes the MDR output of address decoder U3 (Q5-pin 10) to go low. This low is applied to the output enable pin of U11 (OE2-pin 3), allowing the outputs of U11 to be placed on the data bus and read by the microprocessor. The BIM microprocessor does not read the outputs of U11 unless it is first informed that there is information on the system data bus. It is alerted when DBSY (DATA BUSY) goes high. This bus is also controlled by the system timer module and is set high whenever a data source has been given control of the system data bus. DBSY connects to the BIM through card edge connector pin 94. When there is activity on the data bus, a high signal on that line is clocked into latch U14 at the D2 input (pin 6). The signal exits U14 at Q2 (pin 7), is inverted through NAND gate U9B and applied to one input of U31A. The other input to this gate is tied to the TS1 signal, so that the microprocessor NMI interrupts are masked when TS1 is low. If TS1 is low, as it normally is, DBSY passes through U9B and is inverted by U31A and U17F, signaling an interrupt, alerting the microprocessor that there is activity on the system data bus. The microprocessor is able to mask the DBSY interrupts by setting pin 20 high. This causes open collector gate U37E to pull low, grounding the input to U9B. The result is that the output of U9B is always high, in turn keeping the output of U31A low. This low is inverted and level shifted by U17F, forcing NMI high, disallowing DBSY interrupts.
DBSY interrupts are also not permitted when the module is three-stated because of a failure in some aspect of the circuitry. In this case, it is the TS1 signal at the input of U31A
which causes a high at the NMI input of the microprocessor. The net result is that a faulty BIM is not permitted access to the system data bus.
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Another microprocessor interrupt, IRQ (U1-5), synchronizes the microprocessor to the start of a new frame on the TDM bus. The microprocessor can externally mask these interrupts because there are occasions when the microprocessor must not be interrupted. If it must mask frame sync interrupts, the microprocessor writes to address $7C. This address is decoded by U3 and causes the Q4 output of that chip (pin 11) to go low. When this low is combined with a low on the R/W line (from U1-38), a logic low is clocked through to the Q output of U21A (pin 5). This signal is, in turn, applied to the D input of U21B (pin 12). At the start of the TDM frame, the system frame synchronization signal, A4, goes low. This negative transition is seen as a rising edge at the Q output of D flip-flop U15A (pin 2). This signal, which also synchronizes TSAC U5, is level-shifted to 5 V by U17D and U17E, and is used to clock U21B. As long as pin 12 of U21B is low, only logic highs are clocked out of the Q output of that chip and the microprocessor is not interrupted. To unmask frame sync interrupts, the microprocessor performs a read of address $7C. This again causes the Q4 output of U3 (pin 11) to go low. In this case, however, the D input of U21A is high (pin 2), clocking a high through to the Q output of U21A. A low at Q of U12B is then clocked to the IRQ lead on the transition of A4, interrupting the microprocessor. This interrupt is a signal to the microprocessor that new data is being clocked into U11. The microprocessor reads the data by accessing address $7D, initiating the sequence described above. When the Q5 output of U3 (pin 10) goes low at the end of the data loading sequence, it also resets U21B so that the interrupt to the microprocessor is cleared. Once the DBSY pulse is received and an NMI interrupt is initiated, the microprocessor allows the first three bytes of the 13-byte data packet to be latched onto its data bus on successive TDM frames. The third byte of the packet contains the address of the module the data is intended for (destination byte). The microprocessor then checks whether this address matches the one assigned to it, a binary number programmed into the DIP switch located on the module. There are special cases in which a data packet is addressed to all the modules and, though this packet does not contain the BIM address, the microprocessor recognizes and receives this data. If the data is intended for the BIM, the data is continuously placed, byte by byte, onto the module data bus, and synchronized by successive IRQ interrupts. If the packet is addressed to another module, the microprocessor masks frame sync IRQ and ignores the rest of the data packet. The sequence in which data is received proceeds as follows: First, DBSY goes high, indicating that there will be data on the data bus during the next 13 frames. The data happens to be coincident with time slots 0 and 1 on the TDM bus. DBSY causes an NMI interrupt in the microprocessor. The microprocessor immediately unmasks the frame sync interrupts IRQ and reads the data that has been clocked into U11. After reading the first three bytes of data, the microprocessor has determined whether the data is intended for the BIM. If the data is intended for another module, it masks the frame sync interrupts and goes on to other tasks. Otherwise, it leaves frame sync interrupts unmasked so that it is interrupted each time a new byte of data is ready to be released from the output of U11 onto the data bus.
Transmit data
When the BIM microprocessor needs to use the system data bus to transmit data packets, it must first be granted control of that line. While all modules in the system receive data at
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all times, only one module at a time may transmit data. All the modules that have access to the data bus share control of it according to their respective slot numbers. If a module assigned to slot 0 has control of the data bus, when it is finished sending data, the module assigned to slot 1 will get a chance to use the data bus. If it has not requested use of the data bus, the module assigned to slot 2 will get a chance. This continues to slot 31 and then starts over again at slot 0. The System Timer Module (STM) functions as the arbiter of the data bus. Data bus status is indicated by the busy bus (BSY), a line controlled by the STM. This bus is low when the data bus is not available and toggles at a rate of two pulses per slot when the data bus is available. These pulses occur at the first and fifth bits of each slot. This clocking constitutes a polling sequence for all boards in the system. There is one BSY bus corresponding to each of the three TDM buses. A board that is jumpered for TDM bus 1 will also be jumpered for BSY1. The same applies to TDM bus 2 and BSY2, and TDM bus 3 and BSY3. These lines enter the BIM at card edge connector pins 74, 78 and 82, with jumpers inserted according to which TDM bus the module is assigned to. The selected line is connected to the D0 input of U14 (pin 3). When the BIM requires use of the data bus, the microprocessor initiates a data request by writing address $7F on the module address bus. This address is decoded by U3, causing the Q7 output, DR, of that chip to go low. This low is inverted and level shifted to 12 V by U37D, clocking a low to the Q output of U20A. This low does not reach the next stage of the data request circuit until the SN signal goes low. This signal, derived from the TXE output of TSAC U5 through NOR inverter U19A, goes low whenever the time slot assigned to the module is valid on the TDM bus. The appearance SN enables three-state buffer U25C to apply DR (from U3-7) to the D input of U20B (pin 9). Meanwhile, the BSY signal, consisting of the pulses at bits one and five, is continuously clocked into latch U14. These pulses are then applied to the clock input of U20B (pin 11), clocking the low signal originating from U3-7. The net result is a high at the Q output of U20B (pin 12), which is then buffered by U25D and bus driver circuitry and placed on the DRDY (DATA READY) line, exiting the board at card edge connector pin 83. This signal is only allowed through to that line as SN goes low, (when the time slot assigned to the BIM occurs). The high-going transition on DRDY signals the data bus arbiter on the STM that the BIM requires access to the data bus. The arbiter then halts the polling sequence, forcing the BSY lines low, preventing any other modules from gaining access to the data bus. The Q output of U20B is also applied to the reset pin of U20A (pin 4), cancelling the data request by forcing the Q output of U20A high. At the same time that the microprocessor requests use of the data bus, it also writes out the first byte of its data packet, the start-of-text byte, to parallel-to-serial shift register U10 through the module data bus. U10 serially clocks data onto the system data bus only if the BIM has a data grant (the Q output of U20B is high). The microprocessor writes data into U10 by writing to location $7E. This address is decoded by U3, causing the Q6 (MDW) output of that chip (pin 9) to go low. This signal, together with the R/W signal from U1, appear at the inputs of NOR gate U22B. When both of these signals go low, a high appears at one input of U13C which, combined with a high pulse from the E clock (microprocessor synchronization clock), causes the PL input of U10 to go low, latching data from the microprocessor data bus into latch U10.
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When the BIM has a data grant (DG), buffer U25F is enabled by a low on the Q (DG) output of U20B (pin 13), allowing the data clock (DC) to reach U10. The data is then serially clocked onto the system data bus. The outgoing bit stream is up-shifted by U24A and passes through buffer U25E and bus driver circuitry on its way to the data bus. As with U25F, buffer U25E is enabled only when the BIM has a data grant. To this point, the microprocessor has issued a data bus request and has written the first byte of the data packet (the start-of-text byte) into U10. Even when the module has been granted control of the bus, the microprocessor must verify it. So, when the next frame sync interrupt occurs, the microprocessor latches the second byte of the packet (the data source byte in this case, its own slot address) into U10. In the next frame, the microprocessor latches the third byte of data into U10 (the destination address byte) and reads the data that was placed on the data bus during the previous frame (the source address byte). If that data contains its own slot address, the microprocessor knows that it has control of the data bus. It then continues to write data into U10 for 13 frames (a complete message packet). If the slot address contained in the second byte does not match that of the BIM, the microprocessor knows that it does not have control of the data bus. The microprocessor then re-latches the start-of-text byte into U10 and waits for the next DBSY to occur, repeating the process described above until it gains control. Once the microprocessor does gain control of the data bus, the module outputs data in 13 consecutive frames. During each frame when it has control, the module sends a DRDY pulse to the STM. Since the BIM has control of the data bus for 13 frames, 13 such pulses will be generated. These pulses are counted on the STM and after 13 pulses have been counted, the STM forces the busy bus to begin polling again. In order to prevent a module from capturing the data bus for consecutive data transmissions, during the fourteenth frame, the STM outputs only one pulse during the time slot assigned to the module which just finished transmitting data. This single pulse appears at the fifth bit of that slot. The consequence is that a rising edge will appear on the appropriate BSY bus, which will clock a logic high into U20B. This causes the Q output of that device to go low, removing the data grant from the module. Normal polling (two pulses per slot) then resumes during the next slot. The data transmission sequence proceeds as follows: First, the microprocessor generates a DRDY pulse which is routed to the STM, indicating that the BIM requires use of the data bus. DRDY is enabled only when the time slot assigned to the BIM occurs on the TDM bus. The microprocessor also latches the first byte of the data packet (start-of-text) into U10. Next, the STM halts the polling sequence on the BSY lines and a DBSY pulse initiates an NMI interrupt to the microprocessor, indicating that some activity is present on the data bus. The microprocessor then assumes it has control of the data bus, loading the second and third bytes of the packet into latch U10 in successive TDM frames. It then reads back the second byte (the source address byte) to verify that the data currently on the bus indeed originated from itself. If this address matches that programmed in the BIM DIP switch, the microprocessor continues to place the data packet on the bus until the message is complete (13 bytes). On the fourteenth byte, the data grant is removed from the board and normal polling resumes during the next slot on the TDM bus. If the address does not match, the BIM has not captured the bus and must continue the request sequence until it gains control.
8-14
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Auxiliary input/output
The BIM has six card edge connector pins (65-70) that are brought out to the termination panel and can be used as auxiliary inputs or outputs. The I/Os are connected to the BIM internal data bus through three-state buffer U6. The I/O lines are pulled up, making their normal state a logic high (5 V). The microprocessor periodically reads the I/O bits and sends their status over the system data bus to the main microprocessor on the COIM. The COIM microprocessor interprets the I/O bits and take the necessary actions. When reading the I/O bits, the BIM microprocessor also reads the status of the CALL and IRQ inputs to U8. The status of the CALL line is sent to the operator position to control a call indicator display. The IRQ information is used by the BIM microprocessor as a synchronizing signal when it is generating tones. The BIM microprocessor can write to the I/O lines as well. To accomplish this, it writes to latch U7. That data is applied to driver U29, which contains seven open-collector Darlington drivers. The driver outputs are connected to the I/O card edge connectors, giving the microprocessor the ability to pull the I/O lines low.
Tone generation
Sometimes the BIM must generate and transmit tones to the base station. The BIM microprocessor generates these tones by looking up the required data in a ROM table, which is based on the JU13 setting. This is done by placing the binary number, byte by byte, on the internal data bus and then routing it to the same circuits that process the digital audio signals for transmission to the base station. This data is labeled CT (Companded Tones) and appears at pin 2 of U24A. In order to allow CT to reach the D/A circuitry, the microprocessor initiates a tone enable procedure. For synchronization, it programs TSAC U5 to output a high RXE signal during slot 0 of the TDM bus. RXE is latched into U26 through the D0 input (pin 3). It exits through the Q0 output (pin 2) and is labeled DRXE . Whenever the BIM does not have control of the data bus, the DG signal is high, resulting in a high at the Y output of U27 (pin 9, labeled TONE ENA). This signal appears, together with DRXE, at the inputs of NAND gate U9D (pins 12 and 13). Whenever slot 0 occurs, the output of U9D (pin 11) goes low for one slot, enabling three-state gate U33E to pass CLK pulses through to the C2 input of U10 (pin 15). This allows eight bits of serial tone data to be clocked out of U10 at the system bit rate (2 MHz). The BIM is incapable of sending data on the system data bus at the same time that it is generating tones, since the output of U25E is three-stated. The tone data (CT) is level-shifted by U24A and clocked into latch U28, appearing there at the D3 input (pin 14). The microprocessor writes a binary 0 to multiplexer U27 through MBE0 and MBE1. This binary number appears at the A and B control lines of U27, instructing it to gate CT from latch U28 to the X output of the multiplexer (pin 7 of U27). From this point, the tone data is treated as normal transmit audio. When selected, the data is then applied to the CODEC. At the next occurrence of time slot 0, eight new bits are sent by the microprocessor to latch U10 and another sample of the tone is processed by the CODEC.
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Chapter 8 Theory
From the CODEC, the tones (now in analog form) are applied to low pass filter hybrid Z4. If the tones being generated are function tones, they are simply low-pass filtered and applied to the line driver hybrid. If the tones are to be transmitted by the base over the air, they must first be de-emphasized. This is done so that all tone frequencies are transmitted with the same deviation after being pre-emphasized by the base, ensuring that they will be received at the same level. To de-emphasize the tones, pin 17 of the microprocessor is set to logic 0. This low is inverted by U37C, (labeled DEMP ) and applied to pin 3 of the low pass filter hybrid. This high switches in a de-emphasis network in the hybrid, causing de-emphasized tones to be sent to the base station.
Guard tone gating and low pass filter hybrid

One important function of the BIM is to mix the transmit audio which it passes to the base station with the guard tone to key the transmit function. The guard tone is generated on the system timer module by dividing the main clock frequency of 3.9672 MHz down to 2175 Hz, by selecting JU13. This square wave is passed to the CEB interconnect board and routed throughout the system. The Guard Tone (labeled GT) enters the BIM at card edge connector pin 98 and appears at the input of NAND gate U9A (pin 1). The other input to this gate is derived from the Q1 output of latch U32 (pin 5). When the microprocessor sets this bit low, it is inverted and level shifted through U24E and labeled GTE (Guard Tone Enable), resulting in a logic low at U9A (pin 2). The 2175 Hz square wave is then applied to a resistor attenuator on the low pass filter hybrid, entering at pin 12. When applied to this lead, the signal appears at a point in the circuit that provides the degree of attenuation necessary to produce a guard tone level approximately 30 dB lower than the high guard tone level. This provides the low guard tone to the base station. When the microprocessor must send high guard tone, it sets the Q0 output of U32 (pin 2) high. This signal is level shifted and inverted by U24F and is labeled HGE (High Guard Enable). The resulting low appears as one input to U31B. The consequence is that the 2175 Hz is now applied to pin 11 of the low pass filter. This lead is connected to a point in the resistor network where the attenuation provided is 30 dB higher than the low guard tone level. At this time, both high guard and low guard tones are being generated but the high guard tone dominates. In either case, the tone is routed through a three-stage, five-pole low-pass filter inside the hybrid. It then appears at the input to the line driver hybrid (Z5-2, 3) to be placed on telephone lines connected to the base station.
8-16
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Three-state control
The BIM has specialized bus drivers for driving the DRDY bus, the data bus and the TDM bus. These drivers are designed to be fail-safe in that the board cannot short circuit any of them. To accomplish this goal, power and ground are switched to the drivers. When power and ground are switched off, the bus drivers are in a three-stated mode, and appear as a high impedance to the buses they drive. By virtue of the switched power and ground, the drivers are normally held in this high impedance state and are enabled only when it is required that they drive their respective buses. The driver consisting of Q21 and Q22 drives the DRDY bus; the driver consisting of Q19 and Q20 drives the system data bus; and the driver consisting of Q23 and Q24 drives the TDM bus. In the event of a board failure, the bus drivers are also held in three-state, so that the board is isolated from the rest of the system. The bus drivers are enabled through NOR gates U19A, U19B, and U19C. The output of U19A is passed through latch U14 (D5) where it is labeled SN. This signal goes low whenever the TDM slot assigned to the BIM becomes valid and is used to synchronize the functions of the BIM with the occurrence of the module time slot. This low transition appears also at the input of U19B (pin 9), causing the output of that gate to go high. This high is inverted by U19C which turns off transistor Q6, allowing Q18 and Q4 to turn on, feeding switched power to the bus drivers. The switched power in turn saturates Q3 and Q5, providing switched ground to the bus drivers. When the output of U19A returns high, the output of U19C goes high, turning on Q6. This turns Q18 and Q4 off, also shutting down Q3 and Q5 through CR34. During normal operation, transistor Q9 is saturated and the green LED is on. Should a failure occur, Q9 turns off. This allows one of the inputs of U19B (pin 8) to be pulled high, forcing a low at the output regardless of the state of the other input. The results is that the bus drivers are disabled and the BIM is three-stated off of the system buses.
Logging recorder output

The BIM supports an optional logging recorder that records transmit and receive audio for future playback. U30 sums transmit and receive audio and drives transformer T3, which places the audio on LOG OUT pins 63 and 64 of edge connector P1. This audio is passed to P2 on the CEB interconnect board for connection to the logging recorder. The BIM performs routine audio diagnostic testing during normal operation by periodically injecting 2175 Hz bursts into its audio paths. Q214 mutes these tones to prevent inappropriate logging recorder activation. Prior to the test tones being sent, the BIM microprocessor writes a word to octal latch U7. This causes U7-9 to go high (+5 V). This signal is passed to level shifter/inverter U29, and then to inverter U12. U12-8 drives the gate of an N-channel JFET (Q214) placed across the output and inverting terminals of operational amplifier U30. When the JFET gate voltage is positive relative to its source terminal, (as in the case when test tones are being muted) the JFET is on (has low resistance between source and drain). Low JFET resistance causes U30 to have low gain so that it cannot drive transformer T3, thus muting the test tones. Conversely, if the JFET gate voltage is negative relative to its source terminal, the JFET is off and audio passes to the logging recorder unimpeded.
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Chapter 8 Theory
Table 8-2
Pin definitions for BIM connector P2

Connected to/Function
Aux audio in from P1-62 or TXI from codec via JU19 Ground Spare bus 1 on motherboard from P1-72 (has a feed-thru) Aux IO5 from P1-69 2W DC negative input to T1-1 Aux IO6 from P1-70 2W DC positive input to T1-4 Processor port U1-8 2W audio from P1-58 2W audio from P1-57 4W audio from P1-60 4W audio from P1-59 Aux IO latch U7-19 (goes active during all tone tests) Processor serial port U1-16 (data to TSAC) Fused 15 volts Processor port U1-9 (TCLK signal to TSAC) Processor port U1-17 DLMed audio from z2 via JU28/29 Q4 output of data latch U32-12 5 volts
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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Chapter 8
Table 8-3
Integrated Circuit Description + 12 V

1 10 8 14 16 8 8 10 8 14 7 8 10 14 7 7 16 14 16 8 16 14 14 8 7 7 7 7 10 7 16 16 16 16 8 8 8 8 8 8 14 7 10 16 14 8 28 10 7 20 14 20 4 14 14 20 14 1 8 7 8 14 16 20 16 20 16
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36
Logic Ground
7 20 16 28
+5V
Analog Ground
Description
Microcomputer 3-State Octal Latch 3-Line to 8-line Decoder 16k X 8 EPROM Time Slot Assigner 3-State Hex Buffer Latch 3-State Hex Buffer Quad 2-input NAND Gate 8-Bit Shift Register 8-Bit Shift/Storage Register Hex Schmitt Trigger Quad 2-Input NAND Gate Hex D-Type Flip-Flop Dual D-Type Flip-Flop PCM Mono Circuit Hex Inverter Dual Binary Up Counter Quad 2-Input NOR Gate Dual D-Type Flip-Flop Dual D-Type Flip-Flop Quad 2-Input NOR Gate Octal Line Driver/Buffer Hex Inverter w/Open Collector Outputs 3-State Hex Buffer Hex D-Type Flip-Flop Dual 4-Channel Data Selector Hex D-Type Flip-Flop 5V to 15V Interface Driver Dual Operational Amplifier Quad 2-Input NOR Gate Latch 3-State Hex Buffer 16k X 8 RAM or 32k X 8 RAM Transceiver Triple 3-Input NAND Gate
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Chapter 8 Theory
Table 8-3
Integrated Circuit Description (continued) + 12 V

7 14 16 16 4 7 8 8 11
U37 U203 U204 U205 U206
Logic Ground
14
+5V
Analog Ground
Description
Hex Inverter Dual D-Type Flip-Flop 4-Bit Divide by N Counter Dual Binary Up Counter Quad Operational Amplifier
Table 8-4
Master BIM Jumper Table

Position
"2D" "2I" OUT -25 dBm (US) -35 dBm (international) -40 dBm 4-Wire receive sensitivity: "4D" "4I" OUT -25 dBm (US) -35 dBm (international) -40 dBm Normal operation Special applications only DLM/AGC operation Call LED dropout delay Call LED dropout delay Call LED activation (voice or activity) Normal operation Special applications only
Jumper
JU1
Function
2-Wire receive sensitivity:
JU2
JU3
IN OUT
JU4 JU5 JU6 JU7 JU8
See Table 8-5 See Table 8-6 See Table 8-6 See Table 8-7 OUT IN
JU9 JU10 JU11 JU12
SeeTable 8-5 -See Table 8-7
DLM/AGC operation Not used Call LED activation (voice or activity) 4-Wire receive termination:
IN OUT JU13 JU14 JU15 JU16 See Tables 8-8 and 8-9 See Table 8-10 See Table 8-11 See Table 8-11
600 ohm 10k ohm System clock and guard tone frequencies 2-Wire and 4-Wire muting 2-Wire transmit termination 2-Wire transmit termination
8-20
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Table 8-4

Position
IN OUT 1k ohm 10k ohm Normal operation Special applications only Not used Not used Not used 2-Wire transmit max output level: "D" "I" +11 dBm (US) - 10 dBm (international) Busy bus selection: "B1" "B2" "B3" Busy bus 1 Busy bus 2 Busy bus 3 Mux bus selection: "M1" "M2" "M3" Mux bus 1 Mux bus 2 Mux bus 3 2-Wire and 4-Wire muting 2-Wire and 4-Wire muting 2-Wire and 4-Wire muting Receive audio routing Receive audio routing Firmware PROM size selection: "8K" "16K" 8k 16k or 32k Not used Not used Receive squelch gate selection: "ENBL" "DSBL" Enabled Disabled Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only
Jumper
JU17
Function
Logging recorder output termination:
JU18
IN OUT
JU19 JU20 JU21 JU22
----
JU23
JU24
JU25 JU26 JU27 JU28 JU29 JU30
See Table 8-10 See Table 8-10 See Table 8-10 See Table 8-12 See Table 8-12
JU31 JU32 JU33
---
JU34
IN OUT
JU35
IN OUT
JU36
IN OUT
JU37
IN OUT
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Chapter 8 Theory
Table 8-4

Position
IN OUT Normal operation Special applications only
Jumper
JU38
Function
JU39
IN OUT
Normal operation Special applications only
JU40 "NORM" "TEST" JU41 "NORM" "TEST" JU42 "BIM" "SPI/DPI" JUA IN OUT JUB OUT IN JUC IN OUT
Codec (U16) loopback test: Normal operation Test mode Codec (U16) loopback test: Normal operation Test mode Logging recorder mute control: Board used as a BIM Board used as an SPI or DPI Normal operation Special applications only Normal operation Special applications only Normal operation Special applications only
JUD
OUT IN
Normal operation Special applications only Normal operation Special applications only
JUE
OUT IN
Table 8-5
DLM or AGC Operation

JU4 JU9
IN OUT DLM operation AGC operation
IN OUT
8-22
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Table 8-6
JU5 IN OUT OUT
Call LED Dropout Delay

JU6 IN IN OUT 0.6 second 1.1 second 1.9 second
Table 8-7
JU7 IN OUT
Call LED Activation

JU11 IN or OUT IN Call LED responds to voice Call LED responds to activity
Table 8-8
JU13
System Clock Frequencies

JU13 Position A2 IN IN OUT OUT System Timer Module Crystal Frequency 3.6450 MHz (note 1) 3.9672 MHz (notes 2 and 3) 3.9672 MHz (notes 2 and 3) 4.0960 MHz (note 4)
Position A3 OUT IN OUT IN
Note 1: International non-Embassy/non-SmartZone Operation Note 2: Either configuration may be used for 3.9672 MHz Note 3: US non-Embassy/non-SmartZone operation Note 4: Embassy/SmartZone operation
Table 8-9
JU13
Guard Tone Frequencies

JU13 Position A0 IN OUT OUT IN System Timer Module Guard Tone Frequency 2100 Hz 2175 Hz 2325 Hz 2432 Hz
Position A1 IN OUT IN OUT
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Chapter 8 Theory
Table 8-10
2-Wire and 4-Wire Receive Audio Muting JU25

OUT OUT IN OUT IN OUT
JU14
OUT OUT OUT
JU26
OUT OUT OUT
JU27
Normal non-signaling BIM (muting controlled by uP) Normal non-signaling BIM (muting controlled by uP) Full duplex signaling - 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). Simplex or half-duplex signaling - 2W and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). External high speed mute (simplex) - 2W muted when switched ground at pin 68 of card edge connector (Aux I/O 4). External high speed mute (duplex) - 2W and 4W muted when switched ground at pin 68 of card edge connector (Aux I/O 4). Full duplex signaling with parallel console - 2W muted when switched ground at pin 68 of card edge connector (Aux I/O 4) and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3). Signaling and external high speed mute - 2W and 4W muted when switched ground at pin 67 of card edge connector (Aux I/O 3) or when switched ground at pin 68 of card edge connector (Aux I/O 4). Allows BIM uP to mute both 2W and 4W with the 2W mute control line.
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
Table 8-11
2-Wire Transmit Termination

JU16
"IN" "IN" "OUT" 600 ohm 900 ohm High Impedance
JU15
"IN" "OUT" "OUT"
Table 8-12
JU28 IN IN OUT

JU29 IN OUT IN Normal Operation (audio routed from DLM directly to squelch gate) Normal Operation (audio routed from DLM directly to squelch gate) TBIM with Dual LOBL (audio routed from DLM through Dual LOBL to squelch gate)
8-24
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 8
Base Interface Module BLN6654D Overlay
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Chapter 8
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Chapter 8

(Sheet 1 of 4)
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Chapter 8
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Chapter 8

(Sheet 2 of 4)
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Chapter 8
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Chapter 8

(Sheet 3 of 4)
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Chapter 8
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Chapter 8

(Sheet 4 of 4)
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Chapter 8
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BLN6654D Parts List

Reference
Description
Reference
Description
capacitor, fixed:
C1 thru 12 C13 C14 C15 thru 17 C18 C19 C20 thru 24 C25,26 C27 thru 29 C30 C31 C32 C33 thru 35 C36 C37 C38 C39,40 C41 C42 C43,44 C45 C46,47 C48 C49 C50 C51 C52 C53 C54 thru 93 C95,96 C97 thru 99 C100 C201 C202 C203 C204 C205 C206,207 C208 C209,210 C212 C213 C215 C216,217 C219 2113741B45 2313748G06 2313748G14 2113741B45 2313748G04 2113740B73 2113741B45 0811051A12 2313748G22 2113740B73 2313748G04 0884637L22 0811051A12 2113741B37 2113741B45 2113740B73 2113740B34 2313748G14 2313748G04 2313748G14 2113740B34 2313748G14 2113740B69 2313748G06 2113740B42 2113741B45 2382028P02 2313748G04 2113741B45 2113741B45 2113740B49 2313748G14 2113740B73 0811051A11 2113741B45 0811051A09 2313748G04 0884549T01 0811051A11 2113741B45 2113741B45 2313748G06 2113740B49 2313748G06 2313748G09 CAP CHIP CL2 X7R REEL 0.01 UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP ELEC 22 UF 35V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ELEC 1.0 UF 50V 20% CAP CHIP REEL CL1 30% 1000PF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .068 5 63V CAP ELEC 100 UF 25V 20% CAP CHIP REEL CL11000PF30% 50V CAP ELEC 1.0 UF 50V 20% CAP MTLZ POLYEST .22UF 10% 100V CAP MTLZ POLYEST .068UF 5% 63V CAP CHIP CL2 X7R REEL 4700PF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP REEL CL1 1000PF 30% 50V CAP CHIP REEL CL1 24PF 30% 50V CAP ELEC 22 UF 35V 20% CAP ELEC 1.0 UF 50V 20% CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 24PF 50V CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 680 CAP ELEC 4.7 UF 50V 20% CAP CHIP REEL CL1 30% 51PF 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ALU 1.0 20% 50V CAP ELEC 1.0 UF 50V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP REEL CL1 30% 100PF 50V CAP ELEC 22 UF 35V 20% CAP CHIP REEL CL1 30% 1000PF 50V CAP MTLZ POLYEST .047 5% 63V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .022 5% 63V CAP ELEC 1.0 UF 50V 20% CAPACITOR MYLAR BOXED 2.2UF 10% 250V CAP MTLZ POLYEST .047 5% 63V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP CHIP REEL CL1 30% 100 CAP ELEC 4.7 UF 50V 20% CAP ELEC 10 UF 35V 20%
C220 C221,222 C223,224 C226 C228 C235
2313748G04 2313748G22 2113741B45 0811051A12 2313748G04 2313748G05
CAP ELEC 1.0 UF 50V 20% CAP ELEC 100 UF 25V 20% CAP CHIP CL2 X7R REEL 0.01UF 5% 50V CAP MTLZ POLYEST .068 5% 63V CAP ELEC 1.0 UF 50V 20% CAP ELEC 2.2 UF 50V 20%
diode: (see note)

CR1 thru 6 CR7 thru 14 CR15 CR16 thru 19 CR20 CR22 thru 27 CR30,31 CR32,33 CR34 thru 36 CR37 CR38 thru 42 CR43 thru 48 CR50 CR51 thru 53 CR202 CR204 CR205,206 CR207 CR209 CR211 thru 213 CR215 thru 218 CR219 CR220 4882290T02 4813833C10 4882290T01 4813832A18 4813833C10 4813833C10 4813833C10 4813832A33 4813833C10 4813833C07 4813833C10 4813832A33 4813832A33 4813833C10 4813832A26 4813832A26 4813833C10 4813833C07 4813833C10 4813833C10 4813833C10 4882290T02 4813833C10 DIODE SI HOT CARRIER*HSMS2802* DIODE GEN PUR .1A 70V MMBD6050 DIODE SI HOT CAR HSMS-2800-31 6.8V TRANS SUP P6SMB6.8AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE 20V TRANS SUP P6SMB20AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE DUAL 100V 5C COMM ANO DIODE GEN PUR .1A 70V MMBD6050 DIODE 20V TRANS SUP P6SMB20AT3 DIODE 20V TRANS SUP P6SMB20AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE 13V TRANS SUP P6SMB13AT3 DIODE 13V TRANS SUP P6SMB13AT3 DIODE GEN PUR .1A 70V MMBD6050 DIODE DUAL 100V 5C COMM ANO DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE GEN PUR .1A 70V MMBD6050 DIODE SI HOT CARRIER*HSMS2802* DIODE GEN PUR .1A 70V MMBD6050

fuse:
jumper:
JU3 thru 7 JU9 JU11 JU12 JU17,18 JU26 JU28,29 JU34 thru 39 JUA0 JUC0 0611009B23 0611009B23 0611077A01 0611009B23 0611009B23 0611009B23 0611009B23 0611077A01 0611009B23 0611009B23 RES JUMPER RES JUMPER RES CHIP JUMPER RES JUMPER RES JUMPER RES JUMPER RES JUMPER RES CHIP JUMPER RES JUMPER RES JUMPER
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Reference
Part Number
Description
Reference
Part Number
Description

Q1 Q2 Q3 thru 5 Q6 Q7 thru 9 Q10 Q11 Q12,13 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q201 Q202 Q203 Q204 Q205,206 Q207 Q208 Q209,210 Q211,212 Q213 Q214 4813824A12 4813823A04 4813824A12 4811043C02 4813824A12 4813824A06 4813824A12 4813824A18 4813824A18 4811043C02 4813824A09 4880141L03 4813824A09 4880141L03 4813824A09 4880141L03 4813823A04 4813824A18 4813823A04 4813824A18 4813824A11 4813824A12 4813824A18 4813824A12 4813823A04 4813824A18 4813823A04 XSTR NPN 40V .6A SW B=80 XSTR N-CH RF JFET MMBF5484LT1 XSTR NPN 40V .6A SW B=80 TSTR 48R00869570 A/I XSTR NPN 40V .6A SW B=80 XSTR NPN 30V DARLINGTON XSTR NPN 40V .6A SW B=80 XSTR PNP 40V .6A SW B=100 XSTR PNP 40V .6A SW B=100 TSTR 48R00869570 A/I XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR NPN 32V GENP B=100-250 TSTR PNP SOT23 LO PROFILE TAPE XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR NPN 40V .6A GENP B=75 XSTR NPN 40V .6A SW B=80 XSTR PNP 40V .6A SW B=100 XSTR NPN 40V .6A SW B=80 XSTR N-CH RF JFET MMBF5484LT1 XSTR PNP 40V .6A SW B=100 XSTR N-CH RF JFET MMBF5484LT1
resistor, fixed:
R1 thru 10 R17,18 R19 thru 24 R25,26 R27 R28 thru 35 R36 R37 R38 R39 thru 42 R43 R44,45 R46 R47 R48 R49 R50 R51 R52 thru 54 R55 R56 thru 59 R60 thru 64 R65 R66,67 R68 thru 76 R77 thru 80 R81 R82 thru 85 R86 R87 thru 90 R91 R92,93 R94 R95 thru 97 R98 R99 0611077A98 0611077A98 0611077B25 0611077B07 0611077A98 0611077A58 0611077A98 0611077A82 0611077B47 0611077B07 0611077A82 0611077B07 0611077A82 0611077B15 0611077A90 0611077B05 0611077A90 0611009A53 0611077B07 0611077A68 0611077A58 0611077A98 0611077A90 0611077B07 0611077B47 0611077A82 0611077B07 0611009A65 0611077A87 0611009A65 0611077A82 0611077A98 0611077A58 0611077A98 0611077A94 0611077A98 RES CHIP 10K 5%1/8W RES CHIP 10K 5% 1/8W RES CHIP 120K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 18K 5% 1/8W RES CHIP 4700 5% 1/8W RES FCF 1500 5% 1/4W RES CHIP 22K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES FCF 4700 5% 1/4W RES CHIP 3600 5% 1/8W RES FCF 4700 5% 1/W4 RES CHIP 2200 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 6800 5% 1/8W RES CHIP 10K 5% 1/8W
R100 R101 R102 R103 R104 R105 thru 109 R110 R111 R112 R113 R114 R115 thru 118 R119 R120 R121,122 R123 R124,125 R126 R127 R129,130 R131 R132 R133 R134 R135 R136 R137 thru 140 R141 R142,143 R144 thru 148 R149 R150 R151,152 R153 R154 thru 159 R160,161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 thru 179 R180 thru 185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195,196 R202 R203 R204 R205 R206 R207 R209 R210 R212 R214 R215
0611077A26 0611077A90 0611077B27 0611077A98 0611077B07 0611077B47 0611077B23 0611077A98 0611009A73 1883452F41 0611077B07 0611077A98 0611077A74 0611077A50 0611077B07 0611077A82 0611077B07 0611077A98 0611077A74 0611077A68 0611077A78 0611077A82 0611077A98 0611077A78 0611077A68 0611077A78 0611077A98 0611077A90 0611077B15 0611077A82 0611077A84 0611077B07 0611077A90 0611077B07 0611077A98 0611077A26 0611077A98 0611077A90 0611077A98 0611077B07 0611077A82 0611077B01 0611077A64 0611077A74 0611009A49 0611077A90 0611077A64 0611009A01 0611077A58 0611077A74 0611077A42 0611077A58 0611077A74 0611077A42 0611077A58 0611077A74 0611077A42 0611009A01 0611077A82 0611077B15 0611077B29 0611077B23 0611077B47 0611077B31 0611077A58 0611077B07 0611077A98 0611077B15 0611077B29
RES CHIP 10 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 150K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 10K 5% 1/8W RES FCF 10K 5% 1/4W POT BD CKT MOUNT A/I RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5%1/8W RES CHIP 100 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 2700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 10 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 12K 5% 1/8W RES CHIP 390 5% 1/8W RES CHIP 1000 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 4700 5% 1/8W RES CHIP 390 5% 1/8W RES FCF 10 5% 1/4W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47 5% 1/8W RES FCF 10 5% 1/4W RES CHIP 2200 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 180K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 180K 5% 1/8W
8-36
68P81095E50-A 1/18/01
Reference
Part Number
Description
Reference
Part Number
Description
R216 R217 R218 R219 R220 R222 R223 R224 R225 R226 R227 R228 R229 R230,231 R233 R234,235 R237 thru 239 R241 R243 thru 245 R247 R249 R250 R251 R252,253 R254 R255,256 R257,258 R259 R260 R261 R262 R263 R264 R265,266 R270 R271 R272 R273 R274 R276 R277 R278 R279 R300
0611077B23 0611077A82 0611077A74 0611077B47 0611077B23 0611077B23 0611077B07 0611077A98 0611077B37 0611077A98 0611077B37 0611077B25 0611077B47 0611077B07 0611077B37 0611077B31 0611077A98 0611077B23 0611077A98 0611077A68 0611077A56 0611077B31 0611077B15 0611077B13 0611077B29 0611077A98 0611077B07 0611077B15 0611077B47 0611077B07 0611077B11 0611077A80 0611077A74 0611009A49 0611077B47 0611077A98 0611077B07 0611077B47 0611077A98 0611077A74 0611077B23 0611077B15 0611077B47 0611077A58
RES CHIP 100K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 120K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 180 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 39K 5% 1/8W RES CHIP 180K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 33K 5% 1/8W RES CHIP 1800 5% 1/8W RES CHIP 1000 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 1 M 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 220 5% 1/8W
U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U203 U204 U205 U206
5184887K70 5184887K13 5113811D20 5184887K01 5184887K06 5184887K09 5184887K13 5184118K01 5184118K13 5184118K79 5184118K14 5184887K71 5184887K70 5184887K62 5184887K70 5183222M75 5184621K89 5184887K09 5184118K56 5184887K71 5184064F76 5184118K80 5184118K29 5184118K14 5184887K13 5184887K78 5184887K06 5113819D04
IC HEX D F/F_14174_ IC CMOS DUAL F/F __4013_ PCM CODEC/FLTR MONO-CIRCUIT IC CMOS HEX BUFFER __4049_ IC CMOS DUAL BIN CTR __4520__ IC CMOS QUAD NOR ___4001_ IC CMOS DUAL F/F __4013_ IC DL F/F D-TYPE _4LS74_ IC QUAD 2-INP NOR _4LS02_ IC OCT BFR 3-ST NONINV_4LS244_ IC TYPE 75LS05 IC HEX BFR 3-STATE NONINV_4503 IC HEX D F/F_14174_ IC DL 4 CHAN DATA SEL IC HEX D F/F_14174_ IC MONO AMP __1413_ IC DUAL OP AMP __3358_ IC CMOS QUAD NOR ___4001_ IC OCT D-TYPE F/F _4LS273_ IC HEX BFR 3-STATE NONINV_4503 IC CMOS SRAM (32KX8)_60256_ IC OCT BUS XCVR _4LS245_ IC 18K29 TTL LOGIC IC TYPE 75LS05 IC CMOS DUAL F/F __4013_ IC CTR BCD/4BIT BIN _4569_ IC CMOS DUAL BIN CTR __4520__ GEN PURPOSE 14 DIP MC3303P

VR1,2 VR3 5113816J03 5113816D01 IC 12V POSITIVE REG,100MA IC 5V POSITIVE RES. 1.0A
crystal: (see note)

Y1 4882611M15 4.9068 MHz CRYSTAL
network:
Z1 Z2 Z3 Z4 Z5 0182989R27 0182989R36 0182989R26 0182989R30 0182989R29 MODE HYBRID R 2R MODE HYBRID GAIN ALC MODE HYBRID CPTR ALC MODE HYBRID FLTR XMT MODE HYBRID DVR LINE
switch:
S1 S2 4084961N01 4083849F02 SW PB SPDT MOMENTARY SWITCH ROCKER DIP 8 POSTN
0310943J09 0982808R10 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 2683678T02 2880001R03 SCRTPG TT3X0.5X6 INTSTARPAN (2 used) SKT IC DIP 28 CONT (used with U4) SKT CONN (used with JU1) SKT CONN (used with JU2) SKT CONN (4 used with JU13) SKT CONN (used with JU15) SKT CONN (used with JU16) SKT CONN (used with JU22) SKT CONN (used with JU23) SKT CONN (used with JU24) SKT CONN (used with JU30) SKT CONN (used with JU33) SKT CONN (used with JU40) SKT CONN (used with JU41) SKT CONN (used with JU42) HEATSINK REGULATOR CON PCB HDR .1 GLD SR ST 3 POS (used with JU1)
transformer:
T1 T2,3 2583036L01 2584007C02 XFMR AF XMFR AF

U1 U2 U3 U5 U6 U7 U8 U9 U10 U11 U12 U13 5183625M66 5183539M01 5184118K34 5184704M45 5184887K71 5184118K56 5184118K27 5184887K08 5184118K35 5184810F64 5184887K52 5184118K06 IC BI IC 39M01 TTL LOGIC IC DCDR 3-TO-8 LINE _4LS138_ IC CMOS DGTL __14416_ IC HEX BFR 3-STATE NONINV_4503 IC OCT D-TYPE F/F _4LS273_ IC TYPE 74LS367 IC CMOS QUAD NAND __4011_ IC SHIFT RGTR 8-BIT _4LS165_ IC 8BIT SHIFT RGTR _4LS229_ IC MC14584BCP IC 74LS00 TTL LOGIC
68P81095E50-A 1/18/01
8-37
Reference
Part Number
Description
Reference
Part Number
Description
2880001R03 2880001R03 2880001R03 2880001R03
CON PCB HDR .1 GLD SR ST 3 POS (used with JU2) CON PCB HDR .1 GLD SR ST 3 POS (used with JU15) CON PCB HDR .1 GLD SR ST 3 POS (used with JU16) CON PCB HDR .1 GLD SR ST 3 POS (used with JU22)
2880001R03 2880001R03 2880001R03 2880001R03 2880001R03 2880001S03 2880001S03 2880001S04 2883290P04 5583323P01
CON PCB HDR .1 GLD SR ST 3 POS (used with JU30) CON PCB HDR .1 GLD SR ST 3 POS (used with JU33) CON PCB HDR .1 GLD SR ST 3 POS (used with JU40) CON PCB HDR .1 GLD SR ST 3 POS (used with JU41) CON PCB HDR .1 GLD SR ST 3 POS (used with JU42) CON PCB HDR 1 GOLD DR ST 6 POS (used with JU23) CON PCB HDR 1 GOLD DR ST 6 POS (used with JU24) CON PCB HDR 1 GOLD DR ST 8 POS (used with JU13) PLUG HEADER 20 PIN HNDL CKT BD
NOTE: For optimum performance, diodes, transistors, integrated circuits,

and crystals must be ordered by Motorola part number.
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68P81095E50-A 1/18/01
9 9 Dual Receive
Interface Module
About this chapter

Section
Introduction Theory BLN6656C Parts List
Page
9-2 9-3 9-21
Models covered
The following models of the Dual Receive (DR) Module are covered in this chapter:
Model
BLN6656C Dual Receive Module
Description

68P 81 095E 5 0-A 11/30/ 2000- U P
9-1
Chapter 9
Dual Receive Interface Module
Introduction
Introduction
The DR module provides separate receive audio processing for two distinct audio lines. The module provides the interface between the analog audio from two base station receive channels and the Time Division Multiplexed (TDM) bus within the console. The module consists of two major parts: p p Audio processing circuitry that digitizes the analog signals from the phone lines and inserts them into the correct slot on the TDM bus Microprocessor-controlled circuitry that is the interface to the system data (serial) communication bus
9-2
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Chapter 9
Dual Receive Interface Module Theory
Theory
The following topics are discussed in the theory: p p p p p p p p p p p Audio Processing Microprocessor System Module address programming Microprocessor watchdog timer and reset sequence Transmit data Receive data Bus driver/three-state control Module self test feature Auxiliary inputs DR module jumpering DR signal names
Audio processing
The audio signals received from the base station are passed through phone lines to the CEB and are first processed by the dual receive interface module. These signals appear at card edge pins 57- 60 and are transformer-coupled into separate Digital Level Memory (DLM) circuits. The DLM circuitry consists primarily of three hybrid circuits for each channel, which are supported by a number of discrete on-board components. Both CH 1 and CH 2 are identical in function; only CH 1 is described herein. The DLM provides two main functions: p p Adjusts the gain of the DLM circuit so that there is a constant audio output level of 0 dBm at Z1-11 whenever voice audio at transformer T1 is -25 to +10 dBm. Holds the gain of the DLM hybrid Z1 at the level set by the last voice input signal sensed prior to a pause.
During normal voice operation, audio mute gate Q103 is on. Input voice audio is applied to the DLM gain hybrid Z1-4. A feedback amplifier inside the Z1 hybrid adjusts the gain to provide a constant audio output of 0 dBm at Z1-11. An AGC circuit with fast attack and slow release times is connected between Z1 pins 1 and 2. AGC-controlled audio is applied to DLM comparator hybrid Z5-12, where it is compared to a noise signal of 16 kHz. The output of Z5-10 is always switching high and low. If the audio input signal is voice, then the switching rate of the signal at Z5-10 is less than 1200 Hz. If the audio input signal is noise, the signal rate is greater than 1280 Hz. Counter U27 is reset ( by LCLK = 80 Hz) every 12.5 milliseconds. If voice is present in the audio channel, U27 does not reach full count before reset and the output (U27-10) remains low. If noise is present in the audio
68P 81095E 50-A 11/30/ 2000
9-3
Chapter 9 Theory
channel, U27 reaches full count before reset and the output at U27-11 goes high. The U27-11 output is clocked into U29A, and provides a voice noise indication at the U29A Q output. During voice pauses, pin 20 of Z3 goes high, indicating noise is present on the audio channel. This causes C117 to charge and turn off the squelch gate (Q20) via inverter U12A to mute the speaker audio. A high on pin 20 of Z3 also causes the U29A Q output (pin 1) to go low. This enables a counter located on the DLM R-2R Hybrid (Z3) to begin counting up. The count is converted to an analog voltage ramp at Z3-13. The ramp voltage increases as the counter increases. This voltage is applied to Z5-6 and is compared to the DLM Gain Hybrid control voltage applied to Z5-5. When the voltages are equal, the output of a comparator on Z5 changes state, causing Z5-9 to go high, disabling the counter on Z3. This latches the gain setting of the DLM Gain Hybrid (Z1) to the level set by the last voice input signal that was present just prior to the pause. During tone tests, test tones are periodically looped through the DLM circuitry to verify audio path integrity. When a test is to be performed, the microprocessor applies a high level MUTE signal to the base of Q16. This turns off audio gates Q103 (Channel 1) and Q203 (Channel 2) to prevent channel audio from interfering with the test tones. The MUTE signal also causes Z5-16 to go low. This causes the Z5 output (pin 20) to go high and set the U29A Q output (pin 1) low. This is done so that the test tone does not use a change in the gain setting which was latched by the last voice signal. The test tones are routed to Z1-6 (for Channel 1) and routed from output Z1-11 to other circuitry on the dual receive module. The low at Z5-16 also causes squelch gate Q20 to turn on, allowing the test tone to reach the CODEC (coding/decoding) (U16). Channel 2 operation is identical. Whenever voice is present on the audio channel, pin 20 of Z3 goes low and U29A is reset. The low on Z3-20 causes C117 to discharge, which in turn causes squelch Q20 to turn on, allowing audio to reach the CODEC (U16). The reset of U29A causes Q104 to turn on, making U30C-8 output to go high, turning on Q102, causing CALL1 to go low. This low signal is detected by the microprocessor, which sends a message to the COIM. The COIM then instructs the radio control board to provide a call indication display at the operator console. When the voice stops, Q104 turns off, and capacitor C109 begins to charge. When the inverting input to U30C becomes sufficiently high, U30C output goes low and the call indication at the console is deactivated. Jumpers JU18-JU22 allow various call light dropout delays to be used. The output of each DLM circuit is routed to a CODEC integrated circuit, which not only converts the analog audio to a Pulse Code Modulation (PCM) format, but provides the anti-aliasing filters required for accurate replication. The RECEIVE AUDIO 1 signal is processed by DLM 1 and appears at pin 3 of CODEC-filter U16. The output of DLM 2 (RECEIVE AUDIO 2) is converted by CODEC-filter U17 (also at pin 3). After performing an A/D conversion of the audio, the CODECs then insert the digital audio into the correct slots on the TDM bus. Eight bits of digital audio are clocked serially out of each CODEC when their respective TDE inputs go high (Transmit Data Enable-pin 10). These enabling signals come from U5, the Time Slot Assigner Circuit (TSAC) and are labeled RXE and TXE. In order to enable the CODECs at the appropriate times, the TSAC must stay synchronized with the TDM bus. This synchronization is accomplished by using signal A4, a 7.75 kHz signal generated by the system timer module that enters this board at card edge pin 92. The analog audio is sampled at the rate 7.75 kHz and, as such, is the
9-4
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Chapter 9
frequency at which one frame passes on the TDM bus. A falling edge on the A4 signal indicates the start of a new frame, but since the TSAC identifies the beginning of a frame with a rising edge, the signal is latched into D type flip-flop U15A and the Q output is fed into the TSAC. Because of the manner in which A4 is generated on the system timer module, this signal is actually two clock periods ahead of the data on the TDM bus. After it is latched into U15, A4 is only one bit ahead. When the TSAC recognizes that the correct slot is present on the TDM bus, the RXE output (pin 13) goes high, allowing CODEC U16 to output a digitized audio stream from the TDD output (pin 11). At this point, since A4 is still one bit ahead of the TDM bus, the data from the CODEC is also out of synchronization. The digital audio is therefore presented to latch U14 (pin 13), where it is delayed one clock cycle. On the next clock period, a logic low is clocked to pin 14 of U14 by NOR gate U19-10, turning on three-state buffer U25A, and allowing eight bits of digital audio to be clocked onto the TDM bus. After RXE has been high for eight bits (channel 1 digitized audio has been clocked onto the TDM bus), the TXE line from the TSAC goes high, enabling U17. Pin 14 of U14 stays low, keeping three-state buffer U25A enabled. CODEC U17 clocks eight bits of data (channel 2 audio) onto the TDM bus by the same method. The TDD outputs of the CODECs are three-stated unless their TDE signals (pins 10) are high. This allows the TDD outputs to be tied together, since their respective TDE pins are never high at the same time. In this manner, the CODECs are enabled during consecutive slot times, allowing the module to process two separate channels.
The microprocessor system is comprised of a microprocessor (U1), an octal latch (U2), an address decoder (U3), and a read-only memory (U4). Also included in this circuit block is a RAM (U32), and a data bus buffer (U33). The microprocessor provides the control functions that are necessary for the proper operation of the module and for communication with the rest of the system. ROM U4 contains the operating program for the microprocessor. The octal latch (U2) is required to capture the lower eight address bits, which are present on the microprocessor data bus during the first half of each microprocessor machine cycle. These address bits are latched into address decoder U3 by address strobe (pin 39) from the microprocessor. The data bus then serves as a true data bus for the remainder of the cycle. The address decoder (U3) provides a logic low on 1 of 8 outputs, depending on which address the microprocessor outputs onto the address bus. In this way, control signals are sent to various parts of the board to control functions at the appropriate times. The functions of these control signals are explained in detail in the following sections.

The two receive channels of the DR module are always assigned to adjacent slots on the TDM bus. Furthermore, since the pair of slots must always begin on an even slot number, the module must be addressed to an even number.
68P 81095E 50-A 11/30/ 2000
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Chapter 9 Theory
The first receive slot is contained in the address programmed on the module DIP switch. The second is the next slot that occurs on the TDM bus. A logic high is programmed by opening a switch, while a logic low is programmed by closing one. Bits A5 and A6 of the DIP switch select one of the three possible TDM buses to be accessed by this module. The microprocessor reads the DIP switch selection by outputting hex address 7B onto the address bus. This causes the ADRRD output line of address decoder U3 (pin 12) go low, allowing the programmed address to appear on the microprocessor data bus. After reading the data bus, the microprocessor sends the module address information to TSAC U5 via three port outputs labeled CS (Chip Select), DI (Data Input), and TCLK (TSAC Clock). This information informs the TSAC that it is to place channel 1 receive audio into the slot, which has been programmed on the DIP switch, and channel 2 receive audio into the next slot. For example, if the DIP switch is programmed with the following bit pattern, Channel 1 receive audio is placed into slot 8, and channel 2 receive audio is placed into slot 9 on the first TDM bus.
Not Used A7
0
TDM Bus # A6
0
Slot Number A4
0
A5
0
A3
1
A2
0
A1
0
A0
0
Microprocessor watchdog timer and reset sequence

To ensure proper operation of the DR module, a watchdog circuit monitors the microprocessor. This circuit, comprised of binary counters U18A and U18B, provides a reset for the microprocessor during power-up and monitors activity on one of the microprocessor outputs. If it does not periodically sense activity on this output, it attempts to reset the microprocessor. If the microprocessor is successfully reset, operation continues as normal. If it does not reset properly, the module is three-stated and isolated from the system buses. When the board is plugged in, U18A powers up randomly while U18B powers up reset. If, for example, U18A powers up with the Q3 output (pin 6) low, that signal is applied to the enable input of U18B (pin 10), disabling it. Meanwhile, U18A begins to count LCLK pulses which occur at U18-2. LCLK is an 80 Hz clock that is generated in the Digital Level Memory (DLM). U18A increments until the Q3 output goes high, when, due to a logic high on its clock input, it is inhibited. The same high level on Q3 enables U18B, which begins counting until its Q3 output (pin 14) goes high. At this point, pin 1 of NOR gate U31 is high. This signal causes the output of U31 to go low, releasing the microprocessor from reset. On the other hand, if U18A powers up with the Q3 output high, it is disabled due to a logic high on its clock input. U18B increments until its Q3 output goes high, allowing the microprocessor to come out of reset as before. After being reset, if the microprocessor is performing correctly, port 2 output pin 10 toggles low approximately once every 10 ms. This square wave is level-shifted by U24B and differentiated by C32 and R315, providing a high going pulse that resets U18A. Since only negative transitions of the square wave from the microprocessor result in reset pulses,
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U18A is reset about once every 20 ms. If it does not get reset, the Q3 output of U18A goes high after 100 ms. This logic high enables U18B. After counting for 100 ms, U18Bs Q3 output goes low, causing RESET on the microprocessor (pin 6) to go low. After another 100 ms, the Q3 output of U18B returns high, causing transistor Q8 to turn off, allowing the microprocessor to come out of reset. In the event that the microprocessor is not able to come out of reset, or if it is unable to reset U18A, the signal on pin 6 of the microprocessor (RESET) is a square wave with a period of about 200 ms. If the module is performing correctly, pin 6 of the microprocessor is at a steady 5 V level. The microprocessor is able to voluntarily power the module down by placing a logic high on PD (pin 13). This switches on transistor Q6, which turns off Q9, causing the green LED to turn off. Q9 turning off also allows the high from U18-14 to turn Q10 on, turning the red LED on. Table 9-1 shows the LED status for various operating conditions of the DR module.
Table 9-1
DR module LED status operating conditions

Conditions Red LED
OFF ON FLASH FLASH ON OFF
Green LED
ON OFF OFF OFF OFF OFF
Normal operation Microprocessor powerdown Insane microprocessor Fail RAM/ROM Lose LCLK Lose 12 V
When the microprocessor comes out of reset, the logic states of pins 8, 9, and 10 of the microprocessor define the mode in which it operates. To power up in the normal operating mode, pins 8 and 10 must be low on the rising edge of the RESET pulse, and pin 9 must be high. This arrangement is accomplished by routing the RESET signal through diodes CR19 and CR21.
Transmit data
When the microprocessor needs to use the system data bus to transmit data packets, it must first be granted control of that line. All the modules in the CEB share access to the bus according to their respective slot numbers. When, for example, a module assigned to slot 1 has control of the system data bus, it transmits the data packet while all other modules stand idle. When the transmission is completed, the module assigned to slot 2 gets a chance to use the data bus. If it has not requested use of the system data bus, the module assigned to slot 3 gets a chance. This continues to slot 31 and then starts over again at slot 0. The use of the system data bus is arbitrated by the busy ( BSY) bus line, a line controlled by the system timer module. There is one BSY line corresponding to each of the three TDM buses. A board that is jumpered for TDM bus 1 will also be jumpered for BSY 1. The
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same correspondence exists between TDM bus 2 and BSY2, and between TDM bus 3 and BSY3. The busy bus and the arbitration circuitry is discussed in detail in the Theory section of Chapter 13 System Timer Module. In the event that the module requires use of the system data bus, microprocessor U1 initiates a data request by requesting hex address 7F through the address bus. This address is decoded by U3, causing its Q7 output (pin 7) to go low. The low appears on a line labeled DR. It is inverted by U24-B, level shifted to 12 V, and presented to the clock input of flip-flop U20A (pin 3). Every time the slot assigned to the module is valid on the TDM bus, the signal SN goes low, enabling U25D and allowing the DR signal to appear at the D input of U20B. Meanwhile, the BSY signal assigned to this module is continuously clocked into latch U14 at pin 3. Whenever the system data bus is not in use and the module slot is valid on the TDM bus, a rising edge is passed through U14 to the clock input of U20B (pin 11). If the module had requested use of the system data bus, then the D input of U20B would be low, making the Q output (pin 12) high. This output is then buffered by U25B and bus driver Z7 and appears as a high-going pulse on the DRDY (data ready) bus, signaling the system data bus arbiter on the system timer module to stop the polling sequence. The BSY bus goes low, preventing any other modules from gaining access to the system data bus. The Q output of U20B is fed back to the reset pin of U20A. This resets U20A, thus forcing the Q output to go low. When the microprocessor requests the use of the system data bus, it also writes out the start of text byte to shift register U10. This parallel-to-serial shift register clocks data onto the system data bus only if the module has a data grant; that is, if the Q output of U20B is high. The microprocessor writes to this latch by performing a write to hex location 7E, causing the Q9 lead on U3 (pin 9), which carries the signal labeled MDW, to go low. The MDW and the E signals (microprocessor clock) appear at the input of NOR gate U22 forcing a logic low at the PL input of U10 (pin 1), thereby latching data from the microprocessor data bus into U10. The data is clocked onto the system data bus by the data clock (DC) generated by the system timer module. This clock pulse appearing at card edge pin 97, is latched in U14 and inverted by U23B. The serial data from U10 is level shifted by U24A and applied to buffer U25C. U25C is enabled only when the module has a data grant (Q output U20B low). U25C is applied to driver Z7, which outputs the data to the system data bus. This data is buffered by U12B, C and U23A and applied to shift register U11. The data is clocked through U11, serial to parallel, by the DC signal via U14 onto the microprocessor data bus. Whenever a module has been given control of the system data bus, DBSY is high. DBSY is latched by U14, generating an interrupt signal at U1-4. This alerts the microprocessor that the system data bus is active. The microprocessor also unmasks the frame sync interrupt (IRQ). At this time, the microprocessor reads the microprocessor data bus which contains the system data bus data that is clocked through U11. The start of text byte data contains the slot address of the module sending data on the system data bus. If the microprocessor recognizes its module slot address when it reads its data bus, it knows that it has control of the system data bus. The microprocessor then continues to write data into U10 for 13 frames (a complete message packet). For details concerning data packet protocol, refer to the Theory section of Chapter 13 System Timer Module. If the slot address assigned to this module was not the last byte sent on the system data bus, it knows that it does not have control of the system data bus, and it re-latches the
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start-of-text byte into U10. It then waits for the next DBSY to occur and repeats the process described above until it gains control of the system data bus. Once it does gain control, and the microprocessor verifies this fact, the module sends data in 13 consecutive frames. During each frame when it has control of the system data bus, the module sends a DRDY pulse to the system timer. The DRDY pulse is generated by an ANDing (via U25B) the DG and SN signals. When the module has a data grant, DG is high for 13 frames. This signal appears at the input of U25B. In each frame, SN goes low for one slot and a logic high appears on the DRDY bus (through bus driver Z7) for the duration of the slot. Since the module has control of the data bus for 13 frames, 13 such pulses are generated. These pulses are counted on the system timer board. After 13 pulses have been counted, the system timer forces the busy bus to begin polling again. This means that a rising edge appears on the BSY bus, and clocks a logic 1 into U20B. This causes the Q output on U20B to go low, removing the data grant from the module.
Receive data
Though the system data bus is separate from the TDM bus, it operates synchronously with it. Information or instructions appear on the data bus at the same time slots 0 and 1 occur on the TDM bus. For the rest of the TDM frame, nothing appears on the data bus. During time slots 0 and 1, 8 bits are clocked onto the data bus at a 1 MHz rate by whichever module in the system currently has control. Although only one node at a time can use the system data bus, all nodes at all times can receive data from it. Each time a byte of data appears on the system data bus, it is clocked into shift register U11 by the data clock (DC). On the DR module, the data clock is latched into U14 before it is inverted and downshifted by U23B, and applied to the clock inputs of U10 and U11. The serial information from the system data bus is routed to Schmitt inverters U12B and U12C and is downshifted by U23A before appearing at the data input of shift register U11 (pin 11). When eight bits of data have been clocked into U11, it is available in parallel on the outputs of U11. These outputs are connected to the microprocessor data bus and are normally held in a three-state mode. When the microprocessor wishes to read in the data, it writes to hex address 7D. Decoded by decoder U3, this address causes the Q5 output (MDR pin 10) to go low. This signal is applied to the output enable pin of U11 (pin 3) and allows the parallel data to be placed on the microprocessor data bus. The microprocessor can now read in the data. The microprocessor does not read the outputs of U11, however, unless it knows that there is activity on the system data bus. It is alerted to system data bus activity when the DBSY signal goes high. This bus is brought high by the system timer module whenever a data source has been given control of the system data bus. The DBSY signal is clocked into latch U14 and applied to the input of inverter U31D. It is then gated through U31B, downshifted and inverted by U23C and applied to the NMI interrupt input of the microprocessor. This interrupt alerts the microprocessor that activity is about to begin on the data bus. If the microprocessor does not wish to monitor data activity, it has the ability to mask these interrupts by placing a logic high on pin 20. This signal gets inverted by open collector gate U24B and holds the input U31A low, regardless of the logic state of DBSY.
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This keeps NMI high, no matter what DBSY does, and the microprocessor does not get interrupted. Another interrupt, IRQ, is used to synchronize the microprocessor to the start of a frame on the TDM bus. Since data on the system data bus is synchronous with slots 0 and 1 on the TDM bus, valid data is placed in U11 soon after a start of frame interrupt occurs. The IRQ interrupt signals the microprocessor that it can read latch U11 and get a valid byte of data. The signal is latched and inverted through U23D and U23E before clocking an interrupt pulse through flip-flop U21B. The frame sync interrupts can be controlled by the microprocessor by reading or writing to latch U21A. If frame sync interrupts are to be masked, the microprocessor writes to hex location 7C, causing a low-going pulse to appear at the Q4 output of decoder U3 (pin 11). Labeled FSM, this signal delivers a logic low to NOR gate U22, providing a high pulse to the clock input of U21A (pin 3). When U21B is clocked, the Q output (pin 8) is always high, and no interrupts may occur. If frame sync interrupts are not to be masked, the microprocessor performs a read operation from latch U21A, causing a logic high to appear at the Q output of U21A (pin 5). When U21B is clocked at the start of a frame, a logic low is clocked to the Q output of U231B, providing a microprocessor interrupt. In response to this interrupt, the microprocessor reads hex address 7D, activating the Q5 output of U3 (MDR), allowing the release of the data from latch U11. At the same time, MDR resets latch U21B. This clears the frame synch interrupt, so that the microprocessor can be interrupted again at the start of the next frame.
Bus driver/three-state control

The complementary emitter follower bus drivers (B1, B2, & B3) on the DR module are held in a three-state mode until it is required that they drive their respective buses. B1 drives the data ready (DRDY) bus, B2 drives the TDM bus, and B3 drives the system data bus. Control signals RXE, TXE, and DG are used to turn on the bus drivers. The first two signals emanate from the Time Slot Assigner Circuit (TSAC) to allow the drivers to place digital audio into the appropriate time slot on the TDM bus. When the module has control of the system data bus, the DG signal enables the drivers to send DRDY pulses, requesting control of the system data bus and to transmit messages on it once access has been granted. NOR gate U19B normally has input pins 3 and 4 held low through saturated transistor Q9. When either TXE or RXE goes high, the output of NOR gate U19C goes low, switching the output of U19B to a logic high. Inverted at U19A, this signal turns transistor Q5 off but turns transistors Q2, Q3, Q4, and Q18 on, supplying power and ground to the bus drivers (B1-B3). Whenever RXE and TXE are low, and DG is high, U19B has a low output which is inverted by U19A, activating Q5. When this transistor is on, power and ground are disconnected from the bus drivers, placing them in a high impedance state. The Power Down (PD) output from microprocessor U1, can be used to disable the bus drivers if the module is malfunctioning. By placing a logic high on this control line, the microprocessor can cause transistor Q6 to become active, turning off Q9. This sequence causes the output of U19A to go low, switching off Q5, and disconnecting the power and ground to the bus drivers.
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three-state control guarantees the isolation of the module if there is a failure that could threaten the integrity of the TDM bus or of the system data bus. Two signals, THREE-STATE 1 (TS1) and THREE-STATE 2 (TS2), are used to disable the module. TS1 is an output of the watchdog timer circuit. When this signal goes high, it is an indication that the microprocessor is not operating properly. TS2 goes high when either TS1 is high, or when the microprocessor voluntarily powers down the module. If the watchdog circuit detects a failure, TS1 turns on, immediately disabling U31B and inhibiting DBSY interrupts from reaching the microprocessor. In this case, the DR module does not react to any activity on the system data bus. This signal also goes high during a power-up sequence, preventing interrupts from reaching the microprocessor while it is initializing its programs. The TS1 and PD signals are diode ORed into the base of Q6. By using an OR function, either signal may affect the LED status lights. If TS1 goes high, Q6 turns on, shutting down Q9 which, in turn, turns off the green LED. Also, the Q3 output of U18B (pin 14) toggles, flashing the red LED through R318 and Q10. If PD has gone high, the green LED again shuts off but the Q3 output of U18B simply goes high, keeping Q10 turned on, resulting in a steady red LED. When either PD or TS1 goes high, Q9 is off. Whenever Q9 is not active, pins 3 & 4 of NOR gate U19B are pulled high through R95. This particular point in the circuitry is labeled TS2. Whenever TS2 is high, it is an indication that the module is malfunctioning and should be isolated from the TDM and system data buses, ensuring that there is no disruption of the operation of other modules using these buses. Whenever TS2 is high, a number of things occur. First, since TS2 is related to TS1, the red LED turns on and the green LED turns off, indicating some problem on the board. Second, the output of U19A is forced low, preventing the SWA+ (Q4) and SWGND (Q2, Q3) transistors from turning on. With these transistors off, the bus drivers (B1-B3) are placed in a high impedance state. Next, the gate that removes U25A from its inhibit mode, U19C, is disabled so that no digital audio may reach the TDM bus. The closure of this path is actually redundant since driver B2 is already disabled. Finally, to prevent the module from obtaining a data grant, not only does TS2 disable latch U20B by appearing at the set lead (pin 8), the signal forces U25B into a three-state mode. Once again, driver B1 has already been disconnected so the isolation is redundant.
Module self test feature

As part of the system fault maintenance feature, the DR module has a function that verifies the integrity of the audio paths on the board. If any of the paths fails the test, the module voluntarily isolates itself from the TDM and system data buses and notifies the operator that a problem exists. The test is initiated by the microprocessor. The output TEST (pin 14) is first set high, allowing a test tone (2175 Hz entering the board at card edge pin 98) to be gated through inverter U12D and transistor Q1. Following the signal path, the tone is routed into both the channel 1 and channel 2 DLM circuits and appears at the inputs of CODECS U16 & U17 (pin 3). The tone is digitized and inserted into the correct slots on the TDM bus as if it were receive audio. Once on the TDM bus, the test tone is routed to the COIM where, if it is detected, a successful test is indicated.
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While the test is running, an output from the microprocessor labeled MUTE (pin 12), turns off mute gates Q103/Q203 within the Digital Level Memory (DLM) circuitry, inhibiting receive audio from reaching the CODECS. This muting prevents voice audio from mixing with the test tone and falsifying the test. This simple test verifies correct operation of not only both DLM circuits but the circuit block that digitizes the audio and places it in the proper slot on the TDM bus. The components involved in these functions include CODECS U16 & U17, latches U14 and U15, buffer U25 and TSAC U5. This test verifies the proper operation of the system bus isolation switching circuitry as well.
Auxiliary inputs
The DR module has six auxiliary inputs that can be used to supply information to its resident microprocessor. The inputs are connected to the three-state buffers within U6. These inputs are brought out to terminations on the card cage to accept switched ground inputs from external equipment. Periodically, the microprocessor reads the auxiliary inputs and sends the status over the system data bus to the system main microprocessor located on the COIM. The system main microprocessor interprets the information and takes whatever action is required. The microprocessor on the DR module reads the input bits by making the INPRD output of address decoder U3 low (Q2 pin 13). The U6 buffers are then enabled and the auxiliary inputs appear on the microprocessor data bus from which the microprocessor can read them. When the microprocessor reads the status of these auxiliary inputs, it also reads the signals CALL1 and CALL2. Entering the board at card edge pins 69 and 70, these signals go low when audio coming in from the base station is detected. CALL1 is activated when audio is detected in DLM1, and CALL2 is activated when audio is detected in DLM2. The status of these bits is sent to the operator position so that the appropriate operator indicators can be displayed.
DR module jumpering
The various jumpering configurations for the DR module are shown on the schematic diagram jumpering charts.
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DR signal names
Table 9-2 defines the signals present on the DR module.
Table 9-2
DR signal names
Definition
Read module address Address decode TDM bus #1 busy TDM bus #2 busy TDM bus #3 busy Voice activity on channel 1 Voice activity on channel 2 2 MHz system clock TSAC chip System communications (serial) data bus System data bus busy Data clock TSAC data input Data grant Data ready System data bus request Microprocessor enable signal output Mask frame synch interrupts Interrupt address strobe Ready auxiliary inputs Low frequency clock (80 Hz) TDM bus #1 TDM bus #2 TDM bus #3 Read from system data bus Write to system data bus Power down Receive channel 1 enable Microprocessor reset RS-232-C receive data Microprocessor read/write control output Slot sub-n (goes high when the slot the module has been addressed for is valid on the TDM bus)
Signal name ADR RD A3, A4 BSY 1 BSY 2 BSY 3 CALL1 CALL2 CLK, CLK CS DB DBSY DC DI DG DRDY DR E, BUFF E FSM IAS INP RD LCLK MB1 MB2 MB3 MDR MDW PD RXE RST RX DATA R/W SN
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Table 9-2
DR signal names (continued)

Definition
TSAC clock Transmit digital data High level signals generated by microprocessor during self-test Gated test tone RS-232-C transmit data Channel 1 transmit analog input Channel 2 transmit analog input Test tone Three-state 1 signal Three-state 2 signal Receive channel 2 enable Voltage analog ground (6 V) Reference signal derived from A3 (address decode) signal Test tone input
Signal name TCLK TDD TEST, MUTE TT TX DATA TXIA TXIB TT TS1 TS2 TXE VAG 16 KHZ 2175 KHZ
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Dual Receive Interface Module BLN6656C Overlay
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Dual Receive Interface Module BLN6656C Schematic

(Sheet 1 of 2)
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Dual Receive Interface Module BLN6656C Schematic

(Sheet 2 of 2)
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BLN6656C Parts List

Reference
Description
Reference
Description
capacitor, fixed:
C1 thru 8 C9 C10 thru 24 C25,26 C27 C28 thru 30 C31 C32 C33 C34 thru 36 C37,38 C39 C40,41 C42 C43 C44 C48 thru 63 C100 C104 C105 C106 C107 C108 C109 C110 C111 C113 C114 C115 C116 C117 C118,119 C200 C205 C206 C207 C208 C209 C210 C211 C215 C216 C217 C219 2113741B69 2313748G04 2113741B69 2111022A39 0811017A01 0811051A12 2111022A39 0811017A01 2313748G04 2313748G22 2313748G14 2313748G04 2313748G14 2111014A42 0811017A06 2313748G06 2113741B69 0811017A08 2313748G09 2313748G06 2313748G04 2313748G06 0811017A08 2313748G06 0882045F09 0811051A12 2113741B69 2313748G09 2111022A55 2111022A64 2313748G05 2113741B69 0811017A08 2313748G06 2313748G04 2313748G06 0811017A08 2313748G06 0882045F09 0811051A12 2111022A55 2111022A64 2313748G05 2113741B69 CAP CHIP CL2 X7R REEL 0.1UF 5% 50V CAP ELEC 1.0 UF 50V 20% CAP CHIP CL2 X7R REEL 0.1UF 5% 50V CAP CER DISC 24PF 5% NPO 50V CAP POLYEST .001UF 5% 50V CAP MTLZ POLYEST .068UF 5% 63V CAP CER DISC 24PF 5% NPO 50V CAP POLYEST .001UF 5% 50V CAP ELEC 1.0 UF 50V 20% CAP ELEC 100 UF 25V 20% CAP ELEC 22 UF 35V 20% CAP ELEC 1.0 UF 50V 20% CAP ELEC 22 UF 35V 20% CAP CER DISC 51PF 5% NPO 100V CAP POLYEST .0047UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP CHIP CL2 X7R REEL 0.1UF 5% 50V CAP P0LYEST .01UF 5% 50V CAP ELEC 10 UF 35V 20% CAP ELEC 4.7 UF 50V 20% CAP ELEC 1.0 UF 50V 20% CAP ELEC 4.7 UF 50V 20% CAP P0LYEST .01UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP MTLZ POLYEST 2.2UF 10% 250V CAP MTLZ POLYEST .068UF 5% 63V CAP CHIP CL2 X7R REEL 0.1 5% 50V CAP ELEC 10 UF 35V 20% CAP CER DISC 100PF 5% NPO 50V CAP CER DISC 200PF 5% NPO 50V CAP ELEC 2.2 UF 50V 20% CAP CHIP CL2 X7R REEL 0.1UF 5% 50V CAP P0LYEST .01UF % 50V CAP ELEC 4.7 UF 50V 20% CAP ELEC 1.0 UF 50V 20% CAP ELEC 4.7 UF 50V 20% CAP P0LYEST .01UF 5% 50V CAP ELEC 4.7 UF 50V 20% CAP MTLZ POLYEST 2.2UF 10% 250V CAP MTLZ POLYEST .068UF 5% 63V CAP CER DISC 100PF 5% NPO 50V CAP CER DISC 200PF 5% NPO 50V CAP ELEC 2.2 UF 50V 20% CAP CHIP CL2 X7R REEL 0.1 5% 50V
CR21 thru 26 CR29 thru 41 CR100 thru 111 CR200 thru 212
4811034A01 4811034A01 4811034A01 4811034A01
DIODE 48C83654H01 A/I DIODE 48C83654H01 A/I DIODE 48C83654H01 A/I DIODE 48C83654H01 A/I

fuse:
jumper:
JU1 JU3,4 JU5 thru 16 JU18,19 JU21,22 JU23 thru 25 0611009B23 2880001S03 0611009B23 0611009B23 0611009B23 2880001R03 RES JUMPER CON PCB HDR 1 GOLD DR ST 6 POS RES JUMPER RES JUMPER RES JUMPER CON PCB HDR .1 GLD SR ST 3 POS

Q1 Q2 thru 4 Q5 thru 7 Q8,9 Q10 Q11,12 Q13 Q14 Q16 Q17 Q18 Q20 Q100,101 Q102 Q103 Q104 Q200,201 Q202 Q203 Q204 4811043C02 4813824D08 4811043C02 4813824D08 4813824D04 4813824D12 4813824D04 4811043C37 4811043C02 4813824D12 4811043C02 4811043C37 4813824D06 4811043C02 4811043C37 4813824D10 4813824D06 4811043C02 4811043C37 4813824D10 TSTR 48R00869570 A/I TSTR NPN 80V .5A MPSA06RLRP TSTR 48R00869570 A/I TSTR NPN 80V .5A MPSA06RLRP TSTR DARL NPN 30V .3A MPSA13 TSTR PNP 80V .5A MPSA56RLRP TSTR DARL NPN 30V .3A MPSA13 TSTR 48R00869653A/I TSTR 48R00869570 A/I TSTR PNP 80V .5A MPSA56RLRP TSTR 48R00869570 A/I TSTR 48R00869653A/I TSTR NPN 40V .2A 2N3904RLRP TSTR 48R00869570 A/I TSTR 48R00869653A/I TSTR PNP 40V .2A 2N3906RLRP TSTR NPN 40V .2A 2N3904RLRP TSTR 48R00869570 A/I TSTR 48R00869653A/I TSTR PNP 40V .2A 2N3906RLRP
resistor, fixed:
R1 thru 22 R23 thru 32 R33 thru 39 R40 thru 44 R45 R46,47 R48 R49 R50 R51 thru 56 R57 R58 thru 61 R62,63 R64,65 R66 0611077A98 0611077A58 0611077B47 0611009A65 0611009A73 0611009A65 0611077A82 0611077A90 0611077A82 0611077B07 0611077B15 0611077A82 0611077B07 0611077A82 0611077B47 RES CHIP 10K 5% 1/8W RES CHIP 220 5% 1/8W RES CHIP 1 M 5% 1/8W RES FCF 4700 5% 1/4W RES FCF 10K 5% 1/4W RES FCF 4700 5% 1/4W RES CHIP 2200 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 2200 5%1/8W RES CHIP 22K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1 M 5% 1/8W
diode: (see note)

CR1 thru 6 CR13 CR14 thru 19 4811034A01 4882592W01 4811034A01 DIODE 48C83654H01 A/I DIODE SCHOTTKY BARRIER DIODE 48C83654H01 A/I _
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BLN6656C Parts List
R67 thru 70 R71 R72,73 R74 R75 R76 R77 R78 R79,80 R81 R82,83 R84 R85 R86 R87 R88 R89 R90 R91,92 R93 R94 R95,96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 thru 108 R109 R110 R111 R112,113 R114 R115 R116,117 R119 thru 121 R122 R123 R124 R125 R126 R127 R128 R129 R130 R131 R134 R135 R136 R137 R144 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212,213 R214 R215 R216,217 R218 R219 thru 221 R222 R223 R224
0611077A98 0611077A94 0611077A74 0611077A90 0611077A98 0611077B07 0611077A90 0611077A98 0611077B19 0611077A98 0611077A94 0611077A26 0611077A90 0611077A82 0611077A78 0611077A68 0611077A78 0611009A73 0611077A68 0611077A98 0611077A78 0611077A98 0611077B07 0611077A82 0611077B07 0611077A98 0611009B22 0611077A98 0611077A74 0611077B15 0611009B22 0611077A98 0611077A68 0611077B17 0611077A98 0611077B37 0611077A98 0611077B37 0611077B31 0611077A98 0611077B23 0611077B15 0611077B07 0611077A98 0611077B37 0611077B47 0611077B07 0611077B33 0611077B15 0611077B47 0611077B11 0611077B27 0611077A90 0611009A49 0611077B01 0611077A98 0611009B22 0611077A98 0611077A74 0611077B15 0611009D22 0611009A73 0611077A74 0611077A98 0611077A68 0611077B17 0611077A98 0611077B37 0611077A98 0611077B37 0611077B31 0611009A89 0611077A98 0611077B23 0611077B15 0611077B07
RES CHIP 10K 5% 1/8W RES CHIP 6800 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 68K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 6800 5% 1/8W RES CHIP 10 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 1500 5% 1/8W RES FCF 10K 5% 1/4W RES CHIP 560 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES FCF 1M 5% 1/4W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47K 5% 1/8W RES FCF 1M 5% 1/4W RES CHIP 10K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 56K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 220K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 270K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 33K 5% 1/8W RES CHIP 150K 5% 1/8W RES CHIP 4700 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 12K 5% 1/8W RES CHIP 10K 5% 1/8W RES FCF 1M 5% 1/4W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 47K 5% 1/8W RES FCF 1M 5% 1/4W RES FCF 10K 5% 1/4W RES CHIP 1000 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 560 5% 1/8W RES CHIP 56K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 220K 5% 1/8W RES FCF 47K 5% 1/4W RES CHIP 10K 5% 1/8W RES CHIP 100K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 22K 5% 1/8W
R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R240 R241 R300 thru 304 R305 R306 R307,308 R310 R311 R312 R313 R315 R316 R317 R318 R319,320 R321 thru 325 R326 R327 R328 R329 R330 R331 R332 thru 337 R338,339 R340 R341 R342 R343
0611077A98 0611077B37 0611077B47 0611077B07 0611077B33 0611077B15 0611077B47 0611077B07 0611077A98 0611077B11 0611077B27 0611077A90 0611009A49 0611077B03 0611009A73 0611077A98 0611077A74 0611077A98 0611077A90 0611077A90 0611077A50 0611077B07 0611077A98 0611077B07 0611077B15 0611077A90 0611077B15 0611077B07 0611077A82 0611077B07 0611077A84 0611077A90 0611077A78 0611077B05 0611077A90 0611009A97 0611077A26 0611077A90 0611077A98 0611077A64 0611077B07
RES CHIP 10K 5% 1/8W RES CHIP 390K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 270K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 1 M 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 33K 5% 1/8W RES CHIP 150K 5% 1/8W RES CHIP 4700 5% 1/8W RES FCF 1000 5% 1/4W RES CHIP 15K 5% 1/8W RES FCF 10K 5% 1/4W RES CHIP 10K 5% 1/8W RES CHIP 1000 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 100 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 47K 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2200 5% 1/8W RES CHIP 22K 5% 1/8W RES CHIP 2700 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 1500 5% 1/8W RES CHIP 18K 5% 1/8W RES CHIP 4700 5% 1/8W RES FCF 100K 5% 1/4W RES CHIP 10 5% 1/8W RES CHIP 4700 5% 1/8W RES CHIP 10K 5% 1/8W RES CHIP 390 5% 1/8W RES CHIP 22K 5% 1/8W
switch:
S1 S2 4083849F02 4084961N01 SWITCH ROCKER DIP 8 POSTN SW PB SPDT MOMENTARY
transformer:
T1,2 2584007C02 XMFR AF

U1 U2 U3 U4 U5 U6 U7 U8 U10 U11 U12 U13 U14 U15 U16,17 U18 U19 U20 U21 U22 U23 U24 U25 5183625M66 5183539M01 5184118K34 5190044C22 5184704M45 5184887K71 5184118K79 5184118K27 5184118K35 5184810F64 5184887K52 5184118K06 5184887K70 5184887K13 5113811D20 5184887K06 5184887K18 5184887K13 5184118K01 5184118K13 5184887K01 5184118K14 5184887K71 IC BI IC 39M01 TTL LOGIC IC DCDR 3-TO-8 LINE _4LS138_ IC PRGMD EPROM 8KX8 IC CMOS DGTL __14416_ IC HEX BFR 3-STATE NONINV_4503 IC OCT BFR 3-ST NONINV_4LS244_ IC TYPE 74LS367 IC SHIFT RGTR 8-BIT _4LS165_ IC 8BIT SHIFT RGTR _4LS229_ IC MC14584BCP IC 74LS00 TTL LOGIC IC HEX D F/F_14174_ IC CMOS DUAL F/F __4013_ PCM CODEC/FLTR MONO-CIRCUIT IC CMOS DUAL BIN CTR __4520__ IC CMOS TRP NOR __4025_ IC CMOS DUAL F/F __4013_ IC DL F/F D-TYPE _4LS74_ IC QUAD 2-INP NOR _4LS02_ IC CMOS HEX BUFFER __4049_ IC TYPE 75LS05 IC HEX BFR 3-STATE NONINV_4503
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U26 U27,28 U29 U30 U31 U32 U33 U34 U35,36 U37
5184887K78 5184887K06 5184887K13 5113819D04 5184887K09 5184064F76 5184118K80 5184118K29 5113816J03 5113816D01
IC CTR BCD/4BIT BIN _4569_ IC CMOS DUAL BIN CTR __4520__ IC CMOS DUAL F/F __4013_ GEN PURPOSE 14 DIP MC3303P IC CMOS QUAD NOR ___4001_ IC CMOS SRAM (32KX8)_60256_ IC OCT BUS XCVR _4LS245_ IC 18K29 TTL LOGIC IC 12V POSITIVE REG,100MA IC 5V POSITIVE REG,1.0A
crystal: (see note)

Y1 4882611M15 XTAL OSC 11M15
network:
Z1,2 Z3,4 Z5,6 Z7 0182989R36 0182989R27 0182989R26 0182989R28 MODE HYBRID GAIN ALC MODE HYBRID R 2R MODE HYBRID CPTR ALC MODE HYBRID DVR BUS
0310943J09 0982808R10 0984728L01 2683373P02 5583323P01 SCRTPG TT3X0.5X6 INTSTARPAN (2 used) SKT IC DIP 28 CONT (used with U4) SKT CONN (5 used) HT SINK TSTR HNDL CKT BD
NOTE: FOR OPTIMUM PERFORMANCE, DIODES, TRANSISTORS,

INTEGRATED CIRCUITS, AND CRYSTALS MUST BE ORDERED BY MOTOROLA PART NUMBER.
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10 10 Console
Operator Interface Module
About this chapter

Section
Introduction Theory BLN7061A Parts List
Page
10-2 10-3 10-37
Models covered
The following models of the Console Operator Interface Module (COIM) are covered in this chapter:
Model
BLN7061A
Description
Console Operator Interface Module

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Introduction
The purpose of the BLN7061A Console Operator Interface Module (COIM) is to interface the operator position to the CEB. The COIM is based on the MC68020 microprocessor. It serves the same purpose as, and is an enhancement of, the MC68000 microprocessor-based Advanced Expanded Operator Interface Module (OMI). In a trunked system, jumpers on the COIM may also be configured so the board is the interface between the CEB and the Trunking Central Controller. The Trunking Central Controller and the COIM communicate via RS-232 protocol through a modem-phone link. In both applications, the COIM hardware remains the same except for the jumper settings, while the firmware and personality EEPROMs define the application. The COIM also provides Audio Expansion Interface (AEI) triple slot receiver capability. This circuitry processes the three audio Mux Buses and distributes audio to either the Select, Unselect, Monitor1 or Monitor2 operator position speakers.
p p
A Dual Universal Asynchronous Receiver-Transmitter IC (DUART) which provides two serial data links: one to the operator position, and one to the diagnostic printer port (TTY). The DUART also has one input port and one output port, used for reading and writing status and control signals. A Logic Cell Array (LCA) which contains:
p p p p p
m m m m m m m
control circuitry for system TDM bus and data bus access interrupt priority encoder for the microprocessor tone detect and audio source control circuitry for fault maintenance, programming interface circuitry for AEIs tone generator audio TDM bus interleaving for the DSP56166 miscellaneous status lines which are read by the microprocessor.
Microprocessor watchdog circuitry. Voltage regulation and protection circuitry. A/D conversion circuitry for operator microphone audio. Balanced audio outputs for Select, Unselect, Monitor 1 and Monitor 2 channels. Reconstruction filter for Monitor 2 output
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Console Operator Interface Module Theory
Theory
Refer to Figure 10-1. The COIM consists of eight main circuit blocks:
p p p p p p p p p
Microprocessor and peripherals Watchdog timer and three-state control Diagnostic tone detection Operator audio interface CEB data bus interface Logic Cell Array (LCA) Digital Signal Processor (DSP) and peripherals Audio output circuitry Voltage regulation
MUX BUS
CODEC
AUDIO MUX
MIC AUDIO GUARD TONE
AEI CONTROL MUX BUS 1, 2, 3
TONE GEN.
DIAGNOSTIC TONE DETECTOR MUX CTL ROM
TONE DETECT
CLOCK A4
TSAC
SELECT/BEEP
DATA BUS DATA CLOCK
DATA BUS INTERFACE
AEI PGM INTERFACE
UNSELECT
Interleaved Audio
DSP
MUX MON 1
DRDY
DATA RQST/ DATA GRANT
LCA INTERRUPT PRIORITY ENCODER
TDM ADDR. MON 2
DATA REQUEST DBSY
DUART
OPERATOR POSITION DATA TO DIAGNOSTIC TERMINAL
PERSONALITY EEPROM
15V 9V
VOLTAGE REGULATION
12V 5V MICROPROCESSOR
RAM
PAL
PROGRAM EPROM
CONTROL SWA+, SWGND TRI-STATE CONTROL
WATCHDOG
DATA REQUEST
CEN041 110395JNM
Figure 10-1 Block Diagram of COIM
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Microprocessor and peripherals

Refer to the schematic diagram. The COIM uses the MC68020 microprocessor, which has 32-bit address and data buses. The microprocessor runs at 15Mhz, driven by a crystal oscillator. The microprocessor also supports an instruction cache, which can be disabled by inserting jumper JU2.
Timing signals
The microprocessor timing signals are generated by a set of three programmable array logic (PAL) chips. U2 generates chip select signals used by the peripherals and memory attached to the processor. U3 generates the output enable and write enable signals that specify when a peripheral is to read from or write to the microprocessor data bus. The write enable signals also control dynamic bus sizing. U4 generates wait states for slow peripherals, as well as the bus error signal. It also signals the size of the data transferred to the microprocessor.
On-board memory
There is one socket for program EPROM located on the board (P3). It can accept one Single In-line Memory Module (SIMM) with memory capacities of two or four Mb. All the devices are eight bits wide. ROM accesses are 32 bit transfers. The SIMM board will accept a wide variety of 32 pin PLCC parts. Refer to Table 10-1 for component placement for specific memory configurations. There are two sockets for devices which store personality and user information. The sockets can be populated with either EPROM or EEPROM devices. Devices with memory capacities of 256kbit, and 1,2, or 4 Mb are supported. The memory capacity of each device must be selected using jumpers prior to use. Transfers to and from these devices are 16 bits wide. There are four RAMs that are permanently soldered to the board (U208 through U211). They have a capacity of 512k bytes in a 32 bit wide configuration. The LCA interfaces directly with the microprocessor data bus in a byte wide configuration. The LCA appears as a series of registers to the microprocessor. Besides acting as a peripheral, the LCA is also responsible for interrupt prioritization.
I/O interface
The Dual Asynchronous Receiver Transmitter (DUART) provides two serial communication paths for the board. It is also a general interface for various input and output signals, and provides a real time interrupt via the built in timer. The DUART interfaces to the processor as an 8-bit wide device. Serial port A relies on a BLN6755C serial board to provide the interface necessary to communicate with the outside world. Port B uses an onboard driver and receiver. The transmitter for port B is a current gain stage based on the CEB bus driver circuit. The port B receiver is a balanced, opto-coupled design. It provides better noise immunity and fault protection. As a consequence of using an opto coupled design, compatibility changes have been made to the BLN6755C.
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NOTE Use of the A and B versions of the BLN6755 Serial Board with the BLN7061A COIM is not recommended.
The DUART also provides an input/output interface for the following signals:
Table 10-1
COIM Outputs
Description
A control signal that instructs the AEI to generate a beep tone at the OP Clear To Send signal used in RS232 communication Used to switch the green status LED on or off A control signal used to reset the tone detection circuitry Signal used to vote for a system timer switch Used to interface with the TSAC circuitry located in the LCA Tristates the board
Output BEEP CTS GRN-LED TND-RESET A-B_-VOTE TSAC-SEL VOL-TS
Table 10-2
COIM Inputs
Description
Carrier Detect signal supplied by the BLN6755C 12 Volt power fail a dual purpose signal generated by the LCA 10 hz clock generated by the system timer module clear to send signal used by the operator position interface
Input CAR-DTCT 12V-FAIL PF-RDY-BSY 10-HZ CTS
Watchdog timer and three-state control

The watchdog timer starts the microprocessor and some peripherals when power is first applied to the board, and provides automatic recovery in case of a hung microprocessor. This circuitry also generates the three-state signals that isolate the board from the rest of the system. A DS1232 microprocessor monitor checks three conditions for the microprocessor: power supply, software execution and external override. First, a precision reference and comparator circuit is used to monitor the status of power (VCC). When an out of tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in tolerance condition, the reset signals are kept in the active state for a minimum of 250ms to allow the power supply and processor to stabilize. Second, the DS1232 provides a pushbutton reset control. The DS1232 debounces the pushbutton input and guarantees an active reset pulse width of 250ms minimum. The
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third function is for watchdog timing. The microprocessor monitor has an internal timer which forces the reset signals to the active state if the strobe input is not driven low prior to time out. As long as the processor continues to strobe DOG, the processor will not be reset. If JU1 is inserted, then DOG-RESET will be held in the inactive state, effectively disabling the reset circuit. In the event of a clock failure, the board will be permanently held in reset. The tristate signal is asserted whenever reset is asserted, or whenever the voluntary tristate signal is asserted. The voluntary tristate signal is generated by the processor via a DUART output. There are two tristate signals: 5V-TS is a TTL level signal that is used to tristate 5 V logic. TS is a 12 V signal used to tristate CMOS logic and the CEB data bus drivers. In the event of 5 V failure, TS is asserted by a passive pull-up resistor. Whenever the board is tristated, the red status LED is lit.
Diagnostic tone detection

Diagnostic tone detection on the COIM allows the microprocessor to check the integrity of audio paths on the board itself and through the systemby means of audio loop tests. Refer to the Maintenance and Diagnostics chapter for more information on conducting the audio loop tests.
Guard tone detection

System guard tone is passed through the various audio paths and routed to the check tone filter comprised of U530 and associated components. There are four possible sources of audio entering this filter: system guard tone, recovered audio from the CODEC, recovered audio from the AEI board, and recovered audio from the resident slot receiver on the COIM. The recovered audio from the CODEC is not normally used in tone tests and only one of these sources is present during a particular tone test. The first stage of the check tone filter provides low-pass filtering and individual gain compensation for each of the sources, ensuring that they are all at about the same level going into the second stage. The second stage is a low-pass filter with a pole at 2175 Hz and a Q of 4.5. The filter eliminates noise which may be present on the audio paths, recovering only fundamental frequency information. The output of the filter appears at the input of a self-biased Schmitt trigger inverter which squares up the signal before it is sent to a level shifting buffer. The output of the level shifting buffer is applied to the LCA, which compares the applied signal to the guard tone signal it is receiving on its GT input. In this manner, it is ensured that the diagnostic tone detector is indeed checking the integrity of the audio path and simply not falsing on some noise which may be present. The microprocessor can then read the result of the test out of the LCA. If the tone test passes, a high appears in the seventh bit position when LCA Port A is read. A high on the LCA TND-RESET input resets this bit in preparation for another test.
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Microprocessor tone tests

The microprocessor begins its tone tests by first checking the guard tone before digitization, at the output of analog multiplexer U528. The microprocessor writes a control word to LCA Port A which sets the LB-SELA and LB-SELB outputs to 11, thus selecting the Y0 input of the multiplexer. This routes guard tone to the tone detection circuitry. Passage of this test indicates that guard tone is present on the system backplane and that the tone detect circuitry is working. Next, the microprocessor writes to LCA Port A to select the X1 input of the multiplexer to be routed to the CODEC for digitization. The digitized guard tone will be placed in the TDM slot assigned to the COIM and the AEI or resident slot receiver will be programmed to recover this audio. The AEI or resident slot receiver will then route the recovered analog audio to the tone detection circuitry via the AEI signal on the system backplane. Finally, to verify operation of the audio routing hardware, the analog multiplexer is programmed to submit no audio to the tone detection circuit, which should result in a negative detection.
Operator audio interface

One of the main functions of the COIM is to accept analog microphone audio from the operator position, digitize the audio, and place it on one of the system TDM buses. Once on the TDM bus, the audio is made available to Base Station Interface modules, which recover the digitized audio and transmit it to a base station for broadcasting. The microphone audio is sent to the COIM via a seven pair cable which connects the CEB to the operator position. This audio is transformer coupled onto the COIM at the MIC-AUD+ and MIC-AUD- inputs. It is applied to analog multiplexer U528 and routed to the CODEC (U515) where it is digitized. The digitized audio from the CODEC TDD output is passed through mux gate U531 and applied to hex flip-flop U503. The output of the flip-flop is sent to three-state buffer U505, and looped back to the CODEC RDD input. The output of the three-state buffer is applied to the bus driver circuitry which then drives the system TDM bus being selected by JU501. U505 and the system bus driver circuitry can both be disabled by the board three-state signal (TS), thus providing double point isolation from the system TDM bus.
CEB data bus interface

The COIM can transmit and receive data from the system data bus, which enters the board on the input labeled DATA . The system data bus is the channel through which all boards in the CEB communicate. Data transfers on the data bus are controlled by the CEB System Timer module. One byte of data is transferred each frame under control of the data clock, DC, generated by the System Timer. This clock shifts data bits onto and off of the data bus during the first two TDM time slots of each frame at one half the TDM bit rate. The System Timer sequentially polls all boards in the CEB for use of the data bus via the Busy Bus lines B1, B2, and B3. The Busy Bus being used by the COIM must correspond to the Mux Bus the module uses and, hence, its TDM address.
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Data bus control

Before transmitting on the data bus, the COIM must request and attempt to seize the bus, and then verify that it has done so. To do this, the COIM first asserts its DATA-REQ signal by writing to decoder U5. This pulse clocks flip-flop U508, making DR low, which is applied to three-state buffer U505. U505 is only enabled during the COIMs assigned TDM slot. The TXn signal from the LCA goes low approximately one system clock period before the COIMs TDM slot becomes active. This signal is then clocked through U503 and AC coupled to the three-state control of U505. With U505 enabled, the DR signal is allowed to reach U508, where the modules polling pulse, clocked off of the Busy Bus via U503, clocks the DR signal through U508. The non-inverting output of U508 (DATA-GRANT) is applied to the LCA as an indication that the board has been granted the data bus. The inverting output of U508 clears the DR signal out of U508 and goes through another three-state buffer of U505 (which is still enabled). The output of the three-state buffer is AC coupled to the bus driver circuitry, producing a high pulse on the system DRDY line. DRDY (data ready) is a signal which goes to the System Timer as an indication that the system data bus has been seized. The Timer responds to DRDY by discontinuing its data bus polling activity, asserting the DBSY line, and generating DC at the beginning of each frame to transmit the data. The COIM asserts DRDY each frame during its TDM slot for the duration of the data packet transfer. When the data transfer is over, the timer removes the DBSY signal, discontinues DC, and begins polling again. The first polling pulse that the timer issues clocks U508, thus clearing the DATA-GRANT signal and in effect removing the COIM from the data bus by preventing it from generating DRDY until another request has been generated.
Data bus transfers

Transmit and receive data to/from the system data bus is handled through LCA U524. The microprocessor writes and reads the LCA registers dedicated to this function. When the microprocessor requests the data bus, it also writes a start-of-text byte (A5) to the CEB data transmit register in the LCA. The start-of-text byte indicates the beginning of a data packet. After a module has been granted use of the data bus and DBSY is asserted, DBSY enters the LCA on the COIM which generates a microprocessor interrupt. If the first byte read out of the CEB data receive register is not start-of-text, the microprocessor assumes that a spurious DBSY interrupt occurred, and ignores the interrupt. When the COIM requesting the data bus receives the DBSY interrupt, it assumes that it has been granted control of the system data bus and so writes its TDM slot address into the CEB data transmit register and unmasks its start-of-frame interrupt by writing to the A4 interrupt mask register in the LCA. The LCA generates the start-of-frame interrupt in response to a falling edge on the system A4 line. After the next start-of-frame interrupt occurs, the microprocessor writes the destination address of its data packet into the CEB data transmit register, and reads the data that was just received. If the byte received (source address) matches the COIMs TDM address, the microprocessor knows that it has control of the data bus and will continue sending its data packet. If the addresses do not match, the microprocessor will again write start-of-text into the CEB data transmit register and await the next DBSY interrupt. As stated above, receipt of a data packet is initiated by a DBSY interrupt. After DBSY is received and the start-of-frame interrupt is unmasked, the COIM receives a byte of data each frame after the start-of-frame interrupt occurs. After reading the third byte
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(destination address) of the data packet, the microprocessor determines if it needs to receive the rest of the bytes. If the packet is bound for another module, it masks off start-of-frame interrupts and attends to other tasks. Otherwise, it leaves the interrupt enabled to receive the rest of the data.
Logic cell array

The COIM LCA, U524, performs the following functions:
p p p p p p p p p
Controlling TDM bus access Providing an interface to the AEIs Data handling for system data bus transfers Providing an interface to the TDM address DIP switch Generating prioritized interrupts for the microprocessor Performing diagnostic tone tests Providing an interface to the audio multiplexer Generating digital tones Audio bus interleaving for slot receiver
The LCA is a static RAM-based device, and therefore must be configured each time the board is powered up. The microprocessor handles this task as part of its start-up activity. Upon power-up, the LCA drives its PF-RDY-BSY output high to tell the microprocessor that it is ready to receive configuration data. The microprocessor then writes a byte of configuration data to the device PD24-uPD31 pins while selecting the LCA via the XLX-SEL input. After the LCA receives the byte, it will drive its PF-RDY-BSY output low until it has processed the information. When it is ready to receive another byte of data, it will again drive PF-RDY-BSY high. This cycle continues until the LCA is fully configured. Once the LCA is configured, the microprocessor communicates with it through a group of ports in the device which are accessed via the PD24-uPD31, PA0-uPA2, PR-W, and XLX-SEL pins. These ports are accessed under the conditions shown in Table 10-3:
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NOTE The operation allowed on each port is shown in parentheses after each description. Note that some ports are write-only; their contents cannot be read.
Table 10-3
LCA Port Access Conditions

LCA Configuration Data (Contents of uPD31-uPD24)
XLX-SEL
0 0 0 0 0 0 0 0 0 0 0 1 0 1
uPR-W
uPA2-i uPa0
0 0 1 1 2 2 3 4 5 6 7
TDM Address (Read) Clear 18ms Interrupt (Write) CEB Data Bus Receive Register (Read) Clear A4 Interrupt (Read/Write) Port A: A-B_STATUS = uPD31 Results of Tone Test = uPD30 (Read) Tone Generator Shift Register (Write) A4 intr. mask (bit2), 18ms intr. mask (bit1), tone gen. enable (bit0); all bits read and write Port A: uPD30-uPD27 = AEI Select Lines (S3-S0), uPD26, uPD25 = LB-SELB, LB-SELA (Write) CEB Data Bus Transmit Register (Write) AEI Configuration Data Register (Write) Clear DBSY Interrupt (Read/Write)
X 1 0 0/1 0 0 0 X
In addition to the ports listed in Table 10-3, there is one more location which the microprocessor accesses to control TDM bus access. The Time Slot Assignor Circuit (TSAC) register can be written by driving the TSAC-SEL input high and writing to the AEI Configuration Data Register. This circuit controls the activity on the TDM transmit enable (TXE) and receive enable (RXE) outputs. These signals go low for one TDM time slot, based on the information written to the TSAC register. The eight bit pattern written on the PD31-uPD24 inputs has the following meanings:
Microprocessor Data Outputs D31
0 0 1 1
TSAC Function
D30
0 1 0 1
D29 - D24
Slot Address Slot Address Slot Address X Program Transmit and Receive TDM Slot Addresses Program Transmit TDM Slot Address Program Receive TDM Slot Address No Operation Performed
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Chapter 10
AEI boards or resident slot receivers are programmed by the COIM to recover certain audio slots off of the TDM buses and route the audio to various operator position speakers. Programming of the slot receiver/AEIs is done via the LCA S3-S0, SHIFT-CLK, SHIFT-DATA, RSSI0_DATA outputs and RSSI_CLK input. S3-S0 select the slot receiver and/or three AEI boards to program. The SHIFT-DATA and SHIFT-CLK signals then send a serial bit stream to all AEIs, providing instructions for audio recovery operations. Upon each write to the slot receiver/AEI configuration data register, eight cycles of SHIFT-CLK are automatically generated, shifting the eight data bits to the AEI. The RSSI_CLK and RSSI0_DATA are used as a second gated clock interface to communicate to the DSP. After SHIFT-DATA is complete, the LCA interrupts the DSP via IRQA, forcing the DSP to generate a gated clock to the RSSI_CLK input. This clock forces a second LCA shift register to shift time slot or control word data to the DSP. This data is saved and indexed in the DSPs control word table. Data for CEB data bus transfers is received and transmitted in serial form on the CEB-RX-DATA and CEB-TX-DATA pins, respectively. These transfers are controlled by read and write operations to the CEB data bus receive and transmit registers, as well as activity on the DG and DC inputs. DG clocks the received serial data while DC, qualified with a valid DG is used to clock transmit data out. The TDM address DIP switch is connected to the COIM data bus D:24-31 through latch U400. U400 drives the COIM data bus upon reception of a TDM_ADD_RD generated by the LCA. These inputs have pull-up resistors so that opening the switch programs a one, while closing the switch programs a zero.
Interrupt priority
The microprocessor interrupt priority lines are controlled by the IPL2-IPL0 outputs. The level on these three lines generate microprocessor interrupts of varying priority as described below. The A4 and DBSY interrupts are edge sensitive, while the DUART-IRQ interrupt is level sensitive. The A4 interrupt actually occurs approximately 24 system clock cycles after the falling of the A4 input. This ensures that by the time the A4 interrupt occurs, any byte that was sent on the system data bus during the first two slots of that frame has been completely received. (See the CEB Data Bus Interface section for more details). Aside from the external signals (A4, DBSY, DUART-IRQ), there are two signals internal to the LCA which are capable of causing interrupts. One signal is the 18ms interrupt. This signal is generated by dividing down the DUART-CLK input to provide a periodic interrupt which can be used to time (and watchdog) various software tasks. The other is the tone generator interrupt, used to notify the software that the tone generator
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shift register is empty and needs to be loaded with another PCM audio sample. Interrupt activity is summarized in Table 10-4.
Table 10-4
Microprocessor Interrupts
DUART-I RQ
X X X active inactive inactive X X active inactive inactive inactive
18 mS Int.
X X X X active inactive
Tone Gen.
A4 Int.
X active inactive inactive inactive inactive
DBSY Int.
active inactive inactive inactive inactive inactive
IPL 2-0
2 3 4 5 6 7
Relative Priority
highest
lowest no interrupt
Diagnostic testing
Diagnostic tone detection is performed using the TND-RESET, GT, and DETECT-TONE inputs. Each time TND-RESET toggles high then low, a new tone test is started. For the duration of the test, the number of cycles of DETECT-TONE are counted per every 8.5 cycles of the GT input. If the number of DETECT-TONE cycles during any 8.5 GT cycle period is between 8 and 10, then the test is given a pass status. Hence, this test ensures that the DETECT-TONE input is within the range of 94% (8 8.5) to 118% (108.5) of the GT input. Stated differently, DETECT-TONE must be within -6/+18% of GT. The LCA can insert tones onto the TDM bus via the tone generator. The tone generator consists of a shift register and some control circuitry. To generate a tone, the software loads a tone sample into the tone generator shift register. That tone sample will be clocked out onto the TDM bus during the boards next TDM slot, via the TONE-DATA signal. The tone is generated at the expense of the microphone audio, as only one of them can be clocked out onto the TDM bus at a time. The switch between microphone audio and tone audio is made by mux gate U531. This gate is controlled by the signal MUX-CNTRL, which is sourced by the tone generator. MUX-CNTRL changes state immediately after the boards TDM slot to properly coordinate the switch from mic to tone and vice-versa. The tone generator enable bit controls the overall execution of the tone generator. When this bit is 0, the tone generator is disabled. When enabled, the tone generator generates an interrupt after each TDM slot, notifying the software that it needs to load the shift register. Additionally, the LCA provides an interface between the microprocessor and the audio multiplexer via the LB-SELA and LB-SELB outputs of Port A. These outputs control the gating of system guard tone directly into the check tone filter and into the CODEC for diagnostic tone detection and the gating of operator microphone audio into the CODEC.
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Chapter 10
Slot receiver circuitry

This circuitry can be broken down into two parts: TDM Bus Interleaving/FIFO interface and AEI Control word/DSP Interface State Machine. The TDM Bus Interleaving/FIFO interface multiplexes the three TDM mux busses onto one serial output bus. This serial output bus is sent to an external serial FIFO for temporary storage until a DSP can read the TDM slots and process the audio information. The serial output bus is clocked out at a 6 MHz bit rate. Synchronization, loading and outputting of serial data is controlled by logic within the LCA. The TDM Bus Interleaving/FIFO interface includes SClk, SData, Delayed Frame Sync, FIFO Write, Analog Mux select 0 and 1, Mux Output enable and DAC Latch enable. SClk is a 7.5 MHz signal which is gated for 24 clocks every 31.25 S. SData is the resulting data onto the serial output bus clocked out at the SClk rate. Delayed Frame Sync is a delayed version of the Frame Sync strobe which resets the time slot counter, identifying the start of a new frame of 96 serial audio time slots. FIFO Write indicates to the FIFO that the interleaved data into the FIFO has changed from the CEBs Mux bus 1 to Mux bus 2, etc. This gives an indication of what data is being processed within the interleaved burst of serial audio data. Analog Mux select 0 and Mux select 1 cycle the Analog Mux U105 through Select, Unselect, Monitor 1 and Monitor 2 output channels. Mux Output enable disables the Analog Mux U105 during transitions between output channels, preventing a channel from inadvertently being driven out of turn during Mux Select transitions. Finally, DAC Latch enable loads the external DAC with data destined for a particular output channel. DAC Latch occurs four times per frame or once every 31.25S. The AEI Control word/DSP Interface State Machine mimics the AEI communication protocol used in older CENTRACOM Series II systems. The AEI Control word/DSP Interface State Machine generates an interrupt output, DSP_IRQA, to the DSP. This interrupt, along with existing AEI control information within the LCA, allows the DSP56166 to support the AEI communication protocol.
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DSP56166 and peripherals

The DSP56166 provides eight functions for audio processing:
p p p p p p p p
PCM -law to linear conversion Volume control of the linearized audio slot sample Summing the current slot sample to one of the four output samples Overhead functions Send output channel sum to external DAC for conversion Frame synchronization Support AEI communications protocol Initialization
PCM -law to linear conversion

The DSP converts PCM -law to linear to allow a compressed, eight bit -law sample to enter the DSP and leave as a 13-bit linear sample that the external DAC can convert to an analog sample. This occurs three times per slot (every 1.3S) and requires a table lookup within the code for a linear value.
Volume control of the sample

Volume control on the linearized audio slot sample occurs three times per slot (every 1.3S). This function includes: reading and masking slot control word, setup for output channel summing, and multiplying by an equivalent volume control factor read from a table.
Summing the slot sample

Summing of the current slot sample can occur to any one of the four output channels. This function does not allow one sample to go to more than one output channel. Summing occurs three times per slot (every 1.3S) and includes reading in output channel, summing and saving.
Overhead functions
Overhead functions include: Polling FIFO empty flag for new sample, looping, and enabling/disabling interrupts.
Analog conversion
Sending the output channel sum to an external DAC for analog conversion occurs four times per frame (every 31.25S).
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Frame synchronization
Frame synchronization occurs once per frame (every 125S). This functions includes: moving accumulated channel sums to an output buffer, zeroing sums for new frame and sending tone test channel to the CODEC. Tone testing requires receiving and reconstructing a 2175 Hz tone and passing it to a detection circuit on the LCA.
AEI communication protocol

The DSP56166 follows the AEI communication protocol in order to insure backward compatibility within CENTRACOM Gold Series systems. The control interface for AEI communications follows this sequence:
1.
The microprocessor writes to the DUART and then the LCA to select an AEI and the TSAC (S1=0, S0=0). The microprocessor writes the time slot whose control word is being modified into the AEI data shift register on the LCA. The microprocessor writes an 8-bit word to the LCA into a shift register. This word contains the slot number of the new (changed) control word. A LCA shift register serially outputs the 8 data bits to all AEIs in the system. After the 8 bits are shifted out of the LCA, the LCA interrupts the DSP by strobing its IRQA input. The DSP then generates a 15 MHz, eight cycle gated clock into the LCA RSSI_CLK input. A second LCA shift register, which contains the same information as that shifted out to the AEIs, then serially outputs the time slot at a 15 MHz rate into the DSP's RSSIO port. The DSP interrupt routine determines the slot number for the new control word by reading S0 and S1, and saves the slot number. The microprocessor must wait a minimum of 17.36 S. The microprocessor writes to the DUART and/or LCA, deselecting AEI Board 0. The microprocessor writes an 8-bit word to the LCA containing new control information. These 8 bits are clocked serially out of the LCA to the AEIs in the system. The bit rate is 460.8 kHz. The microprocessor must wait a minimum of 17.36 S. The microprocessor again writes to the DUART to set AEI Group Select to 0 (AEI Group 0-3). The microprocessor writes to the LCA, setting AEI Select lines S2 and S3 to 0, selecting AEI board 0. This time, S0 and S1 are set to 01, 10 or 11, selecting Slot Receiver A, B or C. This defines the slot receiver the control word is intended for. Once this occurs, the LCA interrupts the DSP by strobing its IRQA input. Upon reception of IRQA, the DSP generates a 15 MHz, eight cycle gated clock into the LCAs RSSI_CLK input. A second LCA shift register, which contains the same information as that shifted out to the AEIs, then serially outputs the control word at 10-15
2.
3.
4.
5.
6. 7. 8.
9.
10. 11.
12.
13.
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a 15 MHz rate into the DSPs RSSIO port. The DSP interrupt routine reads S0 and S1, and determines it has been sent the control word for slot receiver A, B or C. It then saves this control word into the previously sent time slot for the currently selected slot receiver.
14.
The microprocessor must wait a minimum of one frame (125 S) for the change to take effect before it can begin to process another change. The DSP initialization takes place after the DSP exits the Bootload state, where the internal 2K X 16 program memory has been loaded. During initialization, the PLL is programed to 60 MHz, the RSSI ports are set up and the -to-lin table is moved from program memory to internal data memory. The GPIO input on port C is also read to determine if audio outputs may be driven to full mute (>-42dB) or limited to -42dB attenuation for operator position volume level 7.
15.
Audio output circuitry

The audio output circuitry is sourced by DAC U104, driven four times per 8 kHz frame. The DAC receives a 13 bit linear sample and converts it to an analog signal up to 3 V for a duration of 31.25 S. While the DAC is driving out an analog signal, it is receiving a new digital sample designated for the next output channel. The next output channel is determined by Analog Mux U105. The Mux is constantly cycling through its four outputs (Select, Unselect, Mon1 and Mon2) at a rate of one channel every 31.25 S. This cycling is determined by control inputs MUX_SEL0 and MUX_SEL1. Slightly before and after a transition from one channel to the next, LCA output MUX_OE is driving the Mux's output enable. This temporarily disables an output from being driven during a DAC/MUX channel transition, preventing crosstalk from an unwanted channel. The audio through Mux U105 is then passed through a single pole, low pass filter with a 3dB rolloff at 38 kHz. This path is terminated with a 1.5K resistor, providing a low impedance path for noise. The audio path is then AC coupled into a current driver section. In order to pass signal levels consistent with AEIs, the current driver attenuates the low-pass output by 12dB. There are four op-amps driving four 1:1 transformer outputs. The balanced output of each transformer secondary connects to a speaker input at the operator's console, while being used as a designated speaker output. Each output is configured to provide some filtering to the audio. The poles and zeros provide a relatively flat gain in the range of 300 to 3200 Hz. The current driver then drives the operator link with typical signal levels of -14.4dBm. The Monitor 2 output has a jumper settable reconstruction filter. This filter provides signal reconstruction to the 25% duty cycle signal which typically drives the operator link. The reconstruction filter is used for headset applications. The COIM slot receiver also generates an error beep when an the operator makes an error. This 1087 Hz tone is routed to the Select speaker. When the DUART (or OMI bus) pulls pin 53 low, U109 is enabled and divides the GT signal (2175Hz) by two. This output is summed to the Select path and driven to the operator position. The beep tone output of the select transformer is -20.0 dBm when the operator link is loaded.
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Chapter 10
The COIM slot receiver can also generate a 2175 Hz tone on the LCA Tone Detect Output circuit. This allows the COIM to test various modules in the system for audio integrity. In order to check audio paths, the COIM puts a tone in a particular slot on the Mux bus. It then programs the slot receiver or AEI to listen to that slot at full volume. This output provides a small amount of filtering and is driven on the Tone Detection circuit at a level of -14.4 dBm.
Voltage regulation and power fail

Switching regulator VR1 supplies 5 V power to the COIM. The microprocessor and its PALs, oscillator, reset circuitry, DSP and its peripherals, VR5, VR6, memory and miscellaneous peripherals are all powered by 5V. Regulators VR3 and VR4 supply 12 V power. Two separate regulators are used in order to isolate the analog audio circuitry from the switching noise generated by the 12 V logic. VR3 powers the 12 V logic and VR4 powers the audio circuits. The circuitry supplying the two 12 V regulators guards against an SCR condition in the CMOS logic. This circuitry will automatically remove the raw 15 V power from the inputs of the regulator in the event of excessive current draw. The circuitry reapplies power after a short interval. If the SCR condition has not been eliminated, the circuitry will once again remove power, and the process will continue in an attempt to correct the problem. Regulators VR5 and VR6 supply -5 V to the COIM. VR5 powers the audio output negative supplies of DAC U104, analog MUX U105 and op amp U110. VR6 powers the negative supplies of op amps U111, U112 and U113. The -5 V loads are distributed roughly equally between the two regulators. All the voltage regulators use copper pads on the board as heat sinks. The microprocessor monitors two power fail signals. PF1 is generated by the system power supplies. It signals the failure of a system power supply, or it can also signal a mains failure in the case of a battery backed system. This signal is input to the LCA. It is then passed to the DUART as PF-RDY-BSY, which is a dual function signal. Upon power up, PF-RDY-BSY controls data transfers to the LCA. During normal operation, it indicates the status of PF1. The microprocessor reads the DUART to determine the status of PF-RDY-BSY. The 12V-FAIL signal is generated on board and signals the failure of the regulator for the 12V logic. This signal is input directly to the DUART, where it is read by the processor. 12V_FAIL also controls the green status LED DS2. In the event of a 12 V failure, it causes DS2 to flash. However, if the board is in tristate or reset, the flashing of DS2 will be preempted.
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LCA Pin Descriptions

Refer to Table 10-5 for a description of each pin of U524.
Table 10-5
LCA U524 Pin Descriptions

Name Ground VCC IPL2 DBSY RXE IPL1 IPL0 TXn DUART-IRQ MUX_OE CLK PWRDWN
Device ground pin Device power pin. Output - One of three microprocessor interrupt priority lines Input - System DBSY signal used for generating DBSY interrupt Output - Receive enable signal from the TSAC Output - One of three microprocessor interrupt priority lines Output - One of three microprocessor interrupt priority lines Output - Transmit enable signal from the TSAC. Goes low during the BLN7061As TDM slot Input - Duart interrupt request Output- Audio multiplexer output enable Input - System TDM bit rate clock used by the TSAC and for delaying the A4 interrupt Dedicated control pin used to activate a low power standby mode Input - One of three microprocessor address lines used for accessing the LCA ports Output - Transmit Data Enable used by the CODEC Output- AEI serial clock Input - One of three microprocessor address lines used for accessing the LCA ports Output - One of two outputs used for controlling the audio mux Output- AEI serial data Input - Data grant signal used for transmitting data on the system data bus. Output- Delayed Frame sync output Device ground pin Device power pin Input - System frame synchronization signal used by the TSAC Output- Latch external DAC output Input - Reset signal used for initiating diagnostic tone tests Input - Squared-up signal out of the check tone filter used for diagnostic tone detection Input- DSP driven gated clock for Control Word Interface Input - System guard tone used for diagnostic tone detection Input- Audio TDM Bus 3 Input- Audio TDM Bus 2
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Description
PA0
TDE SHIFT-CLK uPA1 LB-SELA SHIFT-DATA DG D_FS Ground VCC A4 LDAC TND-RESET DETECT-TONE RSSI_CLK GT MUXBUS_3 MUXBUS_2
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Chapter 10
Table 10-5
LCA U524 Pin Descriptions (continued)

Name M1 M0 M2 HDC MUXBUS_1 LDC MUX_SEL0 MUX_SEL1 TSAC-SEL SER_DATA PF_INIT Description
Dedicated control input. One of three device mode control lines. Dedicated control input. One of three device mode control lines. Input - One of three device mode control lines Output - Control pin held high during configuration Input- Audio TDM Bus 1 Output - Control pin held low during configuration Output- External Analog Mux select Output- External Analog Mux select Input - Register select line for programming the TSAC Output- Serial FIFO data Dual function pin. Output control pin held low during device power stabilization and clearing of internal memory. Input for system power fail signal after the device is configured Device power pin Device ground pin Output- Control Word data destined for DSP RSSI0 port Output- FIFO write strobe output Output- DSP Interrupt Request A Input - General purpose clock used for generating the 18ms interrupt and AEI-CLK Input- AEI 4 board group select Output - One of four lines used for selecting one of four AEIs to program and one of four devices on the AEI to access. Input - Status lead indicating the active system timer. Output - One of four lines used for selecting one of four AEIs to program and one of four devices on the AEI to access Output- FIFO shift register clock Input- 15MHz clock Dedicated input control signal used in conjunction with the PROG_ input for device reconfiguration Dedicated open-drain input/output control pin which is used in conjunction with the RESET_ input to activate device reconfiguration Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Output- /15MHz clock Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Output - One of four lines used for selecting one of four AEIs to program and one of four devices on the AEI to access Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Input - Chip select used for programming the LCA
Pin
31 32 33 34 35 36 37 38 39 40 41
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
VCC Ground RSSI0_DATA FIFO_WR DSP_IRQA DUART-CLK A-GRP-SEL S3 A-B_STATUS S2 SER_CLK XIN RESET PROG uPD31 XOUT uPD30 S1 uPD29 CS0
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Table 10-5
LCA U524 Pin Descriptions (continued)

Name uPD28 S0 VCC Ground uPD27 CS1 uPD26 TONE-DATA uPD25 PF-RDY-BSY Description
Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Output - One of four lines used for selecting one of four AEIs to program and one of four devices on the AEI to access Device power pin Device ground pin Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Input - Chip select used for programming the LCA Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Output - PCM tone clocked out by the tone generator Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Dual function pin. Output control pin used during configuration to signal a ready status to receive more configuration information. Output after configuration reflecting the inverted state of the PF_INIT input Input/Output - One of eight microprocessor data lines used for programming the LCA and accessing its ports Unused I/O Dedicated device control line with various purposes, depending on the mode of operation. Unused in this application. Input - Select line from microprocessor for accessing LCA ports Input - Chip select used for programming the LCA Input - Receive data from the CEB system data bus. Output - Used to switch between CODEC audio and tone generator tones. Output - One of two outputs used for controlling the audio mux Output - Transmit data to the CEB system data bus Input - Data clock used for system data bus transfers Output- latch read Input - One of three microprocessor address lines used for accessing the LCA ports Input - R/W line from microprocessor used for the LCA ports
Pin
62 63 64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79 80 81 82 83 84
uPD24 UNUSED0 CCLK XLX-SEL CS2 CEB-RX-DATA MUX-CNTRL LB-SELB CEB-TX-DATA DC TDM_ADD_RD uPA2 uPR-W
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Console Operator Interface Module Jumper tables
Jumper tables
Table 10-6
Configurable jumpers
Description
Watchdog control
Reference designation
JU1
Configuration
IN: Disable watchdog timer OUT: Enable watchdog timer
JU2
Cache control
IN: Disable microprocessor cache OUT: Enable microprocessor cache
JU10
Audio Mute
IN: Full Audio Mute OUT: -42dB Audio Mute
JU100 JU101 JU211
MON 2 Filter MON 2 Filter U213 EEPROM size
A: No Mon 2 filter B: Mon 2 filter in A: 256k bit EEPROM selection B: 1M, 2M, 4M EEPROM
JU212
U213 EEPROM size
A: 256k bit EEPROM selection B: 1M, 2M, 4M EEPROM
JU213
U213 EEPROM size
A: 256k bit EEPROM selection B: 1M, 2M, 4M EEPROM
JU214
Vote for system timer
IN: Enable voting OUT: Disable voting
JU500
Busy Bus Selection
B1: Busy 1 (TDM address 0-1F) B2: Busy 2 (TDM address 20-3F) B3: Busy 3 (TDM address 40-5F)
JU501
Mux Bus Selection
MB1: Mux Bus 1 (TDM address 0-1F) MB2: Mux Bus 2 (TDM address 20-3F) MB3: Mux Bus 3 (TDM address 40-5F)
Note:
For Elite ops, the address dip switch on the COIM is S500 and the last switch (switch 8) must be set to "1" (one) or "off."
Fixed Jumpers
Description
Data bus grant removal Data bus grant removal
Table 10-7
Jumper
JU502
Configuration
IN: (Default) Tristate line (TS) removes data grant. OUT: Data request line removes data grant with JU503 in. IN: Data request line removes data grant. OUT: (Default) Tristate line (TS) removes data grant with JU502 in. IN: CODEC performs A-Law conversion. OUT: (Default) CODEC performs -Law conversion.
JU503
JU504
Mu-law/A-law conversion select
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Jumper tables
Table 10-8
COIM Fixed Jumper Table

Description
U212 EEPROM size
Jumper
JU208
Configuration
*IN: 1M EEPROM OUT: 256k EEPROM
JU209
U212 EEPROM size
JU210
U212 EEPROM size
JU228
U212 EEPROM size
*OUT: 1M EEPROM IN: 256k EEPROM
JU229
U212 EEPROM size
JU230
U212 EEPROM size
* denotes default
Table 10-9
SIMM Board Fixed Components

Firmware Topology EPROM or OTPROM 27C010 27C020 27C040 12V Flash 28F010 28F020 5V Flash 29F010 29F040
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 C9 C10 C11
OUT OUT OUT OUT IN IN IN IN OUT OUT IN IN IN IN
IN IN IN IN OUT OUT OUT OUT OUT IN OUT IN IN IN
IN IN IN IN OUT OUT OUT OUT IN OUT OUT OUT OUT OUT
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Console Operator Interface Module Jumper tables
Table 10-9
SIMM Board Fixed Components (continued)

Firmware Topology EPROM or OTPROM 27C010 27C020 27C040 12V Flash 28F010 28F020 5V Flash 29F010 29F040
C12 C13 C14 C15 C16
IN IN IN IN IN
IN IN IN IN IN
OUT IN IN IN IN
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Troubleshooting
Troubleshooting
This section is a guide to tracing the cause of simple problems with the COIM board. More serious problems, such as faulty ICs, are best handled by qualified technicians at the Motorola System Support Center. The COIM has two pairs of red and green LEDs. The upper pair reflect the operating condition of the DSP56166. The lower pair indicate microprocessor operating condition. Generally, the green DSP LED will light more quickly than the green microprocessor LED because of quicker boot loading. The DSP LEDs have only two states: On or Off (they do not flash). The DSPs green LED is controlled by the reception of a frame sync interrupt from the LCA. If the LCA is not programmed correctly, this signal will not be available and the red DSP status LED remains lit. Table 10-10 describes COIM failures as indicated by the four status LEDs.
Table 10-10
COIM Troubleshooting Guide

POSSIBLE CAUSE/CORRECTIVE ACTION
DSP failed LCA failed Improperly installed DSP ROM Improper firmware version PAL failure Improperly installed PROMs Other microprocessor-related failure Software diagnostic failure. Check for: bad or improperly installed PROMS failed RAM failed LCA 12 V power failure EEPROM(s)/PersPROMs PROM blank or corrupted. Check 9 V and 15 V power supplies. Check microprocessor oscillator. Board is in tristate. Check for a valid DIP switch address.
LED INDICATION
Upper Red LED on Lower Green LED on
Lower Red LED flashing twice per second Lower Green LED off: Lower Red LED flashing at a rate other than 2 flashes per second Lower green LED off: Lower Green LED flashing Lower Red LED off Lower Green LED flashing, Lower Red Led on ALL LEDs off. Both Red LEDs always lit.
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Console Operator Interface Module Troubleshooting
Table 10-10
COIM Troubleshooting Guide (continued)

POSSIBLE CAUSE/CORRECTIVE ACTION
Check data transmit path from U214-13 to card edge pins 67 and 68. Check data receive path from card edge pins 69 and 70 to U214-11. Check that the associated RS-232 board is model BLN6755C. Check data transmit path from U214-13 to card edge pins 67 and 68. Check data receive path from card edge pins 69 and 70 to U214-11. Check cable between operator position and CEB. With the console in intercom mode, check for mic audio at card edge pins 57 and 58. If no audio is present: Check operator position Check between OP and CEB. If audio is present: trace the signal through transformer T500 and analog mux U528 to CODEC U515-3. If audio is present at U515, make sure that the Busy Bus and Mux Bus jumpers are installed properly. Verify that the following signals are present at U515 pins: 2 MHz clock - pin 12 Slot Enable - pin 10 6 Vdc - pin 1 Check the digital audio path from U515-11 through U531, U503, U505, and the bus driver circuitry. If this path is OK, the audio problem is not on the COIM.
LED INDICATION
No data to/from console operator position, or operator position indicates link down. No data to/from trunking central controller
No microphone audio being sent to the base station.
COIM does not log into the system
Verify that Busy Bus jumper is properly installed. Verify that the transmit enable signal from the LCA TXE output is present and trace this signal through U517, U501, U505, and U503, to the three-state enable of U505. Verify the DRDY signal path from U505 to card edge pin 93. Verify the CEB transmit data path from the LCA
CEB-TX-DATA output to card edge pin 86. Verify that the SWA+ and switched ground signals are present in
the bus driver circuitry. COIM logs into system but later drops out. No other boards are in the system or there is a problem with the CEB receive data path. Check for activity on card edge pin 86 and trace this signal to the LCA CEB-RX-DATA input.
68P81095E 50- A 11/30/ 2000
10-25
Chapter 10
Troubleshooting
10-26
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 10
Console Operator Interface Module BLN7061A Overlay
68P81095E 50- A 11/30/ 2000
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Chapter 10
10-28
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Chapter 10
Console Operator Interface Module BLN7061A Schematic

(Sheet 1 of 5)
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Chapter 10

(Sheet 2 of 5)
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Chapter 10
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Chapter 10

(Sheet 3 of 5)
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Chapter 10

(Sheet 4 of 5)
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Chapter 10
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Chapter 10

(Sheet 5 of 5)
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Chapter 10
10-38
6 8 P 8 1 0 9 5 E5 0 - A 1 1 /3 0/ 20 0 0
Chapter 10 Console Operator Interface Module BLN7061C Parts List
BLN7061C Parts List

Reference
Description
Reference
Description
capacitor, fixed:
C100 C101 C102 C103 C104 C106 C107,108 C109 thru 111 C112 thru 115 C116 thru 119 C120 C121,122 C160,161 C170 C200,201 C202 C203 C204 C210,211 C500 C501 C502 C503 C504 C505 C506,507 C508 C509,510 C511 C512 C513 C514 C515 C516 C517,518 C519 C700 thru 702 C830 thru 833 C840 thru 843 C850 C852 thru 855 C857 thru 874 C880,881 C882 C883 thru 885 C890 thru 892 C893 C894 C900 thru 904 C906 C907 C909 C910,911 C913 C914,915 C916 thru 918 C919 C920 thru 922 C924,925 C926 C928,929 C930 thru 932 2113740A55 2113741A45 2311049A45 2113741A45 2311049A45 2113740A55 2113741A61 2113740A55 2113741A61 2113740A48 2113741A61 2113741A45 2113741A61 2113741A61 2113740B34 2113740B49 2113740B42 2113740B49 2113741A45 2113740B73 2113741B37 2113743G21 2113740B34 2113741A45 2113740B73 2380090M24 2113741B61 2113740B73 2113741A45 2113740B73 2113741A45 2113741B45 2113741A45 2113740B53 2113741A45 2113740B73 2113740B49 2113741A45 2311049A45 2113741A45 2113741A45 2113741A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2311049A08 2113741A45 2311049A45 2311049A45 2380090M07 2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 100 pF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 100 pF, 5%; 50 V 0.047 uF, 5%; 50 V 100 pF, 5%; 50 V 0.047 uF, 5%; 50 V 51 pF, 5%; 50V 0.047 uF, 5%; 50 V 0.01 uF, 5%; 50 V 0.047 uF, 5%; 50 V 0.047 uF, 5%; 50 V 24 pF, 5%; 50V 100 pF, 5%; 50 V 51 pF, 5%; 50V 100 pF, 5%; 50 V 0.01 uF, 5%; 50 V 1000 pF, 5%; 50 V 4700 pF, 5%; 50 V 1 uF, +80%/-20%; 16V 24 pF, 5%; 50V 0.01 uF, 5%; 50 V 1000 pF, 5%; 50 V 10 uF, 20%; 50 V 0.047 uF, 5%; 50 V 1000 pF, 5%; 50 V 0.01 uF, 5%; 50 V 1000 pF, 5%; 50 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 150 pF, 5%; 50V 0.01 uF, 5%; 50 V 1000 pF, 5%; 50 V 100 pF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 1 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 10 uF, 10%; 35 V 47 uF, 20%; 16 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V
C933 thru 939 C940 thru 942 C943 thru 945 C946 C947,948 C950,951 C952 C953 C955 C956 thru 958 C960 C961 C962 C964 C965,966 C968 C969,970 C971 thru 974 C975,976 C977 C979,980 C981 C982 C984 thru 986 C988 C989 thru 991 C993 C995, 996 C997 thru 999
2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2113741A45 2311049A45 2113741A45 2113741A45 2113741A45 2311049A45
0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 0.01 uF, 5%; 50 V 10 uF, 10%; 35 V
diode: (see note)

CR1 CR3 CR5,6 CR100 CR200 CR500 CR501 thru 504 CR505 CR506 CR700 thru 702 CR900 CR902 thru 904 D1, 2 4805129M72 4813833C10 4813833C10 4813833C10 4813833C10 4882290T04 4813833C10 4813833C07 4882290T04 4813833C10 4813833C10 4813833C10 4813833B01 Schottky type 0.1A, 70 V 0.1A, 70 V 0.1A, 70 V 0.1A, 70 V Diode; hot carrier 0.1A, 70 V Diode, dual 100 W Diode; hot carrier 0.1A, 70 V 0.1A, 70 V 0.1A, 70 V
unknown
Schottky type

DS1 DS2,3 DS4 F1 F2 4882198T01 4882198T03 4882198T01 6505663R04 6505663R01 RED GRN RED
fuse:
4 AMP 1A, 60V
jumper:
JU208 thru 210 JU502 0611079A01 0611079A01 0 , 5%; 1/10 W 0 , 5%; 1/10 W
68P81095E 50- A 1/18/ 01
10-39
connector:
P3 0984527T05 socket, 80 position

Q1 Q2,3 Q100 thru 103 Q200 Q201 Q202 Q203 Q500,501 Q502,503 Q504 Q700 Q701 Q702 Q703 Q704 Q705 Q900 thru 902 4813824A22 4813824A13 4813824A13 4880141L03 4813824A09 4880141L03 4813824A09 4813824A13 4813824A10 4813824A13 4880141L03 4813824A09 4880141L03 4813824A09 4880141L03 4813824A09 4880141L03 PNP NPN NPN PNP NPN PNP NPN NPN NPN NPN PNP NPN PNP NPN PNP NPN PNP
resistor, fixed:
R1 thru 5 R6 R7 R9 R10 R15,16 R20 R21 R23 thru 28 R29,30 R31 thru 33 R34,35 R37 R39 R40 thru 48 R50 thru 52 R100 thru 105 R107 thru 113 R115 thru 121 R122,123 R124,125 R129 R130 R131 R132 R133 R134,135 R136,137 R138,139 R140,141 R142 thru 147 R148 thru 151 R152 thru 155 R160,161 R162 R163,164 R165,166 R167 R168 R169 R170 R172 R173 R174,175 R180 R181 R182 thru 187 R190 thru 193 R194, 195 R200 R201,202 0611079A74 0611079A82 0611079B07 0611079A98 0611079B07 0611079A98 0611079A98 0611079B03 0611079A98 0611079A82 0611079A98 0611079A01 0611079A01 0611079A01 0611079A98 0611079A98 0611079A98 0611079A98 0611079A98 0611079B15 0611079B23 0611079A90 0611079B13 0611079B11 0611079B13 0611079B19 0611079B13 0611079B29 0611079B11 0611079B29 0611079B11 0611079A54 0611079A78 0611079A74 0611079B07 0611079B15 0611079A74 0611079B07 0611079A98 0611079A74 0611079B23 0611079B15 0611079B47 0611079B11 0611079A98 0611079A91 0611079A98 0611079A78 0611079A98 0611079A70 0611079A94 1K, 5%; 1/10 W 2200 , 5%: 1/10 W 22, 5%; 1/10 W 10, 5%; 1/10 W 22, 5%; 1/10 W 10, 5%; 1/10 W 10, 5%; 1/10 W 15K, 5%; 1/10 W 10K, 5%; 1/10 W 2200, 5%: 1/10 W 10K, 5%; 1/10 W O , 5%; 1/10 W O , 5%; 1/10 W O , 5%; 1/10 W 10K, 5%; 1/10 W 10K, 5%; 1/10 W 10K, 5%; 1/10 W 10K, 5%; 1/10 W 10K, 5%; 1/10 W 47K, 5%; 1/10 W 100K, 5%; 1/10 W 4700 , 5%; 1/10 W 39K, 5%; 1/10 W 33K, 5%; 1/10 W 39K, 5%; 1/10 W 68K, 5%; 1/10 W 39K, 5%; 1/10 W 180K 5%; 1/10W 33K, 5%; 1/10 W 180K 5%; 1/10W 33K, 5%; 1/10 W 150 , 5%; 1/10 W 1500 , 5%; 1/10 W 1K, 5%; 1/10 W 22K, 5%; 1/10 W 47K, 5%; 1/10 W 1K, 5%; 1/10 W 22K, 5%; 1/10 W 10K, 5%; 1/10 W 1K, 5%; 1/10 W 100K, 5%; 1/10 W 47K, 5%; 1/10 W 1 M, 5%; 1/10 W 33K, 5%; 1/10 W 10K, 5%; 1/10 W 5100 , 5%; 1/10 W 10K, 5%; 1/10 W 1500 , 5%; 1/10 W 10K, 5%; 1/10 W 680 , 5%, 1/10 W 6800 , 5%; 1/10 W
R203 thru 205 R206 R207 R208 R209,210 R211 thru 213 R214 R215 R216 R217,218 R219 R221 R222 R224 R225 R226 thru 249 R400 thru 407 R500,501 R502,503 R504,505 R506 thru 508 R509 R510,511 R512,513 R514 R515,516 R517 R518 R519 R520,521 R522 R523 R524 R525 R526 R527 R528 thru 530 R531 R532 R533 R534 R535 R536 R537 R538 R539 R540 R541 R542 R543 R544 R545 R546 R547 R548 R549 R550 R551 R552 R553 R554 R555 R556 R557 R558 R559 R560,561 R562 thru 565 R567 thru 569 R570,571 R572 R573 R574 R575 thru 577 R578,579 R580 thru 583
0611079A98 0611079A42 0611079A74 0611079A98 0611079A74 0611079A98 0611079B47 0611079A74 0611079A98 0611079A66 0611079A74 0611079B07 0611079A98 0611079A42 0611079A90 0611079A98 0611079B07 0611079A90 0611079B47 0611079A90 0611079B47 0611079A90 0611079B47 0611079A68 0611079A98 0611079A84 0611079A98 0611079A74 0611079B07 0611079B03 0611079B07 0611079B03 0611079A68 0611079A82 0611079B03 0611079A74 0611079B07 0611079B15 0611079A82 0611079B23 0611079B07 0611079A90 0611079A74 0611079A90 0611079A26 0611079A86 0611079B23 0611079A90 0611079G18 0611079A74 0611079B47 0611079B03 0611079G84 0611079G01 0611079G84 0611079B15 0611079B03 0611079A98 0611079B07 0611079A98 0611079B37 0611077B43 0611079B15 0611079A98 0611077B43 0611079A74 0611079B47 0611079A66 0611079A66 0611079B07 0611079B03 0611079A82 0611079B07 0611079A91 0611079A86 0611079A98
10K, 5%; 1/10 W 47 , 5%; 1/10 W 1K, 5%; 1/10 W 10K, 5%; 1/10 W 1K, 5%; 1/10 W 10K, 5%; 1/10 W 1 M, 5%; 1/10 W 1K, 5%; 1/10 W 10K, 5%; 1/10 W 470 , 5%; 1/10 W 1K, 5%; 1/10 W 22K, 5%; 1/10 W 10K, 5%; 1/10 W 47 , 5%; 1/10 W 4700 , 5%; 1/10 W 10K , 5%; 1/10 W 22K, 5%; 1/10 W 4700 , 5%; 1/10 W 1 M, 5%; 1/10 W 4700 , 5%; 1/10 W 1 M, 5%; 1/10 W 4700 , 5%; 1/10 W 1 M, 5%; 1/10 W 560 5% 1/10 W 10K, 5%; 1/10 W 2700 , 5%; 1/10 W 10K, 5%; 1/10 W 1K, 5%; 1/10 W 22K, 5%; 1/10 W 15K, 5%; 1/10 W 22K, 5%; 1/10 W 15K, 5%; 1/10 W 560 5% 1/10 W 2200 , 5%: 1/10 W 15K, 5%; 1/10 W 1K, 5%; 1/10 W 22K, 5%; 1/10 W 47K, 5%; 1/10 W 2200 , 5%: 1/10 W 100K, 5%; 1/10 W 22K, 5%; 1/10 W 4700 , 5%; 1/10 W 1K, 5%; 1/10 W 4700 , 5%; 1/10 W 10 , 5%; 1/10 W 3300 , 5%; 1/10 W 100K, 5%; 1/10 W 4700 , 5%; 1/10 W Resistor chip 15.0K 1/10 W 1% 1K, 5%; 1/10 W 1 M, 5%; 1/10 W 15K, 5%; 1/10 W RES CHIP 73.2K 1/10W 1% 0805 10K, 1%; 1/10 W RES CHIP 73.2K 1/10W 1% 0805 47K, 5%; 1/10 W 15K, 5%; 1/10 W 10K, 5%; 1/10 W 22K, 5%; 1/10 W 10K, 5%; 1/10 W 390K, 5%; 1/10W 680K, 5%; 1/8 W 47K, 5%; 1/10 W 10K, 5%; 1/10 W 680K, 5%; 1/8 W 1K, 5%; 1/10 W 1 M, 5%; 1/10 W 470 , 5%; 1/10 W 470 , 5%; 1/10 W 22K, 5%; 1/10 W 15K, 5%; 1/10 W 2200 , 5%: 1/10 W 22K, 5%; 1/10 W 5100 , 5%; 1/10 W 3300 , 5%; 1/10 W 10K, 5%; 1/10 W
10-40
6 8 P 8 1 0 9 5 E5 0 - A 1 /18 /0 1
R584 R585,586 R587 thru 591 R595 thru 597 R598 R599 R600 thru 607 R700 thru 702 R703 thru 705 R706 thru 708 R900 R901,902 R903,904 R905,906 R907 R908
0611079A74 0611079A82 0611079A90 0611079B47 0611079A98 0611079A91 0611079A98 0611079A58 0611079A74 0611079A42 0611079A90 0611079A98 0611079A26 0611079A90 0611079A78 0611079A64
1K, 5%; 1/10 W 2200 , 5%: 1/10 W 4700 , 5%; 1/10 W 1 M, 5%; 1/10 W 10K, 5%; 1/10 W 5100 , 5%; 1/10 W 10K , 5%; 1/10 W 220 , 5%; 1/10 W 1K, 5%; 1/10 W 47 , 5%; 1/10 W 4700 , 5%; 1/10 W 10K, 5%; 1/10 W 10 , 5%; 1/10 W 4700 , 5%; 1/10 W 1500 , 5%; 1/10 W 390 , 5%; 1/10 W
U523 U524 U528 U530 U531
5113808A41 5185227U01 5113806A19 5113818A01 5113806A19
Line Driver/Receiver Octal CMOS Field Programmable Gate Array Dual 4-Channel Analog Multiplexer/ Demultiplexer IC LOW COST SING SPLY LM2904DR Dual 4-Channel Analog Multiplexer/ Demultiplexer

VR3,4 VR5,6 5113816A09 5184632T01 12-Volt Positive Regulator Switch-Capacitor Voltge Converter
crystal: (see note)

Y1 Y200 4883568T03 4884450T02 OSC XTAL CLOCK 15.0MHZ 3.6864 MHZ
switch:
S1 S500 4083621T01 4083706T01 pushbutton, spst dip: multiple position, slide type
0310943J09 0913900A13 0982451V13 0983657T01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 0984728L01 2880001R02 2880001R02 2880001R03 2880001R03 2880001R03 2880001R03 2880001R03 2880001S03 2880001S03 5482006W01 5482006W02 5583323P01 Screw, tapping: TT3 x 0.5 x 6 (2 used) SOCKET, 32 position (used with U102) SOCKET, IC 32 PIN SM T & R (used with U212) socket, 114-position (used with U1) Shorting Jumper: 2-contact (used with JU10) Shorting Jumper: 2-contact (used with JU100) Shorting Jumper: 2-contact (used with JU101) Shorting Jumper: 2-contact (used with JU211) Shorting Jumper: 2-contact (used with JU212) Shorting Jumper: 2-contact (used with JU213) Shorting Jumper: 2-contact (used with JU214) Shorting Jumper: 2-contact (used with JU500) Shorting Jumper: 2-contact (used with JU501) plug: 2-pin header (used with JU10) plug: 2-pin header (used with JU214) plug: 3-pin header (used with JU100) plug: 3-pin header (used with JU101) plug: 3-pin header (used with JU211) plug: 3-pin header (used with JU212) plug: 3-pin header (used with JU213) plug: 6-contact (used with JU500) plug: 6-contact (used with JU501) Label, PCB barcode ribbon, thermal transfer Handle, circuit board
transformer:
T100 thru 103 T500 2584007C04 2584007C04 TRANSFORMER, AUDIO SMT TRANSFORMER, AUDIO SMT

U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U16 U100 U101 U102 U103 U104 U105 U108 U109 U110 thru 113 U114 U115 U120 U198 U199 U208 thru 211 U212 U213 U214 U215 thru 217 U218,219 U220 U221 U400 U500 U501 U503 U505 U506 U507 U508 U515 U517 U520 5113801D02 5184720T14 5184720T03 5184720T15 5182802R32 5113808A15 5113808A06 5182802R25 5113805A09 5113805A02 5113805A10 5113806A05 5182316T10 5113808A43 5191044A01 5191045C02 5113803A12 5182663X01 5113806A18 5113811A20 5113805A18 5113819A09 5113818A01 5113808A07 5182456W01 5183808P77 0913900A01 5184830T02 5191043A01 0982451V13 5184437N84 5113808A41 5184709T02 5183808P60 5182802R25 5113808A38 5182802R29 5182316T11 5182316T05 5182802R29 5183808P77 5113806A01 5113806A05 5113811A20 5182802R25 5183808P77 32-Bit Micro Processor Unit IC PRGMD PAL IC PRGMD PAL IC PRGMD PAL IC DIG DCDR DEMUX _LS138_ IC OR QUAD 2 INP MC74ACT32D IC INV HEX MC74ACT04D Hex Inverter Schmit Trigger Hex Inverter Quad 2-Input NOR Gate Dual 4-Input NAND Gate Dual D-Type Flip-Flop CMOS Hex Inverting Buffer IC SHIFT REG 8 BIT UNIVERSAL IC FIFO MEM 256X9 SM 25NS IC PRGMD EPROM IC 56166 DSP,60 MHZ CLK IC LC2 MOS 14BIT DAC -78408-Channel Analog Multiplexer/ Demultiplexer IC PCM CODEC/FLTR MONO-CIR Dual D-Type Flip-Flop with Set/Reset Quad JFET Input Operational Amplifer IC LOW COST SING SPLY LM2904DR Quad 2-Input AND Gate IC UP MONITOR -1232- SM Hex Buffer/Logic-Level Down Converter SOCKET 20 POS. SQ. SUR MT IC SRAM 128KX8 MT5C1008-SM IC EEPROM 128KX8-28C010-DIP SOCKET, IC 32 PIN SM T & R DUART CMOS Line Driver/Receiver Octal OCTOCPLR LOGIC GATE SOIC 601 IC HCMOS QUAD 2 INP NAND HC00 Hex Inverter Octal 3-State Non-Inverter Line Driver Hex Buffer Hex Schmitt Trigger Hex Type D Flip-Flop Hex Buffer Hex Buffer/Logic-Level Down Converter Quad 2-Input NOR Gate Dual D-Type Flip-Flop IC PCM CODEC/FLTR MONO-CIR Hex Inverter Hex Buffer/Logic-Level Down Converter
NOTE: FOR OPTIMUM PERFORMANCE, DIODES, TRANSISTORS,

INTEGRATED CIRCUITS, AND CRYSTALS MUST BE ORDERED BY MOTOROLA PART NUMBER.
68 P81095E 50- A 1/18/ 01
10-41
10-42
6 8 P 8 1 0 9 5 E5 0 - A 1 /18 /0 1

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The easy solution to a tough job.

Simplify your radio dispatch operations.

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

2001 Motorola, Inc. All Rights Reserved Printed in U.S.A.

Land Mobile Products Sector

1301 E. Algonquin Road, Schaumburg, IL 60196

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 3 Descriptor String Assignments

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 5 Maintenance and Diagnostics

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 6 Hybrid Troubleshooting

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 7 CEB Card Cage Interconnect Board

Chapter 8 Base Interface Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 9 Dual Receive Interface Module

Chapter 10 Console Operator Interface Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 12 Punch Block and Spark Gap

Chapter 13 System Timer Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 14 Operator Audio Expansion Interface

Chapter 15 16 I/O Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 16 Logging Recorder Interface Board

Chapter 17 MDC Channel Signaling Modem

Chapter 18 ASTRO Console Interface Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 19 Remote Operator CEB Interface Board (and Later Version)

Chapter 20 RS-232 Interface Relocator Board

Chapter 21 Auxiliary I Module

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 22 Auxiliary II Module

Chapter 23 Tone Line Operated Busy Light

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 24 Dual Tone LOBL

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 26 Power Supplies

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Chapter 27 Cable and Hardware Kits

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

This Page Intentionally Left Blank

About this chapter

Land Mobile Products Sector

1301 E. Algonquin Road, Schaumburg, IL 60196

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

Overview of the CEB

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

System functional description

System functional description

TIMER MODULE TDM BUS WITH CONTROL SIGNALS

OPERATOR INTERFACE MODULE

OPERATOR INTERFACE MODULE

OPERATOR INTERFACE CABLE (ONE CABLE WITH 7 TWISTED PAIRS)

Block diagram of the CEB

68P 81095E 50- A 11/30/2000

CENTRACOM Gold Series Central Electronics Bank Maintenance Manual

System functional description

Time division multiplex switching

ANALOG AUDIO SIGNAL