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Machine Problem Specifications and Guidelines Each group is assigned and tasked to graphically or visually simulate a memory management

scheme and a CPU scheduling algorithm. The simulation may be developed in any programming language the group prefers. Each group is required to demonstrate the project. The following figure shows the general architecture of the simulation program:
Job Generator Job Queue Memory Management Main Memory


CPU Scheduling

Ready Queue

Project Output and Requirements: 1. The program should be able to read the input data from a text file having .txt as file extension. The input text file will have the following format: <number of jobs> <job id1> <arrival time1> <job type1> <memory size1> <CPU burst time1> <job id2> <arrival time2> <job type2> <memory size2> <CPU burst time2> : <job idn> <arrival timen> <job typen> <memory sizen> <CPU burst timen> A timer (or clock) and a pause feature should be included in the simulation program. Before the simulation starts, the program should provide the following two options to the user: (a) simulate both memory management and CPU scheduling; or (b) simulate CPU scheduling only. The program should be able to show the following on screen during simulation: contents of the ready queue memory map (if simulating memory management) CPU Gantt chart free-space list (if simulating memory management) CPU status / current running process The program should also be able to compute and show the following statistics for each job: turnaround time time of arrival in memory (if simulating memory management) waiting time memory location occupied (if simulating memory management) finish time

2. 3.



Simulation Model Parameters: 1. Process Characteristics

A process has the following characteristics: job id 1 to 20 (assume a maximum of 20 jobs) arrival time Jobs arriving to the job queue should have 1 to 20 units time interval. job type system [1], interactive [2], batch [3] For priority scheduling, system jobs have highest priority and batch jobs have lowest priority. memory size 1 K to 16 K length of CPU bursts 1 to 20 time units Note: Both job id and arrival time are unique for each job.


Memory Management Scheme

The total memory space is 64 K. All schemes will be implemented with no compaction. The following are the specifications for each memory management scheme: MFT region sizes: 16 K, 16 K, 8 K, 8 K, 8 K, 4 K, and 4 K allocation: best available fit FIFO job queue with skip allocation: best fit FIFO job queue with skip page size: 2 K allocation: start from first page and allocate to first available frame FIFO job queue with skip segment sizes: 1 K, 2 K, and 3 K (segment job starting first from the 3 K size, followed by 2 K, then 1 K; do not segment using the smaller sizes unless the job cannot anymore be segmented using the bigger sizes) allocation: largest job segment first using worst fit FIFO job queue with skip





CPU Scheduling

The following are the specifications for selected CPU scheduling algorithms: Round-Robin MLQ time quantum is 5 time units three (3) -level queue (see job type) queue scheduling: FCFS for the three queues preemptive between queues three (3) -level feedback queue queue scheduling: q = 8, q = 4, and FCFS respectively non-preemptive between queues


Deliverables: Submit the following in a properly labeled short brown envelope. Label should include names of members (alphabetically arranged according to surnames), the memory management scheme and the CPU scheduling algorithm implemented. Program (CD) Source code Executable file All other files required to run the program Text files containing sample test data Documentation Users Manual (minimum of 5 pages) Internal Design Document (discussion of data structures used and manner of implementation, minimum of 5 pages) Sample Test Data and Results produced by the program (at least 5 sets) Analysis of Algorithms Assigned (the memory and CPU scheduling algorithms work best/worst under what type of data set) Grading System: Program (75%) Correctness and Completeness Screen Layout Documentation (25%) Users Manual Internal Design Document Test Data and Results Analysis of Algorithms

80% 20%

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