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MICROCONTROLLER BASED DIGITAL CLOCK WITH CALENDAR

Vipul M Dabhi, MISTE Abstract:


We have noticed that the time is continuously updated in PC even though the computer is off. To realize this task, we have interfaced two chips: microcontroller (89C51) and real time clock (DS 12887). The result of this is to access the data provided by RTC and displayed it on the 7-segment displays and by using these data realizing timekeeping. Time keeping means by programming we can set alarm before many year. We can build a programmer that will keep track of our programs. In addition of this we are provided one function called day-light-saving, by using this feature we can change our settings in winter and summer accordingly.

Hetal N Patel, MISTE

Keywords:
Real Time Clock, Watch Dog Timer

1. INTRODUCTION
For designing the system basic chips required are: (1) Microcontroller (89C51). (2) Real time clock (DS 12887). (3) Micro monitor chip (DS 1232). (4) Latches (74LS 373). (5) Decoders (74LS 47). More ever, we have designed power supply of 5V regulated and 12 V unregulated for that we have used LM 317 regulated IC [3]. The data produced by RTC is stored in various RAM location of DS 12887; these data are accessed by microcontroller [1] which is to be displayed on 7-segment display [5]. There are seven LEDs also to display seven days of a week. Different time related information is stored in different RAM locations of RTC. To get this data controller sends an address to RTC and RTC sends data on data bus. Now controller sends these data to all the latches [5], but the latch which is selected by controller stores these data and gives it to corresponding BCD to 7-segment decoder [2], than decoder decodes it and sends to display. So in this way we can display all the data produced by RTC [6]. ______________________________
Vipul M. Dabhi, Assistant Professor, EC Department, A D Patel Institute of Technology, New V.V.Nagar -388125, Ta: Anand, Dist: Anand, e-mail: vipuldabhi@yahoo.co.in Hetal N. Patel, Assistant Professor, EC Department, A D Patel Institute of Technology, New V.V.Nagar 388125, Ta: Anand, Dist: Anand, e-mail: hetnik2710@yahoo.com

Figure: 1 Block diagram of the system

The functions of the RTC (DS 12887) are nonvolatile time-of-day clock, an alarm, 100 year calendar, programmable interrupt, square wave generator and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time of day and memory are maintained even in the absence of power.

1.1 Address map of RTC

Figure: 2 Address map of RTC The address map consists of 114 bytes of user RAM, 10bytes of RAM that contains the RTC time, calendar and alarm data and 4 bytes, which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Register C and D are read only. 2. Bit 7 of register A is read only. 3. The high order bit of the seconds byte is read only.

time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cant be change without reinitializing the 10 data bytes. RANGE ADD FUNCTION DEC LOC RANGE BINARY BCD MODE MODE 0 Seconds 0-59 00-3B 00-59 1 Seconds 0-59 00-3B 00-59 alarm 2 Minutes 0-59 00-3B 00-59 3 Minutes 0-59 00-3B 00-59 alarm 4 Hours(121-12 01-0C 01hr) AM 12AM, ,8181-92 8CPM PM Hours (240-23 00-17 00-23 hr) 5 Hours 1-12 01-0C 01alarm(12AM, 12AM, hr) 8181-92 8CPM PM Hours alarm 0-23 00-17 00-23 (24-hr) 6 Day of the 1-7 01-07 01-07 week Sunday=1 7 Date of the 1-31 01-1F 01-31 month 8 Month 1-12 01-0C 01-12 9 Year 0-99 00-63 00-99 Table 1.1 Time, Calendar and Alarm data modes Table 1.1 shows the binary and BCD format of the 10 time, calendar and alarm locations. The 2412 bit cant be change without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents pm when it is logic 1. The time, calendar and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, the problem exists where seconds, minutes, hours etc. may not correlate. The probability of reading incorrect time and calendar data is low. The three alarm bytes can be use in two ways: first, when the alarm time is written in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. Second, to insert a dont care state in one or more from the three alarm bytes. The dont

1.2 Time, calendar and alarm locations


The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar and alarm are set or initialized by writing the appropriate RAM bytes. The contents of 10 time, calendar and alarm bytes can be either binary or BCD format. Before writing the internal time, calendar and alarm registers, the set bit in register B should be written to logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10 time, calendar and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of register B must be set to the appropriate logic level. All 10 time, calendar and alarm bytes must use the same data mode. The set bit in register B should be clear after the data mode bit has been written to allow the real time clock to update the

care code is any hex value from C0 to FF. The two most significant bits of each byte set the dont care condition when it logic 1. An alarm will be generated each hour when the dont care bits are set in the hours byte. Similarly, an alarm is generated every minute with dont care codes in the hours and minutes alarm bytes. The dont care codes in all three alarm bytes create an interrupt every second.

1.6 Interrupts
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The alarm interrupt can be program to occur at rates from once per second to once per day. The periodic interrupt can be selected for rates from 500ms to 122ms. The update ended interrupt can be used to indicate to the program that an update cycle is complete. The processor program can select which interrupts, if any, are going to be used. Three bits in register B enable the interrupts. Writing logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. A 0 in an interrupt enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled IRQ is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in register C. These flag bits are set independently of the state of the corresponding enable bit in the register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read. However, care should be taken when using the flag bits as they are cleared each time register C is read. Double latching is included with register C so that bits which are set remains stable through out the read cycle. All bits which are set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. 1, 2 or 3 bits can be set when reading register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost. The second flag bit usage method is with fully enable interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQ pin is asserted low. The IRQ is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in register C is 1 whenever the IRQ pin is being driven law. Determination that RTC initiated an interrupt is accomplished by reading register C. A logic 1 in bit 7(IRQF bit) indicates that one or more interrupts have been initiated by the DS 12887.

1.3 Power Up/Power down Considerations


The Real Time Clock function will continue to operate and all of the RAM, time, calendar and alarm memory locations remain non-volatile regardless of the level of the Vcc input. When Vcc is applied to the DS 12887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200ms, provided that the oscillator is running and the oscillator countdown chain is not in reset. This time period allows the system to stabilize after power is applied. When Vcc falls below 4.25 volts, the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin. When Vcc falls below approximately 3 volts, the external Vcc supply is switched off and an internal lithium energy source supplies power to the Real Time Clock and the RAM memory.

1.4 Signal Descriptions


Vcc is +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When Vcc is below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by lower input voltage. As Vcc falls below 3 volts, the RAM and timekeepers are switched over an internal lithium energy source. The timekeeping function maintains an accuracy of 1 minute per month at 200C regardless of the voltage input on the Vcc pin.

1.5 Nonvolatile RAM


The 114 general purpose nonvolatile RAM bytes are not dedicated to special function within DS 12887. They can be use by the processor program has nonvolatile memory and are fully available during the update cycle.

The act of reading register C clears all active flag bits and the IRQF bit.

1.7 Oscillator Control Bits


Initially, the internal oscillator of DS 12887 is turned off. This feature prevents the lithium energy cell from being use until it is install in system. A pattern of 010 in bits 4 through 6 of register A will turn the oscillator ON and enable the countdown chain. A pattern of 11X will turn the oscillator ON, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscillator OFF.

1.8 Periodic Interrupt Selection


The periodic interrupt will cause the IRQ pin go to an active state from once every 500ms to once every 122 ms. These function is separate from the alarm interrupt which can be output form once per second to once per day. The periodic interrupt rate is selected using the same register A bits which selects the square wave frequency. Changing the register A bits affects both the square wave frequency and the periodic interrupt outputs. However, each function has a separate enable bit register B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE bit in register B. The periodic interrupt can be used with software counters to measure inputs, create output intervals or await the next needed software function.

an interrupt occurs after every update cycle that indicates over 999ms are available to read valid time and date information. If this interrupt is use, the IRQF bit in register C should be clear before leaving the interrupt routine. A second method uses the update in progress bit (UIP) in register A to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 ms later. If a law is read on the UIP bit, the user has at least 244ms before the time/calendar data will be change. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 ms. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in register A is set high between the setting of the PF bit in register C.

1.10 Registers
A) Register A Bit7 Bit6 Bit5 UIP DV2 DV1 Bit4 DV0 Bit3 RS3 Bit2 RS2 Bit1 RS1 Bit0 RS0

Update In Progress (UIP): The UIP bit is a status flag that can be monitored. When the UIP bit is 1, the update transfer will soon occur. When UIP bit is 0, the update transfer will not occur for at least 244 ms. The Time, Calendar and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read only and is not affected by RESET. Writing the SET bit in register B to a 1 inhibits any update transfer and clears the UIP status bit. DV0, DV1, DV2: These three bits are used to turn the oscillator on or off and reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1and DV2. RS3, RS2, RS1 and RS0: These four rate selection bits select one of the 13 taps on the 15 stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW) pin and /or a periodic interrupt. The user can do one of the following: 1. Enable the interrupt with PIE bit. 2. Enable the SQW output pin with SQWE bit. 3. Enable both at the same time and at the same rate: or

1.9 Update Cycle


The DS12887 executes an update cycle once per second regardless of the set bit in register B. When the set bit in register B is set to 1, the user copy of the double buffered time, calendar and alarm bytes are frozen and will not update as the time increments. However, the time counts down chain continuous to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of reading or writing the time, calendar and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a dont care code is present in all three positions. There are three methods that can handle access of the real time clock that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update ended interrupt. If enable,

4. Enable neither. Table 1.2 lists the periodic interrupt rates and square wave frequencies that can be chosen with the RS bits. These four read/write bits are not affected by RESET. SELECT BITS REG A RS3 RS2 RS1 RS0 PERIODIC INTERRUPT RATE (ms) None 3.90625 7.8125 122.070 s 244.141 s 488.281 s 976.5625 s 1.953125 3.90625 7.8125 15.625 31.25 62.5 125 250 500 SQW O/P FREQ. (Hz) None 256 128 8.192 k 4.096 k 2.048 k 1.024 k 512 256 128 64 32 16 8 4 2

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the pushbutton input and guarantees an active reset pulses width of 250 ms minimum. The function is a watch dog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on time out settings of approximately 150 ms, 600 ms and 1.2 seconds.

1.12 Operation- Watch Dog Timer


A watch dog timer [6] function forces RST and ST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected and 1.2 seconds with TD connected to Vcc. The watch dog timer starts timing out from the set time period as soon as RST and ST are inactive. If a high to low transition occur on the ST input pin prior to time out, the watch dog timer is reset and begins to time out again. If the watch dog timer is allowed to time out, then the RST and ST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals and /or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watch dog to be reset prior to time out. To guarantee that the watch dog timer does not time out, a high to low transition must occur at or less than the minimum shown in table 1.2. A typical circuit example is shown in figure.

Table: 1.2 Periodic interrupt rates and Square wave frequencies B) Register B Bit7 Bit6 Bit5 SET PIE AIE C) Register C Bit7 Bit6 Bit5 IRQF PF AF D) Register D Bit7 Bit6 Bit5 VRT 0 0

Bit4 UIE

Bit3 SQWE

Bit2 DM

Bit1 24/12

Bit0 DSE

Bit4 UF

Bit3 0

Bit2 0

Bit1 0

Bit0 0

Bit4 0

Bit3 0

Bit2 0

Bit1 0

Bit0 0

1.11 DS1232 (Micro Monitor Chip)


The DS1232 Micro Monitor Chip monitors three vital conditions for microprocessors: power supply, software execution and external override. First, a precision temperature compensated reference and comparator circuit monitors the status of Vcc. When an out of tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When Vcc returns to an in tolerance condition, the reset

Figure: 3 Watch Dog Timer

2. HOW TO WORK WITH THE SYSTEM ?


Basically, this system works in three different modes: Normal mode Setting mode Timer mode In normal mode, it displays HOUR: MIN. On the display we can see different timing information on the display just by pressing appropriate switch from mode selection switches. Pressed switch Effect No.1 Shows seconds No.2 Day of week(1-SUN) No.3 Date No.4 Month No.5 Year No.6 To go in other modes Table2.1 Information Table This normal mode is displayed by default. Now to enter in setting mode, press switch no.6 and meanwhile reset the processor, then release reset and hold switch no.6 pressed until 2222 displays. This is to indicate that we have entered in setting mode and LED no.1 will glow to show it. Now we can set time from switches as directed below: Pressed Switch Effect No.1 Minute setting No.2 Hour setting No.3 Day of week setting No.4 Date setting No.5 Month setting No.6 To go in other modes Table 2.2 Effect of switches After setting the new time, to load RTC with new time, press switch no.6, then press switch no.2 and we will have new time loaded and updating of it will be started. Now to go in timer mode, press switch no.6 then 4444 will be displayed on display and LED no.6 will glow. Now to increment the timing use switch no.2 and set desire timings. Then press switch no.1, so timer will be activated.

3. SOFTWARE DESCRIPTION

3. CONCLUSION
This digital calendar follows time starting from a second to years with a fair accuracy. There are extra features like automatic alarm, time setting, non-volatile operation, clock in 12 or 24 hours mode, time keeping and daylight saving. This calendar works for 99 years accurately and its internal timer can run for ten years in the absence of power. So this digital calendar is a multipurpose used at many places for many years.

REFERENCES
[01] Ayala, K. J., 8051 Microcontroller, Second Edition, Penram International. [02] Mazidi, M. Ali and Mazidi J.G. The 8051 Microcontroller and Embedded systems, First Edition, Pearson Education. [03] Gayakwad, R. A., Op-Amp and Linear Integrated Circuits, Fourth Edition, Pearson Education. [04] Rai, Harish C., Industrial Electronics, Second Edition, Galgotia Publication. [05] Gaonkar, R. S., Microprocessor Architecture, Programming and Applications, Fourth Edition, Penram International. [06] Dallas semiconductor, www.dallassemiconductor.com [07] Atmel IC family www.atmel.com [08] General purpose IC www.icmaster.com

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