Keywords:
Real Time Clock, Watch Dog Timer
1. INTRODUCTION
For designing the system basic chips required are: (1) Microcontroller (89C51). (2) Real time clock (DS 12887). (3) Micro monitor chip (DS 1232). (4) Latches (74LS 373). (5) Decoders (74LS 47). More ever, we have designed power supply of 5V regulated and 12 V unregulated for that we have used LM 317 regulated IC [3]. The data produced by RTC is stored in various RAM location of DS 12887; these data are accessed by microcontroller [1] which is to be displayed on 7-segment display [5]. There are seven LEDs also to display seven days of a week. Different time related information is stored in different RAM locations of RTC. To get this data controller sends an address to RTC and RTC sends data on data bus. Now controller sends these data to all the latches [5], but the latch which is selected by controller stores these data and gives it to corresponding BCD to 7-segment decoder [2], than decoder decodes it and sends to display. So in this way we can display all the data produced by RTC [6]. ______________________________
Vipul M. Dabhi, Assistant Professor, EC Department, A D Patel Institute of Technology, New V.V.Nagar -388125, Ta: Anand, Dist: Anand, e-mail: vipuldabhi@yahoo.co.in Hetal N. Patel, Assistant Professor, EC Department, A D Patel Institute of Technology, New V.V.Nagar 388125, Ta: Anand, Dist: Anand, e-mail: hetnik2710@yahoo.com
The functions of the RTC (DS 12887) are nonvolatile time-of-day clock, an alarm, 100 year calendar, programmable interrupt, square wave generator and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time of day and memory are maintained even in the absence of power.
Figure: 2 Address map of RTC The address map consists of 114 bytes of user RAM, 10bytes of RAM that contains the RTC time, calendar and alarm data and 4 bytes, which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Register C and D are read only. 2. Bit 7 of register A is read only. 3. The high order bit of the seconds byte is read only.
time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cant be change without reinitializing the 10 data bytes. RANGE ADD FUNCTION DEC LOC RANGE BINARY BCD MODE MODE 0 Seconds 0-59 00-3B 00-59 1 Seconds 0-59 00-3B 00-59 alarm 2 Minutes 0-59 00-3B 00-59 3 Minutes 0-59 00-3B 00-59 alarm 4 Hours(121-12 01-0C 01hr) AM 12AM, ,8181-92 8CPM PM Hours (240-23 00-17 00-23 hr) 5 Hours 1-12 01-0C 01alarm(12AM, 12AM, hr) 8181-92 8CPM PM Hours alarm 0-23 00-17 00-23 (24-hr) 6 Day of the 1-7 01-07 01-07 week Sunday=1 7 Date of the 1-31 01-1F 01-31 month 8 Month 1-12 01-0C 01-12 9 Year 0-99 00-63 00-99 Table 1.1 Time, Calendar and Alarm data modes Table 1.1 shows the binary and BCD format of the 10 time, calendar and alarm locations. The 2412 bit cant be change without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents pm when it is logic 1. The time, calendar and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, the problem exists where seconds, minutes, hours etc. may not correlate. The probability of reading incorrect time and calendar data is low. The three alarm bytes can be use in two ways: first, when the alarm time is written in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. Second, to insert a dont care state in one or more from the three alarm bytes. The dont
care code is any hex value from C0 to FF. The two most significant bits of each byte set the dont care condition when it logic 1. An alarm will be generated each hour when the dont care bits are set in the hours byte. Similarly, an alarm is generated every minute with dont care codes in the hours and minutes alarm bytes. The dont care codes in all three alarm bytes create an interrupt every second.
1.6 Interrupts
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The alarm interrupt can be program to occur at rates from once per second to once per day. The periodic interrupt can be selected for rates from 500ms to 122ms. The update ended interrupt can be used to indicate to the program that an update cycle is complete. The processor program can select which interrupts, if any, are going to be used. Three bits in register B enable the interrupts. Writing logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. A 0 in an interrupt enable bit prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled IRQ is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in register C. These flag bits are set independently of the state of the corresponding enable bit in the register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read. However, care should be taken when using the flag bits as they are cleared each time register C is read. Double latching is included with register C so that bits which are set remains stable through out the read cycle. All bits which are set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. 1, 2 or 3 bits can be set when reading register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost. The second flag bit usage method is with fully enable interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQ pin is asserted low. The IRQ is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in register C is 1 whenever the IRQ pin is being driven law. Determination that RTC initiated an interrupt is accomplished by reading register C. A logic 1 in bit 7(IRQF bit) indicates that one or more interrupts have been initiated by the DS 12887.
The act of reading register C clears all active flag bits and the IRQF bit.
an interrupt occurs after every update cycle that indicates over 999ms are available to read valid time and date information. If this interrupt is use, the IRQF bit in register C should be clear before leaving the interrupt routine. A second method uses the update in progress bit (UIP) in register A to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 ms later. If a law is read on the UIP bit, the user has at least 244ms before the time/calendar data will be change. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 ms. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in register A is set high between the setting of the PF bit in register C.
1.10 Registers
A) Register A Bit7 Bit6 Bit5 UIP DV2 DV1 Bit4 DV0 Bit3 RS3 Bit2 RS2 Bit1 RS1 Bit0 RS0
Update In Progress (UIP): The UIP bit is a status flag that can be monitored. When the UIP bit is 1, the update transfer will soon occur. When UIP bit is 0, the update transfer will not occur for at least 244 ms. The Time, Calendar and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read only and is not affected by RESET. Writing the SET bit in register B to a 1 inhibits any update transfer and clears the UIP status bit. DV0, DV1, DV2: These three bits are used to turn the oscillator on or off and reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1and DV2. RS3, RS2, RS1 and RS0: These four rate selection bits select one of the 13 taps on the 15 stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW) pin and /or a periodic interrupt. The user can do one of the following: 1. Enable the interrupt with PIE bit. 2. Enable the SQW output pin with SQWE bit. 3. Enable both at the same time and at the same rate: or
4. Enable neither. Table 1.2 lists the periodic interrupt rates and square wave frequencies that can be chosen with the RS bits. These four read/write bits are not affected by RESET. SELECT BITS REG A RS3 RS2 RS1 RS0 PERIODIC INTERRUPT RATE (ms) None 3.90625 7.8125 122.070 s 244.141 s 488.281 s 976.5625 s 1.953125 3.90625 7.8125 15.625 31.25 62.5 125 250 500 SQW O/P FREQ. (Hz) None 256 128 8.192 k 4.096 k 2.048 k 1.024 k 512 256 128 64 32 16 8 4 2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the pushbutton input and guarantees an active reset pulses width of 250 ms minimum. The function is a watch dog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on time out settings of approximately 150 ms, 600 ms and 1.2 seconds.
Table: 1.2 Periodic interrupt rates and Square wave frequencies B) Register B Bit7 Bit6 Bit5 SET PIE AIE C) Register C Bit7 Bit6 Bit5 IRQF PF AF D) Register D Bit7 Bit6 Bit5 VRT 0 0
Bit4 UIE
Bit3 SQWE
Bit2 DM
Bit1 24/12
Bit0 DSE
Bit4 UF
Bit3 0
Bit2 0
Bit1 0
Bit0 0
Bit4 0
Bit3 0
Bit2 0
Bit1 0
Bit0 0
3. SOFTWARE DESCRIPTION
3. CONCLUSION
This digital calendar follows time starting from a second to years with a fair accuracy. There are extra features like automatic alarm, time setting, non-volatile operation, clock in 12 or 24 hours mode, time keeping and daylight saving. This calendar works for 99 years accurately and its internal timer can run for ten years in the absence of power. So this digital calendar is a multipurpose used at many places for many years.
REFERENCES
[01] Ayala, K. J., 8051 Microcontroller, Second Edition, Penram International. [02] Mazidi, M. Ali and Mazidi J.G. The 8051 Microcontroller and Embedded systems, First Edition, Pearson Education. [03] Gayakwad, R. A., Op-Amp and Linear Integrated Circuits, Fourth Edition, Pearson Education. [04] Rai, Harish C., Industrial Electronics, Second Edition, Galgotia Publication. [05] Gaonkar, R. S., Microprocessor Architecture, Programming and Applications, Fourth Edition, Penram International. [06] Dallas semiconductor, www.dallassemiconductor.com [07] Atmel IC family www.atmel.com [08] General purpose IC www.icmaster.com