1) Refer to example 4.2, Page 111 of textbook. Rewrite the necessary design modules using dot operator format.

2) Write separate Testbench files to check the functionality of the modules a. Add_half_0_delay;

module Add_half_0_delay(sum, c_out, a, b); output input xor and endmodule sum, c_out; a, b; M1 (sum, a, b); M2 (c_out, a, b);

Testbench for the above module: timescale 1ns/100ps // 1 time unit =1ns module t; //testbench module // reg:input, wire:output wire reg sum, c_out; a, b, clk;

// instantiate top module to test Add_half_0_delay m(sum, c_out, a, b); // initialize input & set simulation end time initial begin clk=1b1; a=1b0; b=1b0; #70 $finish; end // clock generator, always execute from t=0 forever parameter clk_high=1; // 1 period = 2TU=2ns=>500MHz always #clk_high clk=~clk; // input signal generation reg [1:0] cnt; // 2 bit counter initial cnt=2b0; always @ (posedge clk);

begin; a=cnt [0]; b=cnt [1]; cnt<=cnt+1 end endmodule

b. Add_full_0_delay;

module Add_full_0_delay(sum, c_out, a, b, c_in); output input sum, c_out; a, b, c_in; M1 (w1, w2, a, b); M2 (sum, w3, w1, c_in); M3 (c_out, w2, w3);

Add_ full _0_delay Add_ full _0_delay or endmodule

Testbench for the above module: timescale 1ns/100ps // 1 time unit =1ns module t; //testbench module // reg:input, wire:output wire reg sum, c_out; a, b, c_in , clk;

// instantiate top module to test Add_full_0_delay m(sum, c_out, a, b, c_in); // initialize input & set simulation end time initial begin clk=1b1; a=1b0; b=1b0; c_in=1b0; #70 $finish; end // clock generator, always execute from t=0 forever parameter clk_high=1; // 1 period = 2TU=2ns=>500MHz always #clk_high clk=~clk; // input signal generation reg [2:0] cnt; // 2 bit counter initial cnt=3b0; always @ (posedge clk);

begin; a=cnt [0]; b=cnt [1]; c_in= cnt [2]; cnt<=cnt+1 end endmodule

c. Add_rca_4; and

module Add_rca_4(sum, c_out, a, b, c_in); output [3:0] output input [3:0] input wire Add_ full _0_delay Add_ full _0_delay Add_ full _0_delay Add_ full _0_delay endmodule sum; c_out; a, b; c_in; c_in2, c_in3, c_in4; M1 (sum [0], c_in2, a[0], b[0], c_in); M2 (sum [1], c_in3, a[1], b[1], c_in2); M3 (sum [2], c_in4, a[2], b[2], c_in3); M4 (sum [3], c_out, a[3], b[3], c_in4);

Testbench for the above module: timescale 1ns/100ps // 1 time unit =1ns module t; //testbench module // reg:input, wire:output wire [3:0] wire reg [3:0] reg sum; c_out; a, b; c_in, clk;

Add_rca_4 m(sum, c_out, a, b, c_in); // instantiate top module to test

initial begin // initialize input & set simulation end time clk=1b1; a=4b0; b=4b0; c_in=1b0; #70 $finish; end // clock generator, always execute from t=0 forever parameter clk_high=1; always #clk_high clk=~clk; // 1 period = 2TU=2ns=>500MHz // input signal generation reg [8:0] cnt; // 2 bit counter initial cnt=9b0; always @ (posedge clk);

begin; a=cnt [3:0]; b=cnt [7:4]; c_in= cnt [8]; cnt<=cnt+1 end endmodule

d. Add_rca_16;

module Add_rca_16(sum, c_out, a, b, c_in); output [15:0] output input [15:0] input wire Add_rca_4 Add_rca_4 Add_rca_4 Add_rca_4 endmodule sum; c_out; a, b; c_in; c_in4, c_in8, c_in12, c_out; M1 (sum [3:0], c_in4, a[3:0], b[3:0], c_in); M2 (sum [7:4], c_in8, a[7:4], b[7:4], c_in4); M3 (sum [11:8], c_in12, a[11:8], b[11:8], c_in8); M4 (sum [15:12], c_out, a[15:12], b[15:12], c_in12);

Testbench for the above module: timescale 1ns/100ps // 1 time unit =1ns module t; //testbench module // reg:input, wire:output wire [15:0] wire reg [15:0] reg sum; c_out; a, b; c_in, clk;

Add_rca_16 m(sum, c_out, a, b, c_in); // instan. top module to test

initial begin // initialize input & set simulation end time clk=1b1; a=16b0; b=16b0; c_in=1b0; #70 $finish; end // clock generator, always execute from t=0 forever parameter clk_high=1; always #clk_high clk=~clk; // 1 period = 2TU=2ns=>500MHz // input signal generation reg [32:0] cnt; // 2 bit counter initial cnt=33b0; always @ (posedge clk);

begin; a=cnt [15:0]; b=cnt [32:16]; c_in= cnt [33]; cnt<=cnt+1 end endmodule