SeaSolves Viterbi Decoder is a parameterizable high performance IP core that performs decoding of the convolutionally encoded data as well as punctured codes. The core is compatible with various standards such as DVB, 3G, WLAN, WIMAX IEEE 802.16d and 802.16e. This low latency decoder core supports various code rates, constraint lengths and generator polynomials and supports soft decision decoding. The core offers wireless Chipset designers, OEMs and ODMs a standard compliant platform to accelerate development process and reduce time to market.
Features
Internal puncturing with puncturing clock : 1/2, 2/3, 3/4, 5/6 Code rates : 1/2, 2/3, 3/4, 5/6 Parameterizable trace back length and address width of the memory. Parameterizable width for soft decision from 1 to 8. Parameterizable constraint length from 3 to 9. Parameterizable generator polynomial. Data Format Offset Binary and Sign Magnitude Input Rate : 1/2 Puncturing or non-puncturing the encoded data bits. De-puncturing of punctured convolutional encoded data. Hard Decision and Soft Decision Decoding. Different Trace-back depth for Punctured and Non-punctured data. Provide standard interface with external devices.
Deliverables
Fully Synthesizable VHDL code Fully Functional Test bench Timing simulated target specific VHDL code
www.seasolve.com
Viterbi Decoder
Block Diagram
Depuncturing
BMC
ASC BLOCK
Control Unit
Survivor Memory
Pin Diagrams
Input Clk Clk pun Reset Valid_in Code rate Convolutional Encoder Output Recv Clk Clk pun Reset Valid out Valid_in Code rate Hard Code Viterbi Decoder Output
Valid out
Input/Output Snapshots
www.seasolve.com
Viterbi Decoder
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