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A Simple Single-InputSingle-Output (SISO) Model for a Three-Phase PWM Rectier

Bo Yin, Member, IEEE, Ramesh Oruganti, Senior Member, IEEE, Sanjib Kumar Panda, Senior Member, IEEE, and Ashoka K. S. Bhat, Fellow, IEEE

AbstractThe challenge in controlling a three-phase pulsewidth modulation (PWM) rectier under balanced conditions arises from the fact that the state-space averaged model reported in literature has a multi-inputmulti-output nonlinear structure and furthermore exhibits a nonminimum phase feature. In this paper, a simple single-inputsingle-output model is constructed by separating the d-axis and the q-axis dynamics through appropriate nonlinear feedforward decoupling while maintaining nearly unity power factor operation. With the proposed model, the nonminimum phase feature inherent in an ac-to-dc rectier becomes a simple righthalf-plane zero appearing in the small-signal control-to-output transfer function. In addition, the model exhibits a close similarity to a dcdc boost converter under both large-signal and small-signal operating conditions. This makes it possible to extend the system analysis and control design techniques of dcdc converters to the three-phase PWM rectier also. The validity of the proposed model has been veried experimentally in the frequency domain under open-loop operation of the PWM rectier. The usefulness of the model is further demonstrated through closed-loop operation of the rectier with both voltage mode and inner-current-loop-based schemes. Index TermsPulsewidth modulation (PWM) power converters, voltage mode control.

I. INTRODUCTION VER the past several years, considerable research work [1][14] has been carried out on the control of ac-to-dc pulsewidth modulation (PWM) rectiers (Fig. 1), since these converters possess many desirable features such as sinusoidal line currents at a required power factor, a nearly constant dc output voltage, and bidirectional power delivery capability. As the lter capacitor required is generally small under balanced supply voltage conditions, it may also be believed that these converters can offer excellent dynamic response of the dc output voltage.

Manuscript received June 16, 2006; revised August 6, 2007. First published March 24, 2009; current version published April 8, 2009. Parts of this paper have been presented at the 31st Annual Conference of the IEEE Industrial Electronics Society (IECON 2005), North Carolina, November 2005, and at the 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON 2006), Paris, France, November 2006. Recommended for publication by Associate Editor J. Kolar. B. Yin is with the National University of Singapore, Singapore 117576, and also with Vestas Technology R&D Singapore Pte Ltd., Singapore 189720 (e-mail: yinbo@vestas.com). R. Oruganti and S. K. Panda are with the Centre for Power Electronics, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (e-mail: eleramsh@nus.edu.sg; eleskp@nus.edu.sg). A. K. S. Bhat is with the Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC V8W 2Y2, Canada (e-mail: bhat@ece.uvic.ca). Digital Object Identier 10.1109/TPEL.2008.2012529

Control of three-phase PWM rectiers in the dq synchronously rotating frame (SRF) has been developed from eldoriented control techniques [15], [16] for ac drives in early 1980s. Normally, the control objectives of a PWM rectier are to regulate the dc output voltage on the dc side, achieve unity power factor (UPF) operation on the ac side, and also to achieve fast dynamic response to line and load disturbances. A state-space averaged model has been proposed for the three-phase PWM rectier in the dq SRF [3][5]. However, the model, though accurate, does not give sufcient insight into the controller design and behavior of the three-phase PWM rectier system due to its complex multiinputmultioutput (MIMO) nonlinear structure and the presence of a nonminimum phase feature [5]. Due to this, designing a proper controller for such a converter has been generally a challenging task. It is shown in [5] that direct control of the dc output voltage by means of inputoutput linearization is not possible as the dc output voltage is a nonminimum phase output variable. If carried out, the resultant internal dynamics of the d-axis current will be unstable. On the other hand, by selecting the d-axis and the q-axis currents as dummy output variables, inputoutput linearization can be applied and a rst-order stable zero dynamics system can be obtained for the dc output voltage. Regulation of the dc output voltage can be achieved indirectly once the d-axis current is well controlled. In apparent contrast, direct control of the dc output voltage has been realized by means of inputoutput feedback linearization in [6], by using a simplied model. It may appear that the prediction in [5] and the approach in [6] contradict each other. However, it is worth noting that the nonminimum phase feature inherent in a three-phase boost-type PWM rectier is not reected in the simplied model in [6]. This paper shows that design ignoring RHP zero is possible provided the switching frequency is low such that the RHP zero is at or beyond the Nyquist frequency or the closed-loop system bandwidth is designed to be low. Several models for PWM rectiers operating under balanced input supply conditions are available in literature [3][8]. As mentioned earlier, the popular state-space averaged model [3][5] does not give sufcient insight into the controller design due to its complex MIMO nonlinear structure and the presence of the nonminimum phase feature. The models in [6] and [7] do simplify the system structure and controller design by overlooking the inherent nonminimum phase feature in a PWM rectier. This is particularly so in [7], where the establishment of a MIMO linear model theoretically enables arbitrary pole placement in the closed-loop system. However, although the nonminimum

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Fig. 1.

Structure of a three-phase ac-to-dc PWM rectier.

phase feature is absent in the models proposed in [6] and [7], it does exist in the real boost-type PWM rectier. The existence of this nonminimum phase feature imposes a strict limit on the achievable closed-loop bandwidth of the real system. The simplied models in [6] and [7] are valid only if the closed-loop system operates within this limit. Thus, the information regarding the location of the nonminimum phase feature in the model is required for proper controller design even if the simplied models in [6] and [7] are being used. A novel reduced-order (RO) small-signal model has been proposed in [8]. The three-phase PWM rectier has been modeled here as a dcdc converter with equivalent power transfer capability and small-signal characteristics. However, the second-order RO model proposed is a one-sixth line frequency averaged model that captures only the equivalent power transfer capability of the converter. In addition, the establishment of the RO model neither reduces the number of required current controllers nor simplies the control task from a tracking into regulation problem. Three identical current controllers are needed to be implemented for tracking purposes based on this model. Besides, the signicance of the rooted nonminimum phase feature in the design of the controller is not brought out in the RO model. The fact that the nonminimum phase feature of a PWM rectier presents itself as a right-half-plane (RHP) zero in the small-signal transfer function from current reference to dc output voltage in a control-oriented model has been explored in the research reported in [11][14]. In this approach [11], [12], linear decoupling terms were applied to the overall PWM rectier model in order to reduce cross coupling between d- and q-axis currents. The current loops were then closed with conventional p-type average current mode controllers. From the resulting model, the control-oriented model between dc output voltage and d-axis current reference was obtained by performing a small-signal analysis. The control-to-output transfer function, Gc = v dc / id , which contains an RHP zero and a stable pole, has been obtained by approximation of the measured frequency response in the low- and mid-frequency range. The control-oriented model presented by this control-to-output transfer function facilitates voltage loop design as the model reduces to a single-inputsingle-output (SISO) system after closing the current loops [13]. The presence of the RHP zero in both a three-phase PWM rectier system and a dcdc boost converter shows similarity between them. These results give impor-

tant insights into the behavior of a three-phase PWM rectier system. However, the control transfer function developed in [11] and [12] only links the dc output voltage to the d-axis reference current. Also, this link is established through the use of experimental frequency response and also assuming a certain form of current controller (p-type). The control-oriented model does not link the output voltage to the operation of the rectier switches as would be expected in a detailed model of a power converter. This paper may be viewed as a continuation of the effort in [11][14] to obtain a simple and accurate control-oriented model for the three-phase PWM rectier. It proposes a simple SISO model for a three-phase rectier. In the proposed model, the MIMO system is rst decoupled into two SISO systems in which the q-axis model is a rst-order linear system determining the regulation of power factor, whereas the d-axis model, which is shown to be similar to that of a traditional dcdc boost converter, is a second-order nonlinear system determining the power delivery. Thereafter, a simple SISO model can be obtained for the d-axis operation, when the q-axis current is controlled to be zero or near zero. It was found that the proposed SISO model is similar to a dcdc boost converter under both largesignal and small-signal operations. In the small-signal model, the complex nonminimum phase feature inherent in an ac-to-dc rectier becomes a simple RHP zero appearing in the smallsignal control-to-output transfer function between the dc output voltage and an equivalent duty cycle of the system. The proposed SISO system can be operated in a quasi-openloop mode with output variable being the dc output voltage and the control input being an equivalent duty cycle, which will be dened later. This open-loop characteristic of the SISO model is examined in frequency domain. It is found that the measured frequency response shows an excellent agreement with the predicted response. The nding validates the proposed SISO model. The fact that the SISO model shows a close similarity to that of a traditional dcdc boost converter makes it possible to extend the system analysis and control design of dcdc converters to the three-phase rectiers. By utilizing the small-signal control-to-output transfer functions, both the voltage mode control scheme and inner-current-control-based scheme, which are simple and well-documented techniques often used in dcdc converters, are applied to a three-phase PWM rectier in this

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paper. The steady-state performance and also transient performance are all experimentally investigated. Experimental results show that the proposed controllers can provide both satisfactory steady-state performance and good transient performance, thus further showing the usefulness of the proposed model. As may be expected, the inner-current-loop-based scheme results in better overall performance. II. DEVELOPMENT OF THE SIMPLE SISO MODEL In this section, the proposed SISO model of the three-phase boost rectier is derived. A. Equivalent Circuit for a Three-Phase PWM Rectier The voltage-source type PWM rectier is shown in Fig. 1. Here, ea , eb , and ec represent the source voltages and ia , ib , and ic represent the input currents. Parameters L and R are the inductance and parasitic resistance values of the synchronous inductance. The system differential equations in dq SRF are as given in [3][5] L did + Rid Liq = ed vd dt (1) diq L + Riq + Lid = vq dt 3 dvdc = (ud id + uq iq ) idc . (2) C dt 4 Here, ed , eq and id , iq denote the input voltages and the input currents in the SRF and vd , vq are the control inputs, and in fact, denote the average voltages at the rectier input terminals again in the SRF. The variables vd , vq are related to the dc output voltage as follows: ud vdc vd = 2 (3) v = uq vdc q 2 where ud , uq are the d-axis and q-axis switching functions, respectively. The range of the switching functions is between 0 and 1. Under balanced and steady-state operating conditions, variables in (1) and (2) will all be dc quantities [17]. Multiplying (2) by vdc on both sides and applying (3), we can show that Cvdc dvdc 3 + vdc idc = (vd id + vq iq ). dt 2 (4)
Fig. 2. Equivalent circuit in SRF.

control inputs vd and vq vd vq = vd1 + vd2 vq 1 + v q 2 (5)

Equation (4) shows the power balance between the dc side and the ac side of the converter. The equivalent circuit based on (1) and (4) is shown in Fig. 2. This is similar to the circuit developed earlier by other researchers [17], [18]. B. Nonlinear Feedforward Decoupling Controller In Fig. 2, the coupling terms between the d-axis and the q-axis are represented by the two current-controlled dependent voltage sources. Decoupling may be achieved, if the effects of these two voltage sources are nullied by appropriately adjusting the

where vd1 and vq 1 represent the feedforward decoupling control parts with vdc ud1 vd1 Liq 2 = (6) vdc = Lid vq 1 uq 1 2 where ud1 and uq 1 are portions of the switching functions, and ud and uq correspond to the nonlinear decoupling controller with ud1 = 2Liq /vdc and uq 1 = 2Lid /vdc . With this decoupling control, the differential equation on the ac side can be rewritten as follows: di L d + Rid = ed vd2 dt (7) diq L + Riq = vq 2 . dt Decoupling control has been performed in the development of control-oriented model in earlier research [11][14] also. As mentioned earlier in Section I, a control-oriented model has been developed in [12] by rst introducing decoupling terms, and then implementing current loops. However, the linear decoupling terms ud1 = Liq /vdc ref and uq 1 = Lid /vdc ref used in [12] lead to decoupling the dynamics of d-axis and q-axis only when vdc = vdc ref . At other operating points and under transients, these decoupling terms do not lead to simplication of system dynamics. By substituting (5) and (6) into (4), the differential equation on the dc side can be written as follows: dvdc 3 + vdc idc = (vd2 id + vq 2 iq ) Cvdc (8) dt 2 where vq 2 iq represents the effect of q-axis dynamics on the d-axis. However, under balanced supply voltage and unity or near UPF conditions, the magnitude of this term will be insignicant due to the zero average value of iq . Thus, this term will usually be negligible and can be viewed as a small disturbance in the d-axis. It has been shown experimentally in Section III of this paper that the presence of a small magnitude of q-axis current of either polarity has a negligible effect on the

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Fig. 3. Equivalent circuit in SRF after decoupling and neglecting of q-axis disturbance on d-axis dynamics.

d-axis dynamics, thus justifying the neglecting of the term vq 2 iq in (8). Thus, (8) can be approximated as Cvdc dvdc 3 + vdc idc = vd2 id dt 2 (9)

Fig. 4. (a) DC-to-DC boost converter. (b) Proposed d-axis equivalent circuit for the three-phase PWM rectier.

with vd2 = ud2 vdc /2. Here, ud2 is the system control input and is a portion of switching function ud . The equivalent circuit based on (7) and (9) is shown in Fig. 3. It can be seen that the d-axis and q-axis dynamics are totally decoupled in this model. This large signal model, which is based on the ignoring of the effect of the q-axis current on the d-axis dynamics, is true under unity or near UPF conditions. C. Simple SISO Model After the aforementioned decoupling and simplication assuming near UPF operation, a three-phase boost-type PWM acdc rectier becomes a dual SISO system [19]. From (7) and (9), the differential equations can be rewritten as di L d + Rid = ed 1 ud2 vdc dt 2 (10) dvdc 3 C + idc = ud2 id dt 4 diq L + Riq = vq 2 . (11) dt The q-axis model given in (11) is a rst-order linear system responsible for power factor regulation, whereas the d-axis model is a second-order nonlinear system that determines the power delivery. The q-axis behavior can be represented in the frequency domain by a simple rst-order transfer function, which is shown as 1 iq (s) = . vq 2 (s) Ls + R (12)

In order to appreciate the similarity of the model with that of a dcdc boost converter, we can dene an equivalent duty cycle d = 1 ud2 . The averaged models for both a three-phase PWM rectier and a dc-to-dc boost converter are given in (13) and (14) in Table I. This suggests an equivalent circuit for the proposed SISO model shown in Fig. 4(b) for the three-phase PWM rectier.

In Fig. 4(b), the switch S is assumed to operate at an equivalent duty cycle d resulting in a switching function ud2 . The dc output voltages of the equivalent converter under steady-state operating conditions with and without inclusion of the parasitic resistance of the inductors are summarized in Table I. Here, D is the steady-state equivalent duty cycle, Vdc is average output dc voltage, and Ed is the d-axis supply voltage. As in a dc-to-dc boost converter, the effect of circuit losses will be to reduce the gain, especially at high duty ratio values. The proposed simple SISO model can be obtained by applying the nonlinear decoupling controllers and ensuring UPF regulation, as shown in Fig. 5. This gure shows the implementation of: 1) the decoupling control; 2) abc dq transformations that are needed; and also 3) the q-axis current control loop to keep iq at zero. In this manner, we can operate the three-phase rectier in a quasi-open-loop mode with the variable d(ud2 ) being treated as the control input of the d-axis system and vdc being the system output. The d-axis current output id may also be treated as an output if needed. Another point to be noted is that the transformed switching functions sa , sb , and sc in the abc frame can be used to switch the six switches of the PWM rectier in different ways depending on the actual PWM scheme adopted. It must be noted that the operation of the equivalent switch S in Fig. 4(b) is only partially linked to the operation of the actual six switches of the converter. The operation of the switches of the converter is in fact determined by the complete switching functions ud , uq and the employed PWM technique. It is also worth noting that the models given in Figs. 3 and 4(b) are valid for any kind of loads, namely resistive loads, constant power loads, and constant current load. A three-phase PWM rectier is often used together with closed-loop dcdc converters as loads, in which case, they are said to be loaded with a constant power load. With such a load, the loads input impedance should be used for system modeling and this will complicate the analysis and verication of the use of the simple SISO model. Since our aim is only the verication of the proposed PWM rectier model, a simple resistive load Rdc has been made use of in the rest of the paper.

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TABLE I COMPARISON BETWEEN A DCDC BOOST CONVERTER WITH A THREE-PHASE ACDC RECTIFIER

D. Small-Signal Model Using the State-Space Averaging Approach Ignoring the parasitic resistance R, the average current and output voltage can be obtained from (14) as Vdc = 2Ed 1D and Id = 8Ed . 3Rdc (1 D)2 (25)

The small-signal transfer functions given in Table I for the variations of the output voltage v dc (s) and input current i d (s) for perturbations in the duty cycle d(s) are obtained by a smallsignal analysis using state-space averaging technique. In obtaining the transfer functions given in Table I, the parasitic resistance of the inductor R has been omitted for claritys sake. This can be easily included and more accurate transfer functions obtained for design purposes, if required. As may be noted, the equations given in Table I are the quasi-open-loop transfer functions of the three-phase PWM rectier. They have been arrived at under the assumption that the decoupling control given in (6) has been implemented and also that the q-axis current is being regulated to be zero. The control-to-output transfer function (20) given in Table I is similar to that of a conventional boost dcdc converter derived based on an averaged model. Like a dcdc boost converter, the three-phase boost-type PWM rectier also suffers from the problem of RHP zero in the control-to-output transfer function. The RHP zero is located at a frequency given by
2 3Ed 3Rdc (1 D)2 = . fz = 16L 4LPdc

This location, as in the dcdc boost converter, is closest to the imaginary axis in the complex s-plane under minimum supply voltage and maximum load. The achievable overall closed-loop bandwidth will be limited to a frequency much less than the frequency location of the RHP zero under the worst-case operation. It can be seen from Table I that the frequency of RHP zero for a three-phase PWM rectier is 3/8 times that of a dcdc boost converter for a similar operating condition. However, as a threephase PWM rectier system typically operates at a switching frequency much lower (ten times or more) than that of a dcdc boost converter, the expected overall closed-loop bandwidth of a three-phase rectier may not be as high as that in the dcdc boost converter system. Thus, the RHP zero imposes a stricter limitation on the achievable performance of the controller in the case of a dcdc boost converter than in the case of a PWM rectier. Next, we will briey investigate the signicance of the RHP zero in a three-phase PWM rectier. Let us suppose that the line inductors are designed such that the voltage drop across the inductor under full-load is x% of the supply voltage. The output power Pdc and the inductor value can be expressed as follows: Pdc = 3 Ed Id 2 and L= xEd 100Id (27)

where Id is the full-load d-axis current and is the line frequency in radians per second. Substituting (27) into (26), we have fz = 100f x (28)

(26)

where f is the line frequency in hertz.

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Fig. 5.

Block diagram for realizing the equivalent SISO system of the PWM rectier. TABLE II LOCATION OF RHP ZERO CORRESPONDING TO THE CHOICE OF THE INDUCTOR VALUE

E. Limitations on Achievable Performance With the equivalent SISO system, as given in Fig. 5, a simple closed-loop control scheme can be implemented for controlling the output voltage, as shown in Fig. 8(a). Here, the PWM rectier operated in a quasi-open-loop fashion described earlier is placed within a voltage control loop to regulate the dc output voltage. This simple direct voltage mode control will be investigated to bring out the limits imposed by the RHP zero on the performance of the three-phase PWM rectier. It is well known that the output performance of a single-phase power factor correction unit is limited by the slow response of the bulky capacitor. This drawback is overcome by a three-phase PWM rectier as it successfully gets rid of the line-frequencyrelated ripple on the dc side. This allows ripple-free output voltage operation to be achieved even with a small lter capacitor. As a result, it may seem that the constraint on achievable performance of the voltage loop is totally eliminated because of the fast change in the dc output voltage in response to changes in the delivered output power. However, this is not really the case, as the achievable performance of the voltage loop depends not only on the size of the capacitor but also on the location of the RHP zero in the system transfer function. To illustrate how these two factors (small size of output capacitor and the presence of RHP zero) affect the output performance, the dynamic operation under a step increase in d-axis duty ratio is explained qualitatively in the following. This explanation is similar to that normally given for describing the time-domain effect of the RHP zero in a dc-to-dc boost converter. A step increase of the ON-time of the virtual switch (corresponding to a step decrease in switching function ud2 ) in the equivalent circuit of Fig. 4(b) increases the discharging time of the output capacitor within a switching period. This results in the output voltage initially dipping, but with a delay due to the output side time constant (=Rdc C). Eventually, the d-axis input current will build up because of the increased ON-time of the switch due to the higher duty ratio value. This increased input inductor current will then result in greater charge owing

It may be noted that the RHP zero location for a given line frequency depends only on the inductor choice. Table II shows the location of RHP zero corresponding to the choice of the inductor value for a line frequency of 50 Hz. Thus, the effect of the RHP zero on the achievable performance will become signicant at a higher switching frequency for a given inductor size. For example, let x = 2% and the switching frequency be equal to 6 kHz. In this case, the corner frequency of RHP zero is at 2.5 kHz (see Table II). In this case, the presence of RHP zero will indeed affect the closedloop performance of the PWM rectier and limit the achievable closed-loop bandwidth. Thus, the effect of the RHP zero on the achievable performance may be expected to be more pronounced at low- and medium-power applications, where the switching frequency will be on the high side. It is also worth noting that during inverter mode operation, when energy is being fed into the ac mains, an ac-to-dc converter can be represented as a buck converter that contains a left s-halfplane zero [11]. Thus, in the inverter mode operation, the PWM rectier system does not suffer from the RHP zero problems. This is also true in the case of a dcdc boost converter. A twoswitch dcdc boost converter merely acts as a buck converter during reverse energy ow, and thus, may be expected not to suffer from any RHP zero problem. Likewise, the resonant corner frequency and the damping ratio can be calculated as f0 = 1D 2 3 8LC and = 1 2Rdc (1 D) 8L . 3C (29)

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TABLE III EXPERIMENTAL RECTIFIER SPECIFICATIONS

into the output capacitor and raise the output voltage even with the reduced capacitor charging time. Thus, the dc output voltage initially changes in the wrong direction and exhibits an undershoot during the immediate interval following the step increase in the duty ratio. Following this initial undershoot, the output voltage recovers and increases ultimately to a higher value as demanded by the increased duty ratio. This provides the physical insight into why the nonminimum phase feature exists in a PWM rectier system. In a voltage mode control scheme, if a step increase is given to the reference voltage, the resulting increase in the duty cycle d (decrease in the switching function ud2 ) will cause an initial dip in the dc output voltage. The voltage loop can start to correct the voltage error only after the dc output voltage begins to increase again following this initial dip. If the voltage control loop attempts a faster restoration of the dc output voltage, a positive feedback action will take place and instability will occur. Therefore, although size reduction in the output capacitor will improve achievable output performance to some extent, the constraint on dynamic performance imposed by the nonminimum phase feature is rooted in the fundamental behavior of the boost-type PWM rectier system. III. OPEN-LOOP EXPERIMENTAL VERIFICATION OF THE PROPOSED SISO MODEL The proposed control scheme was implemented on a DSPACE DSP system (DS1104), which uses a oating processor MPC8240 as the main processor, and a TMS320F240 motion control DSP as an interface with the power converter. A 1-kW prototype has been implemented. The specications for the experimental three-phase boost-type PWM rectier are as shown in Table III. For model verication purposes, the operating conditions were chosen such that the effect of RHP zero on the system performance was signicant. As corner frequency of RHP zero is a function of square of supply voltage [see (26)], using a low supply voltage is a simple way to push the RHP zero close to imaginary axis for power delivered and given inductors value. Large valued inductors were used for the same purpose and also for increasing the rectier input admittance [13], thus reducing the sensitivity to the three-phase ac source especially during open-loop operation. Resistive load was used as dc load for model verication purpose. This part of the experiment focused on the investigation of two aspects of the developed analytical model. These are the verication of the proposed quasi-open-loop operation of the equivalent d-axis SISO model in the frequency domain and the verication of the assumption involved in neglecting the q-axis disturbance on the d-axis performance. As the location of the RHP zero is closest to the imaginary axis in the complex s-plane under maximum d-axis current and

Fig. 6. Experimental d-axis control input-to-dc output voltage Bode plots with a supply voltage of 60 Vrm s , 50 Hz, and a load resistor of 45 quasi-openloop operation.

minimum supply voltage condition based on (26), experiments were carried out with a supply voltage of 60 Vrm s , 50 Hz, and a load of 45 , which results in the worst RHP zero location with regard to the specications in Table III. The corresponding value of ed is 84.8 V. As indicated in Fig. 5, decoupling controls vd1 , vq 1 (corresponding to ud1 , uq 1 ) were employed. Additionally, a current controller (corresponding to uq 2 ) was used in q-axis to make the effect of q-axis current on the d-axis insignicant again, as shown in Fig. 5. As the q-axis dynamics is a rst-order system represented by (12), a simple proportionalintegral (PI) controller with a proportional gain of 0.25 and an integral gain of 16.95 was employed. To bring the converter to a certain operating point (here, 200 V), the duty ratio D can be selected based on (25). For the purpose of measuring the control-to-output transfer functions, a perturbation signal u d2 was introduced from a HP4194A gain-phase analyzer into the control input, as shown in Fig. 5. Fig. 6 shows that the experimental Bode plots closely match the theoretical Bode plots obtained based on the ideal control-to-output transfer function. The control-to-output transfer function given in (20) contains a pair of complex poles and an RHP zero. With the presence of a pair of complex poles at a frequency of about 110 Hz [using (29)], it can be seen from Fig. 6 that the phase rolls down from 0 to 180 and the slope of the magnitude (gain) curve changes from 0 to 40 dB/decade. Also, due to the presence of the RHP zero at about 466 Hz [using (26)], the slope of the gain increases from

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Fig. 8. Structures of voltage mode control scheme and inner-current-controlbased scheme.

a large variation in the q-axis current on the small-signal transfer functions are quite insignicant, typically less than 1 dB in magnitude and 5 in phase for most of the frequency range. Therefore, ignoring of the small disturbance due to the q-axis current on the d-axis dynamics in this model is justied as long as the power factor is kept close to unity. The experimental verication of the frequency-domain responses provided in Figs. 6 and 7 demonstrates the effectiveness of the proposed dual SISO model. Fig. 6 also shows the presence of the RHP zero in the system transfer function. IV. VOLTAGE MODE AND INNER-CURRENT-LOOP-BASED SCHEMES IMPLEMENTED USING THE PROPOSED MODEL In this section, both single-loop voltage mode control and multiple-loop inner-current-control-based scheme are designed based on the proposed SISO model. One purpose is to further justify the effectiveness of the SISO model. Another purpose is to establish the fact that well-documented control and design techniques for the dcdc boost converter are applicable to the control of three-phase PWM rectiers using the proposed model. The specications for the three-phase boost-type PWM rectier are the same as shown in Table III. The location of the RHP zero (see Table I) is closest to the imaginary axis in the complex s-plane under maximum load condition. Thus, the controllers are designed for the worst case with a load of 45 . A. Voltage Mode Control Design The voltage mode controller shown in Fig. 8(a) has a singleloop structure. Here, Fv (s) is the control-to-output transfer function given in (20). A three-pole and two-zero compensator hv (s), which has three cascaded stages, is adopted here. The rst stage hv 1 (s) achieves the desired phase margin at the desired bandwidth. The second stage hv 2 (s) is designed to meet the desired steady-state error. The third stage hv 3 (s) is used to neutralize the effect of the equivalent series resistance (ESR) of the dc output capacitor. The compensator function hv 1 (s) is selected to be a simple lead-lag compensator. The zero of hv 1 (s) is taken as the complex pole pair 0 of the system and the pole of hv 1 (s) is chosen to be ten times 0 . The compensator function hv 2 (s) is selected to be a simple PI controller. The proportional gain is set to unity and the integral gain is selected such that the loop gain at dc is large enough to eliminate steady-state error. At the same time, this

Fig. 7. Magnitude and phase difference curves in the experimental control-tooutput Bode Plots between UPF operation and leading power factor operation (solid line) and between UPF operation and lagging power factor operation (dashed line) with a supply voltage of 60 Vrm s , 50 Hz, and a load resistor of 45 quasi-open-loop operation.

40 to 20 dB/decade and the phase rolls further down toward 270 . The measured curve has a similar shape except for a more damped response caused by the parasitic losses in the system. As mentioned in Section I, the presence of the RHP zero with a corner frequency of 466 Hz will limit the closed-loop bandwidth to a frequency much less than this value. Next, how the changes in the q-axis current affect the dynamics of d-axis was investigated experimentally. The key to the proposed SISO model (9) is the viewing of the term vq 2 iq as a small disturbance from q-axis to d-axis in (8). To verify the effectiveness of the SISO model while ignoring this term, the small-signal control-to-output frequency response curves were determined again with the q-axis current being regulated to be a nonzero value of 2 A. As the d-axis current is 7.5 A in both the cases, the corresponding power factors are around 0.966 leading and lagging, respectively. The power factor value was obtained by taking the ratio of real power (P ) over apparent power (S), which is given as PF = 3ed id /2 p = = S 2 + e2 3 ed i2 + i2 /2 q q d id i2 d + i2 q . (30)

Fig. 7 shows the differences in the experimental magnitude and phase plots of the control-to-output frequency responses between UPF and lagging power factor operations (dash line) and between UPF and leading power factor operations (solid line). As may be noted, the differences introduced by even such

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compensator function must not affect the phase and gain margins already designed. The inclusion of the ESR, rc , in the system model will result in an additional left-half-plane (LHP) zero on the control-to-output transfer function Fv (s). The compensator function hv 3 (s) is selected to be a single-pole function with the pole located close to the zero frequency of 1/(Crc ). This third stage also reduces the effect of switching noise by canceling the 20 dB/decade upwards slope in the loop transfer function resulting from the LHP zero due to the ESR. For simplicity, the transfer functions shown in (20), (22), and (24) do not show the effect of the ESR of the dc output capacitor. Finally, the dc gain of the three-pole and two-zero compensator is selected such that the desired gain crossover frequency is achieved. At the worst-case loading of 45 , the corner frequency of RHP zero is 466 Hz, the corner frequency of resonant peak (complex pole pair) is 692 rad/s, and the corner frequency of the LHP zero associated with the output capacitors ESR is 12 900 rad/s with an estimated ESR value of 0.57 . Based on the design procedure, the three poles of the compensator for the voltage mode control were located at 0 rad/s for tight dc regulation, 6920 rad/s as ten times 0 , and 12 900 rad/s to cancel out the effect of ESR, respectively. The two zeros of the compensator were located at the resonant frequency of 692 rad/s and at a frequency of 125.7 rad/s determined by the integral gain of the PI controller. Here, the realizable closed-loop bandwidth is limited by the corner frequency of the RHP zero. Thus, the dc gain used in experiment was chosen as 0.0045 such that the crossover frequency realized was 200 Hz and the phase margin achieved was 35.3 . B. Design of the Inner-Current-Control-Based Scheme The inner-current-control-based scheme shown in Fig. 8(b) has a widely used cascaded structure. Here, Fi (s) is the controlto-d-axis current transfer function given in (22). In designing a multiloop controller, one rst designs the inner loop. The current controller gi (s) is constructed by two cascaded stage compensators gi1 (s) and gi2 (s) where the rst stage gi1 (s) is selected as a lead-lag compensator and the second stage gi2 (s) is chosen as a PI controller. The design of the cascaded stage compensator gi (s) is similar to the design of the rst two stages of the single-loop controller. Once the current loop is closed, the converter can be treated as a new open-loop plant with transfer function Fv i (s) given in (24). The voltage regulator gv (s) contains three poles and one zero. The rst pole is placed at the origin for tight dc output voltage regulation. The second pole is placed at the corner frequency of the RHP zero to compensate the 20 dB/decade upwards slope resulting from RHP zero. The third pole is placed so as to cancel the ESR zero. The zero of the compensator is placed so as to compensate for the pole due to the output lter circuit in the transfer function Fv i (s). The dc gain is again selected to meet the requirements of the crossover frequency. As in voltage mode control design, in the inner current control design also, the poles of the compensator of inner loop were located at 0 rad/s for tight dc regulation and 6920 rad/s at ten times of 0 , and zeros were placed at the resonant frequency of

692 rad/s and at a frequency of 1257 rad/s determined by the integral gain of the PI controller. With the aforementioned design, the crossover frequency realized is 1000 Hz, which is one-tenth of the switching frequency and the phase margin achieved is 118 for the inner loop. One of advantages of the multiloop controller is that the bandwidth of the d-axis current controller is not limited by the location of the RHP zero. The poles of the compensator of outer loop were located at 0 rad/s for tight dc regulation, 2928 rad/s to compensate the effect of the RHP zero, and 12 900 rad/s to cancel out the effect of ESR, respectively, and the zero was placed at 327 rad/s to compensate for the pole due to the output lter circuit in the transfer function Fv i (s). The dc gains for inner loop and outer loop were 0.0373 and 35.1, respectively. The crossover frequency is 80 Hz, which is less than one-tenth time of the bandwidth of the inner loop and the phase margin achieved is 70.5 for the outer loop. Integrator antiwindup technique was also employed to deal with undesired saturation of the PI controller in both cases. C. Experimental Results Fig. 9 shows the experimental loop transfer function Bode plots obtained with a HP4194A gain-phase analyzer along with the analytically calculated results. With voltage mode control, the experimental crossover frequency and phase margin are 173 Hz and 39.5 . The better measured phase margin is likely due to two factors. First, the damped response due to the parasitic losses causes loop gain to cross 0 dB at a frequency less than the predicted value. Second, parasitic losses also account for a much atter phase response. The measured crossover frequency with a current mode controller is 68 Hz, and the phase margin achieved also be attributed to the parasitic losses in the inductors and switches. The measured crossover frequency with inner-currentcontrol-based scheme is 68 Hz and the phase margin achieved is 70 whereas the theoretical crossover frequency is 80 Hz and the phase margin achieved is 70.5 . The small discrepancy may also be attributed to the parasitic losses in the inductors and switches. Fig. 10 shows the steady-state waveforms with both the voltage mode controller and the inner-current-control-based scheme. The total harmonic distortion (THD) of a-phase current was computed to be 3.86% with voltage mode control and 2.87% with inner-current-loop-based scheme. The resultant three-phase currents are also balanced and in phase with their corresponding supply voltages (not shown here) in both the cases. It is worth noting that the current obtained with voltage mode control shows a pronounced attop characteristic. It is due to nonperfect behavior of the voltage mode control. As the current guidance loop is absent, it is not surprising that the performance with regard to the waveform is inferior. Fig. 11 shows the transient responses of the dc output voltage, d-axis current, and a-phase current for a step change in the load from 45 to 60 and back to 45 . The single-loop system exhibits a slightly better transient performance for a load step change. This can be explained with the theoretical frequency responses of output impedance shown in Fig. 12. It can be

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Fig. 9.

Bode plots of the loop transfer function at a maximum load of 45 (a) with voltage mode controller and (b) with inner-current-control-based scheme.

Fig. 10. Experimental waveforms for steady-state operation: three-phase balanced current and output voltage. (a) Voltage mode control. (b) Inner-current-loopbased scheme.

seen that both the controllers provide attenuation of the openloop output impedance; however, the output impedance with the single-loop control is much lower than that with the multiloop control in the frequency range between 16 and 200 Hz. This is the likely reason that the single-loop system exhibits a slightly better transient performance for load step changes. Additional results obtained with both inner-current-controlbased scheme and voltage mode controller can be found in [20]. From the results, we can conclude that both the voltage mode

controller and the inner-current-control-based scheme yield satisfactory steady-state and transient performances. Among the two control systems, the inner-current-control-based scheme exhibits similar or better performance than the voltage mode control system in most aspects. With the inner-current-controlbased scheme, directly controlling the current feeding the output stage makes the voltage-to-current transfer function a rst-order system with an RHP zero, thus largely simplifying the dynamic behavior of the feedback control system. Besides faster overall

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Fig. 11.

Experimental step response for a step change in load. (a) Voltage mode control. (b) Inner-current-control-based scheme.

It was also noted that both the d-axis large-signal averaged model and its equivalent circuit were similar to those of a dc-todc boost converter. Based on this insight, voltage mode control and inner-current-control-based schemes of the types widely used in dc-to-dc converters have been proposed for the threephase PWM rectiers. Experimental steady-state and transient results conrm theoretical expectations, thereby demonstrating the usefulness of the proposed SISO model. REFERENCES
[1] J. R. Rodrigues, J. W. Dixon, J. R. Espinoza, J. Pontt, and P. Lezana, PWM regenerative rectiers: State of art, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 522, Feb. 2005. [2] M. Liserre, R. Teodorescu, and F. Blaabjerg, Multiple harmonics control for three-phase grid converter systems with the use of PI-RES current controller in a rotating frame, IEEE Trans. Power Electron., vol. 21, no. 3, pp. 836841, May 2006. [3] V. Blasko and V. Kaura, A new mathematical model and control of a threephase ACDC voltage source converter, IEEE Trans. Power Electron., vol. 12, no. 1, pp. 116123, Jan. 1997. [4] H. Komurcugil and O. Kukrer, Lyapunov-based control for three-phase PWM AC/DC voltage-source converters, IEEE Trans. Power Electron., vol. 13, no. 5, pp. 801813, Sep. 1998. [5] T. S. Lee, Input-output linearization and zero-dynamics control of threephase AC/DC voltage-source converters, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 1122, Jan. 2003. [6] D. C. Lee, G. M. Lee, and K. D. Lee, DC-bus voltage control of threephase AC/DC PWM converters using feedback linearization, IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 826833, May/Jun. 2000. [7] Y. Ye, M. Kazerani, and V. H. Quintana, Modeling, control and implementation of three-phase PWM converters, IEEE Trans. Power Electron., vol. 18, no. 3, pp. 857864, May 2003. [8] H. C. Mao, D. Boroyevich, and C. Y. Lee, Novel reduced-order smallsignal model of a three-phase PWM rectier and its application in control design and system analysis, IEEE Trans. Power Electron., vol. 13, no. 3, pp. 511521, May 1998. [9] S. Chattopadhyay and V. Ramanarayanan, Digital implementation of a line current shaping algorithm for three phase high power factor boost rectier without input voltage sensing, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 709721, May 2004. [10] T. T. Jin and K. M. Smedley, A universal vector controller for fourquadrant three-phase power converters, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 54, no. 2, pp. 377390, Feb. 2007. [11] J. W. Kolar, H. Ertl, L. Edelmoser, and F. C. Zach, Analysis of the control behavior of a bidirectional three-phase PWM rectier system, in Proc. Eur. Conf. Power Electron. Appl., Sep. 1991, pp. 2-0952-100. [12] S. Hiti and D Boroyevich, Control of front-end three-phase boost rectier, in Proc. IEEE Appl. Power Electron. Conf. Expo., 1994, vol. 2, pp. 927933.

Fig. 12.

Comparison of theoretical output impedance curves.

dynamics (see experimental results given in [20]), having a current control loop makes it easy to implement overcurrent protection. Since anyhow current sensors are required for implementing the decoupling terms (see Fig. 5), implementing the current control loops will not impose an additional hardware burden on the system.

V. CONCLUSION A simple SISO model for a three-phase PWM rectier has been developed in this paper. The model allows the input power factor and output dc voltage to be regulated independently in the q-axis and d-axis, respectively. Using the proposed SISO model, the problem of the RHP zero associated with a three-phase PWM rectier has been highlighted and explored analytically and its effect on the achievable performance has been fully investigated. The open-loop characteristic of the equivalent SISO system has been investigated through analysis and experiments. The results have shown that the proposed SISO model, though simple, can indeed reect accurately the characteristics of a three-phase PWM rectier.

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[13] S. Hiti, D. Boroyevich, and C. Cuadros, Small-signal modeling and control of three-phase PWM converters, in Proc. Ind. Appl. Soc. Annu. Meeting, Oct. 1994, vol. 2, pp. 11431150. [14] D. Graovac and V. Katic, A method of PWM rectier control in voltage linked AC/DC/AC converter, in Proc. 9th Mediterranean Electrotech. Conf. (MELECON 1998), May, vol. 2, pp. 10321036. [15] R. Gabriel and W. Leonhard, Field-oriented control of a standard AC motor using microprocessor, IEEE Trans. Ind. Appl., vol. IA-16, no. 2, pp. 186192, Mar. 1980. [16] J. Holtz and S. Stadtfeld, Field oriented control by forced motor currents in a voltage fed inverter drive, in Proc. Eur. Conf. Power Electron. Appl., Brussels, Belgium, 1985, pp. 3.213.25. [17] C. T. Rim, D Y. Hu, and G. H. Cho, Transformers as equivalent circuits for switches: General proofs and D-Q transformation-based analyses, IEEE Trans. Ind. Appl., vol. 26, no. 4, pp. 777785, Jul./Aug. 1990. [18] J. Chen and K. D. T. Ngo, Graphical phasor analysis of three-phase PWM converters, IEEE Trans. Power Electron., vol. 16, no. 5, pp. 659666, Sep. 2001. [19] B. Yin, R. Oruganti, S. K. Panda, and A. K. S. Bhat, Experimental verication of a dual single-input single-output (SISO) model of a threephase boost-type PWM rectier, in Proc. 31st IEEE Conf. Ind. Electron. Soc., 2005, pp. 10301035. [20] B. Yin, R. Oruganti, S. K. Panda, and A. K. S. Bhat, Performance comparison of voltage mode control and current mode control of a three-phase PWM rectier based on dual SISO model, in Proc. 32nd IEEE Conf. Ind. Electron. Soc., Paris, France, Nov. 2006, pp. 19081914.

Sanjib Kumar Panda (S86M91SM01) received the B.Eng. degree from the Regional Engineering College (REC), Surat, India, in 1983, the M.Tech. degree from the Institute of Technology, Banaras Hindu University, Varanasi, India, in 1987, and the Ph.D. degree from the University of Cambridge, Cambridge, U.K., in 1991, all in electrical engineering. Since 1992, he has been a faculty member in the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor. His current research interests include control of electric drives and power electronic converters, energy harvesting, renewable energy, assistive technology, and mechatronics. Dr. Panda received the Nehru Cambridge Fellowship jointly awarded by the Nehru Trust for Cambridge University and Cambridge Commonwealth Trust in 1987. He was the Chairman of the IEEE Singapore Section in 2003. He was the Conference Organizing Chairman for the IEEE Power Electronics and Drive Systems (PEDS03) Conference and is the Conference Organizing Chairman for the IEEE International Conference on Sustainable Energy Technologies (ICSET 2008). He is also the recipient of the IEEE Third Millennium Medal.

Bo Yin (S04M07) received the B.Eng. and M.Eng. degrees in electrical engineering from Wuhan University, Wuhan, China, in 2000 and 2003, respectively. She is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, National University of Singapore, Singapore. In 2007, she joined the Electrical R&D Department, Vestas Wind System A/S, Vestas Technology R&D Singapore Pte Ltd., Singapore, where she is currently a Senior R&D Engineer in the Converter Design Group. Her current research interests include advanced control of power converter, power quality, design and control of wind turbine systems, and power electronics.

Ashoka K. S. Bhat (S82M85SM87F98) received the B.Sc. degree in physics and mathematics from Mysore University, Mysore, India, in 1972, the B.E. degree (with distinction) in electrical technology and electronics and the M.E. degree (with distinction) in electrical engineering from the Indian Institute of Science, Bengaluru, India, in 1975 and 1977, respectively, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Toronto, Toronto, ON, Canada, in 1982 and 1985, respectively. From 1977 to 1981, he was a Scientist in the Power Electronics Group, National Aeronautical Laboratory, Bengaluru, and was responsible for the completion of a number of research and development projects. He was a Postdoctoral Fellow for a brief period. In 1985, he joined the Department of Electrical Engineering, University of Victoria, Victoria, BC, Canada, where he is currently a Professor of electrical engineering, is engaged in teaching and conducting research in the area of power electronics, and was responsible for the development of the electromechanical energy conversion and power electronics courses and laboratories in the Department of Electrical Engineering. Prof. Bhat is a Fellow of the Institution of Electronics and Telecommunication Engineers (India). He is a Registered Professional Engineer in the province of British Columbia, Canada.

Ramesh Oruganti (S83M85SM01) received the B.Tech. and M.Tech. degrees from the Indian Institute of Technology Madras, Chennai, India, and the Ph.D. degree from Virginia Polytechnic Institute and State University, Blacksburg, in 1987. He was engaged in the area of power conversion for several years in India. He was with the Corporate R&D Division, General Electric Company, USA, where he was involved in the eld of advanced power converter systems. Since 1989, he has been with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor and the Director of the Centre for Power Electronics. He is also a Visiting Academic in the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, N.S.W., Australia. He is active in research on several areas of power electronics. His current research interests include power electronic applications in renewable energy. He has authored or coauthored several papers in power electronics. He holds a patent on dcdc converters. Dr. Oruganti has received Two Prize Paper Awards.

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