BJT Inverter (Transistor Switch)

Transistors (BJT) are widely used in digital logic circuits and switching applications. The fundamental transistor circuit used in switching applicationsiscalledaninverter.
The transistor is in CE configuration and no bias voltageisconnectedtothebasethrougharesistor, but a resistor RB is connected in series with the base and then directly to a pulsetype wave that servesastheinvertersinput.Inthecircuit,VCC and the high level of input are both +5V. The output is thevoltagebetweencollectorandemitter(VCE =vout) .

S.Kal,IITKharagpur

Whentheinputishigh(+5V),theBEjn. is forward biased and current flows through RB in to the base. The values of RB and RC are chosen such that the IB is enough to saturate the transistor. Note thatthevalueofVCE insaturationisnearly 0 ( typically VCE(sat) 0.2 V ). When the transistor is saturated, it is said to be ON and the high input to the inverter (+ 5 V) resultsinalowoutput( 0V). Whentheinputtothetransistorislow,ie, 0 V, the BE jn. is not forward biased, so no base current, and hence no collector current flows. There is no voltage drop across RC and it follows that VCE = VCC. The transistor is in cut off region and is saidtobeOFF.Alowinputtotheinverter resultsinahighoutputandthusthecircuit iscalledanInverter.

S.Kal,IITKharagpur
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InverterDesign

In designing inverter, it is assumed that IC(sat) = VCC/RC and VCE(sat)=0 Sincethetransistoriscutoffwhentheinputislow,regardless ofthevaluesofRB andRC,theequationstobeusedarethose thatapplywheninputishigh.

VCC=VCE+ICRC IC=IC(sat)=VCC/RC IB=IC(sat)/ =VCC/ RC

and IB = ( VH VBE) / RB where VH is high level of the input voltage.

To design a transistor inverter we must have criteria for specifyingthevaluesofRBandRC.Typically,oneofthevalues is chosen, and the value of the other is derived. The S.Kal,IITKharagpur relationshipofRBandRCare

InverterDesign
RB=(VHVBE)/IB=(VHVBE) RC/VCC

RC=VCC/ IB=VCCRB/ (VHVBE) Sincetheseequationsarevalidforaspecificvaluesof ,theyare not entirely practical. varies over a wide range. If the actual value of is smaller than the one used in the design equations, the transistor will not saturate. So in design eqn. must be smallestpossiblevaluethatmightoccurinagivenapplication.So theRBandRCareexpressedintheformofinequalities, RB (VHVBE)/IB=(VHVBE) RC/VCC RC VCC/ IB=VCCRB/ (VHVBE)

S.Kal,IITKharagpur

DiodeLogic(ORgate)

A=low,B=low,bothdiodesD1

and D2 are nonconducting, so output,y=0

A=high,B=low,D1 conducts,D2 is nonconducting, so output, y = (50.7)V=4.3V(high) A=low,B=high,D2 conducts,D1 is nonconducting. Therefore, output, y = (5 0.7) V = 4.3 V (high) A = high, B = high, both diodes D1 and D2 are conducting. Therefore,outputy=(50.7)V=4.3V(high)
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DiodeLogic(ANDgate)

If any of the input is 0, that particular diode is forward biased and the output voltage(y)willbediodedrop, i.e.y=0.7V(logic0) WhenA=high,B =high,i.e. both inputs are at 5 V, both the diodes (D1, D2) are not conducting because the voltage across the diodes is 0. Since no current flows through RL, the output is pulled on to the supply voltage(VCC=5V).Therefore, y=high.

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ResisterTransistorLogic(RTL)NORgate

Ifanyoftheinputs(A,B)becomeshigh(=5V),thatparticular transistor goes into saturation and the output is almost 0 V (= VCE(sat)). Ifboththeinputs(A,B)areatlogiclowlevel(logic0=0V),then switches are cut off and no current flows through RL. So the outputy=+5V(logichigh).

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DiodeTransistorLogic(DTL)NANDgate

IfanyinputAorBorbothA& B are low, Diode D1 / D2 conducts and point X will be at0.7volts T1Off&y=High If A and B are high (5V), diodesD1,D2 willnotconduct, butD3,D4 conductsandsoT1 on (saturation) as the voltageatpointXismorethan 2.1V y=VCE(SAT)andoutputofT1 =Low ThusthecircuitisaNANDgate
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TransistorTransistorLogic(TTL)Inverter

TTL introduced by Texas Instruments in 1964 is a widely usedlogicfamilyofdigitalcircuits. In TTL, base of T2 is connected to collector of T1 whose emitter is used as input terminal. The emitter of T2 is grounded and its base voltage and hence the collector of T1 will not rise above 0.75 V[ VBE(sat)]. If vin is high(~ 5V),theBEJnofT1 isreversebised anditsCBjnisforwardbiased.Thus, thetransistorT1 isininversemodeof operation.ThenIC1 drivesT2 anditwill beON. 1.vin=high,T1isininversemode,T2=ON,vout=VCE(sat)=low 2.vin=low,T1isinnormalmode,T2=cutoff,vout=Vcc=high
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TTLNANDgate

If any of the inputs is at logic level 0, T1, is in normal mode of operation, T3 cut off. outputisatlevel1 If all the inputs are at logic 1, T3 is in saturation and the output is at logic 0. Emitter of T1 5V,BaseofT1 <5V,BE jn R.B. Base of T3 0.75 (maxm).CBjnofT1 F.B.T1 worksininversemodeIC1 IB2 T3 drives into saturation, Y = VCE(sat)ofT3

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TTLNANDGatewithTotemPoleoutput
IntegratedcircuitTTLisfabrica ted with a totempole pair output circuit to allow high speed switching and a large fanout. In an IC TTL NAND gate, T1 and T2 are integrated into a single transistor with two emitters. If necessary, more emitters can be fabricated on the same base and multiple inputTTLgatesmaybe obtained. Each emitter acts like a diode; therefore, T1 with 4k resistor (RB) acts like twoinput AND gate. The rest of the circuit invertsthesignalandtheoverallcircuitactslikeatwoinputNAND gate
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TTLNANDGatewithTotemPoleoutput
The input voltages A and B are either low (grounded) or high (5V). If A or B is low, T1 saturates. This reduces the base voltage of T2 to almost zero. Therefore, T2 cuts off, forcing T4 to cut off. Under these conditions, T3 acts like an emitter follower and couples a high voltage to the output. On the other hand, when both A and B are high, the collector-base junction of T1 becomes forward biased and its collector diode goes into forward condition; this forces T2 and T4 into saturation, producing a low output. Incidentally, without diode D1 in the circuit, T3 would conduct slightly when the output is low. The voltage drop by the diode keeps base-emitter diode of T3, reverseS.Kal,IITKharagpur biased. So only T4 conducts when the output is low. Thus, the circuit behaves as a NAND gate.

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TTLNANDGatewithTotemPoleoutput
The output transistors (T3 and T4) form a totem-pole connection. Either transistor T3 or transistor T4 is on. The output is high when T3 is on and it acts like an emitter follower. The output is low when T4 is on and no current flows through RC. This is important because it keeps the circuit power dissipation down.

The advantage of a totem-pole connection is its lowoutput impedance, which reduces the switching time. The advantage of this arrangement occurs in the output high state. Here T3 is acting as emitter follower with its associated low output impedance (typically, 10 ). This low-output impedance provides a short time constant (RC) for charging up any capacitive load (C) on the output. This action is known as active pull-up and provides very fast rise-time waveforms at TTL outputs.

A standard TTL gate has a power dissipation of about 10 mW and a propagation delay time of nearly 10 ns.

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NMOSInverterandLogicGates
1.

2.

3. 4.

MOSFETs can act both as amplifier / driver and as a load resistor, eliminating the need for ordinary load resistors, which consume large area in siliconICs. MOSFETs take up very little area compared to SiBJTs so that more circuitscanbeformedonawafer. Circuits using MOSFETs have higher yield. Enhancement type MOSFETs are preferred over depletion type because theformercanbeswitchedONorOFF with the supply and also a single polaritysupplyissufficient.
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NMOSInverter
InabasicNMOSinvertercircuit,twoNchannelMOSFETs(M1 andM2)

areusedinthiscircuit.Insteadofpassiveresistiveload,M1 isusedas an active load while M2 is used as a switching/driver transistor. M1 is always in ON state, as it is permanently connected to +5 V and essentiallyRONwillbetheloadresistance.Inresponsetotheinputgate source voltage (Vin), M2 will switch from ON to OFF state. M1 is designed to have a narrower channel than M2 so that ON state resistance (RON) of M1 is greater than that of M2. Typically, RON of M1 and M2 are 100 k and 1 k , respectively. ROFF of M2 is around 1010 . WemanyanalyzethiscircuitconsideringeachMOSFETchannelasa resistancesothatoutputvoltageistakenfromavoltagedividerformed bytworesistances.WithVin =0V,M2 isoff,withaverylargechannel resistanceof1010 .SinceM1 hasRON 100k ,thevoltagedivider output will be essentially 5V. Onother hand,withVin =5 V, M2 is on, withRON 1k .Thevoltagedivideroutputisnownearly0.05V.Thus, S.Kal,IITKharagpur the circuit functions as an inverter since a low input produces a high 16 output,andviceversa.

(a)MOSNANDgate(b)MOSNORgate
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CMOSInverter

CMOS inverter utilizes two matched enhancement type MOSFETs:oneM2, withnchannelandtheotherM1,withap channel.Thebodyofeachdeviceisconnectedtoitssource andthusnobodyeffectarises. In a CMOS switch, nMOS and pMOS are joined at their drains and the series combination is connected across the supply voltage (VSS). +Vss is connected with source pMOS andVss isconnectedtothesourceofnMOSandgrounded. Theoutputistakenatcommondrainandtheinputisapplied incommontobothgates.BothpMOSandnMOStransistors operate in Emode. Vi swings from ground voltage (~0V) to +VSS.
S.Kal,IITKharagpur

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CMOSInverter

WhenVi ground~0V,M2will beOFF,becauseVGS(QN){~0}< VTandM1willbeON,because, VGS(M1){~VSS}>VT. V0=VSS.

When Vi VSS, (logic high) M2 will be ON, because VGS(QN) {~VSS} >VT and M1 will be OFF, because, VGS(M1) { ~ 0} < VT V0 = 0. High gm of M2 will . have small drop w.r.t. ground. GateofM1 isatzerovoltswith respecttosource

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AdvantagesofCMOSInverter

InCMOS,V0=fullsupplyvoltage,whenVi=0. WhenVi VSS,V0approachesaverylowvalue( 10mV) Transitionbetweentwolevels(0andVSS)muchsharp When switch is at one or the other limit of its range, its powerdissipationisnormallyzero.BecauseinHighorLow case one or the other FET is cut off. The current supplied by the supply voltage is nominally zero ( except leakage current 10nA). Impedance looking into the gate of FET is 109 , so in thequiescentcondition,thereisnopowerdissipation.
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CMOSNANDgate

CMOSNORgate
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