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# Flip-Flops

extracts from:
http://www.elec.uq.edu.au/~3e211/pracs/prac2/prac2.htm Dept. of Computer Science and Electrical Engineering The University of Queensland St. Lucia Qld 4072 Australia

The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the stored bit. Binary information can enter a flip-flop in a variety of ways and gives rise to different types of flipflops.

## Introduction - Basic Flip-Flop Circuit

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop or SR latch. The flip-flop in Figure 2 has two useful states. When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal output. When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q' outputs go to 0. This condition violates the fact that both outputs are complements of each other. In normal operation this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.

## (a) Logic diagram

(b) Truth table Figure 2. Basic flip-flop circuit with NOR gates
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## (a) Logic diagram

(b) Truth table Figure 3. Basic flip-flop circuit with NAND gates The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the state of the flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition should be avoided in normal operation.
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## Introduction - Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

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## (b) Truth table Figure 4. Clocked SR flip-flop

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Introduction - D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.

## (c) Transition table Figure 5. Clocked D flip-flop

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Introduction - JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1. Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T flip-flop presented next.

## (c) Transition table Figure 6. Clocked JK flip-flop

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Introduction - T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.

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## Introduction - Triggering of Flip-flops

The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require an input trigger defined by a change in signal level. This level must be returned to its initial level before a second trigger is applied. Clocked flip-flops are triggered by pulses. The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to make the flip-flop sensitive to the pulse transition rather than the pulse duration. The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in Figure 8 the positive transition is defined as the positive edge and the negative transition as the negative edge.

Figure 8. Definition of clock pulse transition The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state transition starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is still 1, a new output state may occur. If the flip-flop is made to respond to the positive (or negative) edge transition only, instead of the entire pulse duration, then the multipletransition problem can be eliminated.
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## Introduction - Master-Slave Flip-Flop

A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flipflop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

Figure 9. Logic diagram of a master-slave flip-flop The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master.

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## Introduction - Edge Triggered Flip-Flop

Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered). The logic diagram of a D-type positive-edge-triggered flipflop is shown in Figure 11.

Figure 11. D-type positive-edge triggered flip-flop When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs make their transitions at the same time, ie., during either the negative edge or the positive edge of the clock pulse.
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## Introduction - Direct Inputs

Flip-flops in IC packages sometimes provide special inputs for setting or clearing the flip-flop asynchronously. They are usually called preset and clear. They affect the flip-flop without the need for a clock pulse. These inputs are useful for bringing flip-flops to an intial state before their clocked operation. For example, after power is turned on in a digital system, the states of
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the flip-flops are indeterminate. Activating the clear input clears all the flip-flops to an initial state of 0. The graphic symbol of a JK flip-flop with an active-low clear is shown in Figure 12.

## (b) Transition table Figure 12. JK flip-flop with direct clear

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Preparation
Prepare the following in your prac book: Basic Flip-Flop i. ii. Draw the logic circuit for an unclocked NOR gate flip-flop. Enter the expected timing diagram for signals Q and Q' in Figure 13.

Figure 13. NOR gate flip-flop timing diagram iii. iv. Draw the logic circuit for an unclocked NAND gate flip-flop. Enter the expected timing diagram for signals Q and Q' in Figure 14.

Figure 14. NAND gate flip-flop timing diagram Master-Slave Flip-Flop i. ii. Draw the logic circuit implemented with gates for the SR master-slave flip-flop in Figure 9. Use NOR gate flip-flops. Enter the expected timing diagram for the signals Y, Y', Q, and Q' in Figure 15.

Figure 15. SR master-slave flip-flop timing diagram Edge Triggered Flip-Flop i. ii. Draw the logic circuit for the D-type positive-edge triggered flip-flop in Figure 11. Enter the expected timing diagram for the signals S, R, Q, and Q' in Figure 16.

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## Figure 16. D-type edge triggered flip-flop timing diagram

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Procedure
Use LogicWorks to simulate the circuits that you have prepared. Use switches from the I/O library for the inputs and probes from the I/O library for the outputs. Place signal names on the circuit so that the signals are visible in the timing window. Create a separate drawing for each circuit. To be sure that your circuits don't cross the printing page boundaries, check the Show Page Outlines option from the Drawing|Display Options... menu. Only print out the circuit and waveforms for the SR master-slave flip-flop.
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Equipment

## Computer - Room 47-405

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References

Mano, M., "Digital Design", Prentice/Hall, 1984. Chapter 6. Smith, R., "Circuits, Devices and Systems", Wiley, 1980. "LogicWorks for Windows 3.0" by Capilano Computing Systems, Ltd., Addison-Wesley, 1995.
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## 74LS Device Data

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2 METHOD
Flip-flop (electronics)

An SR latch, constructed from a pair of cross-coupled NOR gates. Red and black mean logical '1' and '0', respectively.

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edgetriggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.

Contents
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1 History 2 Implementation 3 Flip-flop types o 3.1 Simple set-reset latches 3.1.1 SR NOR latch 3.1.2 SR NAND latch 3.1.3 JK latch o 3.2 Gated latches and conditional transparency 3.2.1 Gated SR latch 3.2.2 Gated D latch 3.2.3 Earle latch o 3.3 D flip-flop 3.3.1 Classical positive-edge-triggered D flip-flop 3.3.2 Masterslave pulse-triggered D flip-flop 3.3.3 Edge-triggered dynamic D storage element o 3.4 T flip-flop o 3.5 JK flip-flop 4 Metastability 5 Timing considerations o 5.1 Setup and hold times o 5.2 Propagation delay 6 Generalizations 7 See also 8 References

 History

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Flip-flop schematics from the Eccles and Jordan patent filed 1918, one drawn as a cascade of amplifiers with a positive feedback path, and the other as a symmetric cross-coupled pair

The first electronic flip-flop was invented in 1918 by William Eccles and F. W. Jordan. It was initially called the EcclesJordan trigger circuit and consisted of two active elements (vacuum tubes). Such circuits and their transistorized versions were common in computers even after the introduction of integrated circuits, though flip-flops made from logic gates are also common now. Early flip-flops were known variously as trigger circuits or multivibrators. A multivibrator is a two-state circuit; they come in several varieties, based on whether each state is stable or not: an astable multivibrator is not stable in either state, so it acts as a relaxation oscillator; a monostable multivibrator makes a pulse while in the unstable state, then returns to the stable state, and is known as a one-shot; a bistable multivibrator has two stable states, and this is the one usually known as a flip-flop. However, this terminology has been somewhat variable, historically. For example:

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1942 multivibrator implies astable: "The multivibrator circuit (Fig. 7-6) is somewhat similar to the flip-flop circuit, but the coupling from the anode of one valve to the grid of the other is by a condenser only, so that the coupling is not maintained in the steady state." 1942 multivibrator as a particular flip-flop circuit: "Such circuits were known as 'trigger' or 'flipflop' circuits and were of very great importance. The earliest and best known of these circuits was the multivibrator." 1943 flip-flop as one-shot pulse generator: "It should be noted that an essential difference between the two-valve flip-flop and the multivibrator is that the flip-flop has one of the valves biased to cutoff." 1949 monostable as flip-flop: "Monostable multivibrators have also been called 'flip-flops'." 1949 monostable as flip-flop: "... a flip-flop is a monostable multivibrator and the ordinary multivibrator is an astable multivibrator."

According to P. L. Lindley, a JPL engineer, the flip-flop types discussed below (RS, D, T, JK) were first discussed in a 1954 UCLA course on computer design by Montgomery Phister, and then appeared in his book Logical Design of Digital Computers. Lindley was at the time working at Hughes Aircraft under Dr. Eldred Nelson, who had coined the term JK for a flip-flop which changed states when both inputs were on. The other names were coined by Phister. They differ slightly from some of the definitions given below. Lindley explains that he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is responsible for coining the term while working at Hughes Aircraft. Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Nelson used the notations "j-input" and "k-input" in a patent application filed in 1953.

 Implementation

## A traditional latch circuit based on bipolar junction transistors

Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous); the transparent ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.

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Simple flip-flops can be built around a pair of cross-coupled inverting elements: vacuum tubes, bipolar transistors, field effect transistors, inverters, and inverting logic gates have all been used in practical circuits. Clocked devices are specially designed for synchronous systems; such devices ignore their inputs except at the transition of a dedicated clock signal (known as clocking, pulsing, or strobing). Clocking causes the flip-flop to either change or retain its output signal based upon the values of the input signals at the transition. Some flip-flops change output on the rising edge of the clock, others on the falling edge. Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a cascade) to form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as an active inverting feedback network for the other inverting amplifier. Thus the two stages are connected in a non-inverting loop although the circuit diagram is usually drawn as a symmetric cross-coupled pair (both the drawings are initially introduced in the EcclesJordan patent).

##  Flip-flop types

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, , in terms of the input signal(s) and/or the current output, .
 Simple set-reset latches  SR NOR latch

An SR latch, constructed from a pair of cross-coupled NOR gates (an animated picture). Red and black mean logical '1' and '0', respectively.

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q. While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the
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Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
SR latch operation SR 00 01 10 Action No Change Q=0 Q=1 The symbol for an SR NOR latch

1 1 Restricted combination

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency digital circuits. Although this condition is usually avoided, it can be useful in some applications. To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-restricted combinations. That can be:

Q = 1 (1,0) referred to as an S-latch Q = 0 (0,1) referred to as an R-latch Keep state (0,0) referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch. Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.
 SR NAND latch

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An SR latch

This is an alternate model of the simple SR latch built with NAND (not AND) logic gates. Set and reset now become active low signals, denoted S and R respectively. Otherwise, operation is identical to that of the SR latch. Historically, SR-latches have been predominant despite the notational inconvenience of active-low inputs.[citation needed]
SR latch operation SR Action

0 0 Restricted combination 01 Q=1 10 Q=0 1 1 No Change  JK latch Symbol for an SR NAND latch

The JK latch is much less used than the JK flip-flop. The JK latch follows the following state table:
JK latch truth table J K Qnext Comment 00Q 010 101 11Q No change Reset Set Toggle

Hence, the JK latch is an SR latch that is made to toggle its output when passed the restricted combination of 11. Unlike the JK flip-flop, the 11 input combination for the JK latch is not useful because there is no clock that directs toggling.

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##  Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output; when several transparent latches follow each other, using the same clock signal, signals can propagate through all of them at once. Alternatively, additional logic can be added to a simple transparent latch to make it non-transparent or opaque when another input (an "enable" input) is not asserted. By following a transparent-high latch with a transparent-low (or opaquehigh) latch, a masterslave flip-flop is implemented.
 Gated SR latch

## A gated SR latch circuit diagram constructed from NOR gates.

A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable). With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent. With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high. The enable input is sometimes a clock signal, but more often a read or write strobe.

E/C

Action

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## A gated D latch based on an SR NOR latch

This latch exploits the fact that in the two active input combinations (01 and 10) of a gated SR latch R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to these two input combinations for the next SR latch by inverting the data input signal. The low state of the enable signal produces the inactive "11" combination. Thus a gated D-latch may be considered as a one-input synchronous SR latch. This configuration prevents from applying the restricted combination to the inputs. It is also known as transparent latch, data latch, or simply gated latch. It has a data input and an enable signal (sometimes named clock, or control). The word transparent comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q. Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronous two-phase systems (synchronous systems that use a two-phase clock), where two latches operating on different clock phases prevent data transparency as in a masterslave flip-flop. Latches are available as integrated circuits, usually with multiple latches per chip. For example, 74HC75 is a quadruple transparent latch in the 7400 series.

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E/C

Comment

Qprev

Qprev

No change

Reset

## Symbol for a gated D latch

Set

The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/C is high, the output equals D.
 Earle latch

Earle latch uses complementary Enable inputs: Enable active Low (E_L) and Enable active High (E_H)

The classic gated latch designs have some undesirable characteristics. They require doublerail logic or an inverter. The input-to-output propagation may take up to three gate delays. The input-to-output propagation is not constant some outputs take two gate delays while others take three. Designers looked for alternatives. A successful alternative is the Earle latch. It requires only a single data input, and its output takes a constant two gate delays. In addition, the two gate levels of the Earle latch can be merged with the last two gate levels of the circuits driving the latch. Merging the latch function can implement the latch with no additional gate delays.

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The Earle latch is hazard free. If the middle NAND gate is omitted, then one gets the polarity hold latch, which is commonly used because it demands less logic. Intentionally skewing the clock signal can avoid the hazard.
 D flip-flop

D flip-flop symbol

The D ip-op is widely used. It is also known as a data or delay flip-flop.[citation needed] The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. . The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.[citation needed] Truth table:
Clock D Qnext 0 1

## Rising edge 0 Rising edge 1

Non-Rising X Q

('X' denotes a Don't care condition, meaning the signal is irrelevant) Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as described above.
Inputs S R D > 0 1 X X Outputs Q 0 Q' 1

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1 0 X X 1 1 X X

1 1

0 1

## 4-bit serial-in, parallel-out (SIPO) shift register

These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock. The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position.
 Classical positive-edge-triggered D flip-flop

A positive-edge-triggered D flip-flop

This clever circuit consists of two stages implemented by SR NAND latches. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the
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lower output becomes low; if D = 1, the upper output becomes low. If the clock signal continues staying high, the outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state as the input logical zero remains active while the clock is high. Hence the role of the output latch is to store the data only while the clock is low. The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) to two input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuits split the single D signal in two complementary S and R signals). The difference is that in the gated D latch simple NAND logical gates are used while in the positive-edge-triggered D flip-flop SR NAND latches are used for this purpose. The role of these latches is to "lock" the active output producing low voltage (a logical zero); thus the positive-edge-triggered D flip-flop can be thought of as a gated D latch with latched input gates.
 Masterslave pulse-triggered D flip-flop

A masterslave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called masterslave because the second latch in the series only changes in response to a change in the first (master) latch. The term pulse-triggered means that data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of the clock pulse.[dubious discuss]

A masterslave D flip-flop. It responds on the negative edge of the enable input (usually a clock)

An implementation of a masterslave D flip-flop that is triggered on the positive edge of the clock

For a positive-edge triggered masterslave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the "master" latch to store the input value when the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now
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"locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge. By removing the leftmost inverter in the circuit at side, a D-type flip flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this:
DQ > Qnext

0 X Falling 0 1 X Falling 1

A CMOS IC implementation of a "true single-phase edge-triggered flip-flop with reset"  Edge-triggered dynamic D storage element

An efficient functional alternative to a D flip-flop can be made with dynamic circuits as long as it is clocked often enough; while not a true flip-flop, it is still called a flip-flop for its functional role. While the masterslave D element is triggered on the edge of a clock, its components are each triggered by clock levels. The "edge-triggered D flip-flop", as it is called even though it is not a true flip-flop, does not have the masterslave properties. Edge-triggered D flip-flops are often implemented in integrated high-speed operations using dynamic logic. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This design of dynamic flip flops also enables simple resetting since the reset operation can be performed by simply discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC) type which performs the flip-flop operation with little power and at high speeds. However, dynamic flip-flops will typically not work at static or low clock speeds: given enough time, leakage paths may discharge the parasitic capacitance enough to cause the flip-flop to enter invalid states.

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 T flip-flop

## A circuit symbol for a T-type flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:
(expanding the XOR operator)

## and can be described in a truth table:

T flip-flop operation Characteristic table Comment 0 0 0 1 1 0 1 1 0 1 1 0 hold state (no clk) 0 hold state (no clk) 1 toggle toggle 0 1 0 1 1 0 0 0 Excitation table Comment No change No change

1 Complement 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate). A T flip-flop can also be built using an edge-triggered D flip-flop with its D input fed from its own inverted output.

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 JK flip-flop

## JK flip-flop circuit diagram

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flipflop, or a T flip-flop. The characteristic equation of the JK flip-flop is:

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## JK Flip Flop operation Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment 0 0 Q hold state 0 01 10 0 1 reset set toggle 0 1 1 0 0 X No change 1 1X 0 X1 Set Reset

11 Q

1 X 0 No change

 Metastability
Flip-flops are prone to a problem called metastability, which can happen when two inputs, such as data and clock or clock and reset, are changing at about the same time, such that the resulting state would depend on the order of the input events. When the order is not clear, within appropriate timing constraints, the result is that the output may behave unpredictably, taking many times longer than normal to settle to one state or the other, or even oscillating several times before settling. Theoretically, the time to settle down is not bounded. In a computer system, this metastability can cause corruption of data or a program crash, if the state is not stable before another circuit uses its value; in particular, if two different logical paths use the output of a flipflop, one path can interpret it as a 0 and the other as a 1 when it has not resolved to stable state, putting the machine into an inconsistent state.

##  Timing considerations

 Setup and hold times

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## Flip-flop setup, hold and clock-to-output timing parameters

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop. Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flipflop. To summarize: Setup time -> Clock flank -> Hold time. The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices. Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased. So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.
 Propagation delay

Another important timing value for a flip-flop (F/F) is the clock-to-output delay (common symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH). When cascading F/Fs which share the same clock (as in a shift register), it is important to ensure that the tCO of a preceding F/F is longer than the hold time (th) of the following flip-flop, so data present at the input of the succeeding F/F is properly "shifted in" following the active edge of the
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clock. This relationship between tCO and th is normally guaranteed if the F/Fs are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum tsu + th.

 Generalizations
Flip-flops can be generalized in at least two ways: by making them 1-of-N instead of 1-of-2, and by adapting them to logic with more than two states. In the special cases of 1-of-3 encoding, or multi-valued ternary logic, these elements may be referred to as flip-flap-flops. In a conventional flip-flop, exactly one of the two complementary outputs is high. This can be generalized to a memory element with N outputs, exactly one of which is high (alternatively, where exactly one of N is low). The output is therefore always a one-hot (respectively one-cold) representation. The construction is similar to a conventional cross-coupled flip-flop; each output, when high, inhibits all the other outputs. Alternatively, more or less conventional flip-flops can be used, one per output, with additional circuitry to make sure only one at a time can be true. Another generalization of the conventional flip-flop is a memory element for multi-valued logic. In this case the memory element retains exactly one of the logic states until the control inputs induce a change. In addition, a multiple-valued clock can also be used, leading to new possible clock transitions.

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## Multivibrator Positive feedback Deadlock Pulse transition detector

 References
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3. ^ William Henry Eccles and Frank Wilfred Jordan, "Improvements in ionic relays" British patent number: GB 148582 (filed: 21 June 1918; published: 5 August 1920). 4. ^ W. H. Eccles and F. W. Jordan (19 September 1919) "A trigger relay utilizing three-electrode thermionic vacuum tubes," The Electrician, vol. 83, page 298. Reprinted in: Radio Review, vol. 1, no. 3, pages 143146 (December 1919). 5. ^ Emerson W. Pugh, Lyle R. Johnson, John H. Palmer (1991). IBM's 360 and early 370 systems. MIT Press. p. 10. ISBN 9780262161237. 6. ^ Earl D. Gates (2000). Introduction to electronics (4th ed.). Delmar Thomson (Cengage) Learning. p. 299. ISBN 9780766816985. 7. ^ Max Fogiel and You-Liang Gu (1998). The Electronics problem solver, Volume 1 (revised ed.). Research & Education Assoc.. p. 1223. ISBN 9780878915439. 8. ^ Wilfred Bennett Lewis (1942). Electrical counting: with special reference to counting alpha and beta particles. CUP Archive. p. 68. 9. ^ The Electrician 128. Feb. 13, 1942. 10. ^ Owen Standige Puckle and E. B. Moullin (1943). Time bases (scanning generators): their design and development, with notes on the cathode ray tube. Chapman & Hall Ltd. p. 51. 11. ^ Britton Chance (1949). Waveforms (Vol. 19 of MIT Radiation Lab Series ed.). McGraw-Hill Book Co. p. 167. 12. ^ O. S. Puckle (Jan. 1949). "Development of Time Bases: The Principles of Known Circuits". Wireless Engineer (Iliffe Electrical Publications) 26 (1): 139. 13. ^ P. L. Lindley, Aug. 1968, EDN (magazine), (letter dated June 13, 1968). 14. ^ Montgomery Phister (1958). Logical Design of Digital Computers.. Wiley. p. 128. 15. ^ Eldred C. Nelson (Sept. 2, 1958 (filed Sept. 8, 1953)). "High-Speed Printing System". US Patent 2850566. "Each flip-flop or bistable multivibrator includes two input terminals, hereinafter termed the j-input and the k-input terminals, respectively, and two output terminals for producing complementary bivalued electrical output signals hereinafter termed Q and Qbar, respectively. Signals applied separately to the j-input and k-input terminals set the flip-flop to conduction states corresponding to the binary values one and zero, respectively, while signals applied simultaneously to both input terminals trigger or change the conduction state of the flip-flop." 16. ^ Sajjan G. Shiva (2000). Computer design and architecture (3rd ed.). CRC Press. p. 81. ISBN 9780824703684. 17. ^ Langholz, Gideon; Kandel, Abraham; Mott, Joe L. (1998). Foundations of Digital Logic Design. Singapore: World Scientific Publishing Co. Ptc. Ltd.. p. 344. ISBN 978-981-02-3110-1 18. ^ Hassan A. Farhat (2004). Digital design and computer organization, Volume 1. CRC Press. p. 274. ISBN 9780849311918. 19. ^ a b Kogge, Peter M. (1981). The Architecture of Pipelined Computers. McGraw-Hill. pp. 2527. ISBN 0-07-035237-2 20. ^ Cotten, L. W. (1965). "Circuit Implementation of High-Speed Pipeline Systems". AFIPS Proc. Fall Joint Computer Conference: 489504 21. ^ Earle, J. (March, 1965). "Latched Carry-Save Adder". IBM Technical Disclosure Bulletin 7 (10): 909910 22. ^ a b Omondi, Amos R. (1999). The Microarchitecture of Pipelined and Superscalar Computers. pp. 4042. ISBN 978-0792384632 23. ^ a b Kunkel, Steven R.; Smith, James E. (May 1986). "Optimal Pipelining in Supercomputers". ACM SIGARCH Computer Architecture News (ACM) 14 (2): 404411. doi:10.1145/17356.17403. ISSN 0163-5964 24. ^ The D Flip-Flop 32

25. ^ Edge-Triggered Flip-flops 26. ^ SN7474 TI datasheet 27. ^ a b Mano, M. Morris; Kime, Charles R. (2004). Logic and Computer Design Fundamentals, 3rd Edition. Upper Saddle River, NJ, USA: Pearson Education International. pp. pg283. ISBN 0-131911651. 28. ^ Thomas J. Chaney and Charles E. Molnar (April 1973). "Anomalous Behavior of Synchronizer and Arbiter Circuits". IEEE Transactions on Computers C-22 (4): 421422. doi:10.1109/TC.1973.223730. ISSN 0018-9340. 29. ^ Often attributed to Don Knuth (1969) (see Midhat J. Gazal (2000). Number: from Ahmes to Cantor. Princeton University Press. p. 57. ISBN 9780691005157.), the term flip-flap-flop actually appeared much earlier in the computing literature, for example, Edward K. Bowdon (1960). The design and application of a "flip-flap-flop" using tunnel diodes (Master's thesis). University of North Dakota., and in Alexander, W. (Feb. 1964). "The ternary computer". Electronics and Power (IET) 10 (2): 3639. 30. ^ "Ternary "flip-flap-flop"". 31. ^ US 6975152 32. ^ Irving, Thurman A. and Shiva, Sajjan G. and Nagle, H. Troy (March 1976). "Flip-Flops for Multiple-Valued Logic". Computers, IEEE Transactions on C-25 (3): 237246. doi:10.1109/TC.1976.5009250. 33. ^ Wu Haomin and Zhuang Nan (1991). "Research into ternary edge-triggered JKL flip-flop". Journal of Electronics (China) 8 (Volume 8, Number 3 / July, 1991): 268275. doi:10.1007/BF02778378. View page ratings Rate this page What's this? Trustworthy Objective Complete Well-written I am highly knowledgeable about this topic (optional) Categories:

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