Input-Output Organization

Mein Memory

CPU

Address lines Data lines Control lines

Keyboard interface

Printer Controller

Disk Interface

Monitor controller

Keyboard

Printer

Magnetic Disk

Monitor

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Figure: Connection of I/O bus to I/O controller

Program Application program Result Operating system

Call BIOS Return

Command I/O controller Status I/O device

Figure: communication between I/O controller and application program

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Address

CPU

Data Memory R/W I/O R/W

Space

Memory address I/O address Space

(a)CPU signals Figure: I/O mapped I/O

Address

(b) address spaces

I/O addresses

CPU

Data Memory R/W

Memory addresses

(a)CPU signals

(b) address space division Figure: Memory mapped I/O

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One clock period

Clock

Address of slave by master

Read signal by master

Data is placed in data bus by slave

Figure: timing diagram for synchronous read operation

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Data bus

Source unit
Strobe

Destination unit

(a) Block diagram

Data bus Strobe

Valid data

(b) timing diagram Figure: source initiated strobe for data transfer
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Data bus Source

Strobe

Destination unit

(a) Block diagram

Strobe Data bus

Valid data

(b) timing diagram Figure: destination initiated strobe for data transfer
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Source

Data bus Data valid Data accepted

Destination unit

(a) Block diagram

Data bus

Valid data

Data valid

Data accepted

(b) Timing diagram Figure: Source initiated transfer using handshaking

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Source

Data request Data bus Data valid

Destination unit

(a) Block diagram

Data request is raised Data accept is acknowledged

Data request Data Valid data

Data valid

(b) Timing diagram

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Figure: destination initiated handshaking technique

Data bus Address bus

Interface Data transfer

I/O devices

CPU
I/O R/W

Execute Stored instruction

Status Register

Memory

F=flag bit

Figure: Data transfer form I/O device to memory through CPU

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Main memory Current program (consists of mainly arithmetic and logic instruction)

Interrupt location

This portion is executed without any interrupt

On completion of ISR, CPU returns to original program and resumes execution of the th program starting from (i+1) instruction
ISR

CPU branches to ISR on receiving th interrupt during i instruction th execution. Before branch, i instruction is executed.

Figure: interrupt process

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CPU

CPU branches to a respective devices ISR after enabling INTA

IE
Using IE flip-flop, CPU detects interrupt

INTA INTR
Interrupt from interrupt controller when data transfer is needed

Interrupt controller

IMR

Device 1

Device 2

Figure: hardware interrupt

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CPU

Address bus Data bus R/W high impedance when HLDA is enabled

Hold HLDA

Figure: CPU bus signals for DMA transfer

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Address Data HOLD HLDA R/W INT

Decoder DMA CONTROLLER

Address Data HOLD HLDA R/W INT Address Data Address Data HOLD HLDA CS R/W RS INT

CS R/W

CPU

RAM

DMA request

DMA acknowledge

I/O device

Figure: typical DMA system

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CPU

Memory

System bus
DMA Controller 1 DMA Controller 2

Floppy disk controller

Hard disk controller

Floppy disk drives

Hard disk drives

Figure: independent DMA controller

CPU

Memory

System bus
DMA Controller 1 DMA controller DMA Controller 2

Floppy disk controller

Hard disk controller

Floppy disk drives

Hard disk drives

Figure: DMA controller with multiple DMA channel