Progress in Silicon Carbide Power Devices

Anant Agarwal, Mrinal Das, Brett Hull, Sumi Krishnaswami, John Palmour, James Richmond, Sei-Hyung Ryu, Jon Zhang
Cree Inc., 4600 Silicon Dr., Durham, NC 27703, USA Anant_Agarwal@cree.com, (919) 313-5539
ABSTRACT SiC materials and device technology has entered a new era with the commercialization and acceptance of 600 V/10 A and 1200 V/10 A Schottky Barrier Diodes (SBDs) in the marketplace. These diodes are finding applications in the Power Factor Correction (PFC) stage of Switch Mode Power Supplies (SMPS). SiC power MOSFETs with ratings of 800-1200 V up to 10 A will soon be commercially available. The next step is to integrate the SiC MOSFET and Schottky diodes in a power module for PFC and motor control applications. For high temperature applications, greater than 2000C, a bipolar switch such as a SiC BJT offers superior performance over the MOSFETs. The lack of gate oxide in the BJT offers better reliability at such extreme temperatures, in addition to the lowest combined switching and conduction losses. INTRODUCTION SiC offers an opportunity to replace Si PiN diodes and IGBTs with SiC Schottky diodes and MOSFETs, respectively, up to about 3000 V. The combination of SiC Schottky diode and MOSFET will save approximately 60-80% of switching losses resulting in an efficiency improvement of 4-6% points in a typical power electronic system. In addition, cooling requirements will be substantially reduced in direct proportion to the reduction in losses. SiC MOSFET can operate reliably up to junction temperatures of 2000C. However, for operation above 2000C, SiC BJTs are an excellent choice.
1200 V SiC MOSFETs The 4H-SiC DMOSFET structure is shown in Fig. 1. The MOS channel length is defined by the p-well and n+ implants, and can range from 0.5 ptm to 1.5 ptm. Electrons flow laterally from the n+ source through an inversion layer across the implanted p-well, then flow vertically through the JFET region formed by two adjacent p-well regions, and then through the lightly doped n- drift region into the drain. The blocking voltage of the MOSFET is determined by the doping concentration and thickness of the n- epilayer. For 1200 V devices, an epilayer with a doping concentration of 6x1015 cm-3 and a thickness of 12 ptm can be used. A thermally grown oxide layer is typically used as gate dielectric due to its repeatability and stability. Typically, the gate oxide is nitrided in NO or N2O to reduce MOS interface state density, which improves the transconductance of the MOSFET. source gate source Figure 2 shows the on-state I-V characteristics of a 1.8 kV s. p+ N+ 4H-SiC DMOSFET. The device has a 500 A thick gate oxide. P+ N+ JP-wel The gate oxide electric field was limited to approximately 3 MV/cm (Vgs = 15 V). The active area of this device is 0.0936 cm2. An on-resistance of 85 mQ (Ron,sp = 8 mQ-cm2), and a drain n- epilayer current of 50 A (534 A/cm2) at a forward drop of 5.7 V were measured at room temperature. At an operating temperature of N+4H-SiC substrate 1500C, the on-resistance increases to 100 mQ (9.4 mQ-cm2). A slight negative shift in MOS threshold voltage at elevated drain temperatures decreases the MOS channel resistance at a fixed gate bias. This cancels out, to some extent, the increase in drift Fig. 1. Simplified cross-section of the SiC layer resistance, resulting in temperature stable on-resistance. DMOSFET. Figure 3 shows the blocking characteristics of the 4H-SiC DMOSFET. The device is normally off, and showed stable avalanche characteristics at a VDS of 1.8 kV with a VGS of 0 V. The biggest challenge in the commercialization of 4H-SiC MOSFET is control of the threshold voltage due to the presence of high positive charge in the oxide (QF 2E12 cm 2). The room temperature
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threshold voltage is approximately 3.5 V, which decreases to 2.2 V at 1500C. However, for power switches, the drain current should be less than 1 [tA in off-state. At this drain current, the gate bias needed to keep the device at off-state is very close to zero, about 1.55 V at room temperature and 1.05 V at 1500C (Fig. 4). Any small glitch in the gate drive can turn the device on, resulting in a 'normally-on' device. Therefore, a more positive low current Vth is desired for stable operation and to ensure a 'normally off' device.
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Inversion layer mobility of the SiC MOSFET is yet another area where considerable improvement is needed. Significant effort has been focused on improving the channel mobility ([tch) in lateral MOSFETs. Some of the important factors known to reduce the channel mobility are: (a) high interface trap charge, Dit, (b) high fixed oxide charge, QF, and (c) poor surface morphology in the channel of the device due to ion implantation and high temperature activation. High value of Dit near the conduction band has been steadily improved by introducing nitrogen, either from NO or N20, at the SiC-SiO2 interface. Nitric oxide (NO) anneals at 1 1 750C have lowered Dit to 1-5E1 1 eV 1cm2 and increased the ptch from single digits to -30 cm2N-s in lateral MOSFETs [1]. However, in the vertical devices, the channel mobility is still somewhat low, less than 20 due to the high doping of the 60 implanted p-wells. Several groups have demonstrated even higher tch ( -150 ReOx NO cm 2 N-s) in lateral MOSFETs by oxidizing in an environment 5 _ containing metallic impurities [2-4]. However, non-idealities in N_ 40 iE_* the oxidation process resulted in enhanced oxide thickness (> Al 1500 A), and incompatibility with high temperature processing 2 like ohmic contact anneals. Recently, Das et. al demonstrated 2 an optimized Metal Enhanced Oxidation (MEO) process which _ produced acceptable gate oxide thickness (- 600 to 900 A). iL 10 While, QF and Dit values for the MEO gate oxide was comparable to that of the conventional NO annealed oxide, 0 4 8 12 16 20 A4 the inversion layer mobility of the MEO MOSFET with GateVoltage (V) Fig. 5. Channel mobility versus gate voltage for implanted p-wells increased to 48 cm2IV-s at Vgs of 20 V, a * g ~~~~~~~~~~~~MEO nd MOSFETs Al and NOchannel. formed on 1 x 1018 cm3 40% increase from the NO process [4]. This would translate in mplanted channel. to a mobility of 30-35 in the vertical DMOSFET, which is sufficient for production. A comparison of channel mobility as a function of gate voltage for three different oxidation processes is shown in Fig. 5 for a lateral MOSFET with Al implanted channel. While the NO process is immediately available for the MOSFET fabrication, the MEO requires further optimization to remove unwanted metal species from the gate oxide. Successful isolation of the relevant MEO specie(s) will enable the next generation of high performance SiC MOS devices. Further improvement in mobility is possible by reducing the surface roughness occurring during implantation and high temperature anneals. Capped activation anneals with graphitized resist has proven to be beneficial in reducing the surface roughness. Incorporation of capped anneal process in the fabrication will also help in a more reliable and robust MOSFET device.
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SiC BIPOLAR JUNCTION TRANSISTORS 5 tm5 tm IO -tm The cross-section of an NPN BJT is shown in Fig. 6. The 1.5~tm emitter, base and collector layers are all epitaxially grown in E 3 one continuous growth run. The blocking layer for the 1200 V B J ~tm,2x1O 17 cmN' B cm3 The BJT is 15 pim thick and doped at 4.8 x 1015 15. 3 BJT chip ~~~1 P consists of alternating base and emitter fingers to form an inter-digitated structure. A double metal process was used. The active area of the device is 0.16 cm2. N, 15 tm, 4.8x1015 cm-3 Fig. 7 shows the forward I-V characteristics of the BJT in P+GRs P+GRs the common emitter mode at room temperature. The device conducts 20 A at a forward voltage of 0.57 V and at IB of 600 N+, 4HSiC mA. The measured specific on-resistance is 4.6 mQ-cm2 The c current gain of the device is 45. Forward blocking Fig. 6. Cross-section of 1200 V SiC BJT. characteristics in the common emitter mode is shown in Fig. 8. The device shows avalanche behavior and blocks 1350 V at a leakage current of 50 pIA. One of the major challenges today in the commercialization of SiC BJTs is the phenomenon of current gain instability. Recently, current gain degradation was observed in 4H-SiC BJTs [5]. The degradation causes the current gain to decrease and the on-resistance to increase with time. This degradation behavior in a 1200 V SiC BJT is shown in Figs. 9(a) and 9(b).
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Collector Voltage (volts)

Fig. 8. Blocking capability of the 0.16 cm2 4H-SiC BJT.

Collector voltage (volts)

The output characteristics of the BJT device in common emitter mode before any stress is shown in Fig. 9(a). The transistor conducts 10 A of collector current at VCE = 1.4 V and IB = 500 mA. After the initial measurement, the device was stressed at 10 A for a given amount of time. The device was powered down, allowed to cool and then the output characteristics were recorded each time. One can observe that the current gain has decreased from 30 to 15, by almost 50%, after about 16 hrs of stress (Fig. 9(b)). In addition, the on-resistance of the device in the saturation region has also increased. The origin of this current gain instability in SiC BJTs is still not very clear. One speculation is that the degradation could be due to the generation and growth of stacking faults in the base of the transistor (Fig. 10). This is similar to what is observed in the drift layer of a SiC PiN diode causing the forward voltage drop to drift. In the PiN diodes, the energy for this expansion of the stacking fault comes from the electron-hole recombination in the conductivity modulated drift layer. This results in reduction of the minority carrier lifetime, reducing the conductivity modulation in the immediate vicinity of the stacking fault, leading to an increase in Vf. Concurrently, in the BJTs, the base of the transistor gets flooded with electron-hole pairs during the operation of the device. The recombination of electron-hole pairs in the base can give rise to stacking faults, which can then reduce the lifetime of the minority carriers locally in the base, resulting in the reduced current gain. The reduction in current gain can also explain the increase in the on-resistance of the BJT in the saturation region since not many carriers make it across the base into the collector. Another possible mechanism for the current gain degradation could be similar to what has been observed in AlGaAs/GaAs Heterojunction Bipolar Transistors (HBTs) [6,7]. In these devices, when the geometry was scaled down to improve the device performance, the current gain was found to drift with time. The drift in the current gain was strongly influenced by the surface recombination effect due to the

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high surface recombination velocity in GaAs. In order to suppress the surface recombination effect, and therefore the instability in the current gain, several device design and process controls were proposed. Among them the introduction of a thin depleted layer with wide-gap and lower surface recombination velocity, such as an AlGaAs passivating 'ledge', on to the extrinsic base was proven to be effective in reducing this behavior [7]. A similar effect may be responsible for current gain degradation in SiC BJTs. Whether it is the generation of stacking faults in the base or surface recombination current in the baseemitter region, the exact origin to the mechanism of current gain instability in SiC BJTs has to be first understood before these devices can be commercialized.
ACKNOWLEDGEMENT This research was funded through the Cooperative Agreement W911INF-04-2-0022 funded by the Army Research Laboratory in Adelphi, Md and by TIA # FA8650-04-2-2410, funded by the Air Force Research Laboratory, in Dayton, Ohio.

REFERENCES
[1] M.K. Das, Recent Advances in (0001) 4H-SiC MOS Device Technology, Materials Science Forum, Vol. 457-460 (2003), pp. 1275-1280. [2] H.O. Olafsson, Ph.D. Dissertation, Chalmers University (2004). [3] D. Alok, et al., US Patent and Trademark Office 6,559,068 (2003). [4] M. Das et. al, Improved 4H-SiC MOS Interfaces Produced via Two Independent Processes: Metal Enhanced Oxidation and 13000C NO Anneal, presented at IOSORM 2005. [5] A. Agarwal et. al, Influence of Basal Plane Dislocation Induced Stacking Faults on the Current Gain in SiC BJTs, presented at IOSORM, Pittsburgh, USA, Sept. 2005. [6] P. Ma et. al, InGaP/GaAs HBT Failure Mechanism Investigation and Reliability Enhancement, Report for MICRO Project 98-018, [7] J-M. Lee et. al, Fabrication and Temperature-dependent characteristics of AIGaAs/GaAs Heterojunction Bipolar Transistors with an AlGaA s-Ledge Structure, J. Korean Physical Society, 40, pp. 320-324, 2002.
1999.

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