Delay Testing of MOS Transistor with Gate Oxide Short

M. Renovell, J.M. Gallire, F. Azas and Y. Bertrand

Laboratoire d'Informatique Robotique Microlectronique de Montpellier LIRMM-UMII Universit de Montpellier II: Sciences et Techniques du Languedoc UMR C5506 CNRS - 161, rue Ada 34392 Montpellier Cedex 5 France Tl: (34)467418523 Fx:(34)467418500 Em:renovell@lirmm.fr

Abstract
Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location.

1. Introduction

process, it is impossible to guarantee that every manufactured parts works perfectly because different types of defects may affect the technological process. The typical defects encountered in today technologies and modeled in yield simulators are the so-called spot defects that may cause shorts and/or breaks in circuit connectivity as well as in transistor structure. These defects are usually responsible for catastrophic or failures of VLSI circuits. Due to the presence of these defects every manufactured chip is tested before to be shipped to the customer. Test generation for any type of defect is obviously not feasible due to the huge amount of CPU time and memory size required. Instead, test generation relies on fault models that are supposed to both represent the defect behavior and allow easy generation of test vectors. Under such conditions, it is absolutely obvious that the test generation cost depends on the tractability of the fault models and the overall test quality depends on the ability of this fault model to accurately represent the defect behavior.
Proceedings of the 12th Asian Test Symposium (ATS03) 1081-7735/03 $17.00 2003 IEEE

Due to the complexity of IC technological

The increasing demand of low ppm defect rates require the derivation of ever more accurate fault model. Accurate fault model can be defined only through a detailed knowledge and understanding of defect behavior. Consequently special attention must be paid to the study of defect with a high probability of occurrence and to defect that exhibit complex behavior not accurately represented by classical fault models. Gate Oxide Shorts defects belong to both categories : (i) the behavior of the defect is very complex because of the modification of the transistor characteristics and due to the important number of parameters involved in this behavior, (ii) they are predominant defects and they will continue to be prevalent as devices are scaled down and oxide thickness are significantly reduced. In the past few years Gate Oxide Shorts have been study by different authors [1-13]. Through a detailed consideration of these very interesting works we observe that several points are crucial when analyzing GOS : - complexity of the model - list of random parameters In the previous works the defective transistor is classically modeled by an array of lumped-elements MOS transistors with a common gate. The array may be complex i.e. bi-dimensional or only composed of 2 or 3 transistors. Obviously, the bi-dimensional array gives more accurate and realistic results but at the expense of the CPU time. The pinhole defect is classically represented by a resistor Rgos between the common gate and a specific node. A large spectrum of parameters may be considered or not for the pinhole such as defect resistance value, defect location and defect size. From this bibliographical study we observed that: The bi-dimensional model is often considered as a very accurate model for electrical simulations, The defect random parameters have to be considered for any detailed study of this defect,

Different works covers different areas or test strategies but there is no paper covering the delay testability of this defect.

Consequently, the objective of this paper is to give a detailed and complete analysis of the dynamic voltage (Delay) behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used as described in section 2. It is important to note at this point that dealing with defect analysis at the transistor or gate level but not at the circuit level, the CPU time remains very reasonable even when we use a complex model such as the bi-dimensional one. The dynamic voltage behavior and consequently the Delay detectability of the defect is studied in section 3 taking into account the defect resistance, location and size. Finally, a global discussion is proposed in section 4 together with some concluding remarks.

number of elements the most accurate are the obtained results. In our study we used a 5x5 array and so we have 50 elementary transistors and 25 nodes numbered from (1,1) to (5,5). A 0.25m technological process is considered, and so the elementary NMOS transistor has a length of Li=0.25m and a width of Wi=0.5m, implying that the overall network is equivalent in this technology to a single transistor of L=2.1m and W=3.5m.
col. 1 G G line m G G line i G G G G G G G G G G G G G G col. j G G col. n G G

S
G G

(i,j) G G G G

D
G G

line 1 (1,1)

Figure 2: A 5x5 bi-dimensional model Figure 3 gives the simulated ID vs VDS characteristics of the 5x5 network and the simulated characteristics of the equivalent single transistor. We can observe a good agreement between the network and its equivalent single transistor.
0,0004

2. The bi-dimensional model

relatively low impedance path between the CMOS gate and the underlying silicon. For this failure, an undesired path of current through the oxide of the gate appears thus creating a violation of the gate isolation principle. It is generally admitted that GOS may have different origins such as lithographic defect on mask, field failure due to ESD Figure 1 gives an example of pinhole defect within a MOS transistor channel.
Gate poly

A GOS is a transistor defect that cause a

ID

0,0003

0,0002

0,0001

Source N+ P

Drain N+

0,4

0,8

1,2

1,6

2,4

VDS

Figure 3: Simulated ID vs VDS Characteristics of the fault free device: 5x5 network and original In the bi-dimensional network, the pinhole is modeled by a resistor Rgos between the common gate G and one of the internal node denoted (if,jf) as illustrated in figure 4.
G
RGOS

Figure 1: Pinhole in a MOS gate In order to study this defect through electrical HSPICE simulation, an electrical model of the fault free transistor based on lumped-element has been proposed in the past [4-5]. In this model represented in figure 2, the non-defective channel is represented by a bi-dimensional array of MOS transistors with : m lines and n columns, n+1 transistors and n nodes per line, m-1 transistors and m nodes per column m(n+1)+n(m-1) transistors, mn nodes denoted (i,j) with i{1,m}and j{1,n}

(if,jf)

S
(1,1)

One can arbitrarily choose the number and size of the elements but it is clear that the higher the
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Figure 4: Faulty network

The HSPICE simulation of the faulty network allow to obtain the ID vs VDS characteristics of the faulty equivalent transistor as illustrated in figure 5 for Rgos=1k and (if,jf)=(3,3). As commented by the authors of many previous papers, the drain current in the defective transistor only slightly resembles the typical fault-free characteristics of figure 3. The first specificity is the fact that the maximum current denoted IDmax in figure 5.a is much smaller than the maximum current in the defect free device. The second and main specificity is the fact that the drain current may be negative when VDS is small in comparison with VGS. In some cases an important negative current denoted IDmin in figure 5.a can flow through the defective transistor. The pinhole that shorts circuit the transistor gate with some point of its channel creates a new device in which an important gate current can flow. It is consequently possible to draw the IG vs VGS characteristics of the defective transistor as shown in Figure 5.b. Note that the value of this gate current IGmax can be relatively high.
0,0002 0,0001

measurements have clearly dimensional model [14-16].

validated

the

bi-

Due to these multiple agreements, we consider the bi-dimensional model as a very realistic model that allows to analyze accurately the behavior of the GOS. Due to the validity of the bi-dimensional model, it will be use in this paper to analyze in detail the dynamic behavior of the GOS as a function of its different parameters.

3.Delay behavior of an inverter with a GOS

IDmax
0 0,4 0,8 1,2 1,6 2 2,4

have any resistance and can be of any location. The objective of this section is to study the dynamic voltage behavior of a faulty inverter as a function of the GOS resistance and location. In order to simulate a realistic situation, we classically consider a cascade of 4 inverters with the GOS on the n-channel transistor of the third inverter as illustrated in figure 6. The extension to a p-channel transistor is straightforward. The validity of the used model is discussed in section 3.1.

It is clear that the pinhole in the oxide can

ID

-0,0001 -0,0002 -0,0003 -0,0004 -0,0005

VDS IDmin

T0

T1

T2

T3

T4

1
#1

1
#2

1
#3

1
#4

D1

D2

D3

CL

D4

a) ID vs VDS
0,0009 0,0008 0,0007 0,0006 0,0005 0,0004 0,0003 0,0002 0,0001 0 0 0,4 0,8 1,2 1,6 2 2,4

D23 Figure 6: The simulated cascade of inverters

When delay testing is considered, a defect may affect the delay Di of a given inverter #i but also the slope of the signal, i.e. the rising or falling time Ti. For this reason, we characterize here the effect by drawing the Di and Ti characteristics versus the random resistance and position parameters of the defect. Note that the GOS in inverter #3 creates a short affecting the input of inverter 3, i.e. the output of inverter #2. For this reason, delays D2 and D3 can not be dissociated. So, inverter #2 and #3 are considered as a block. Consequently, T2 is not considered and we draw the global delay called D23. Note also that delays D1 and D4 are not affected by the defect, making only D23 relevant in this study. In the same way, it is clear that T0 and T1 are not affected by the defect. It is interesting to note that only T3 and T4 are affected but for different reasons. The modification of T3 is directly due to the effect of the defect in inverter #3 while the modification of T4 is an indirect effect due to the modification of T3 on the input of the fault free inverter #4, i.e. the modification of the input signal itself.

IGmax IG VDS=0V

VGS

b) IG vs VGS Figure 5: Simulated characteristics of the faulty network This bi-dimensional model has been validated and evaluated by the authors in several previous papers using different experiments. Indeed, experimental circuits have been designed and manufactured including fault-free transistors as well as intentionally shorted transistors. Note that some shorts have also been created electrically on the fault-free designed transistors allowing a very realistic characterization. This set of experiments and the corresponding

Proceedings of the 12th Asian Test Symposium (ATS03) 1081-7735/03 $17.00 2003 IEEE

For this reason we analyze the D23 and T3 versus resistance and location characteristics in section 3.2. Then we analyze separately, the T4 versus T3 characteristics in section 3.3.

1,2 1 0,8 0,6

Tout ns

3.1. Validity of the model

We use 0.25 technology with VDD=2.5V, minimum transistors in an inverter can be around wp=3m wn=1m Lp,n=0.3m. Slopes (Ti) are determined between 1V and 1.5V (20% of 2.5). Figure 7 gives the typical Ti and Di of a minimum inverter with CL=8.3fF.
0,05 0,04 0,03 0,02 0,01

0,4 0,2

Tin
0 0,6 1,2 1,8 2,4 3 3,6 4,2 4,8 5,4

ns
6

4 3,5 3 2,5 2

D ns

Tout ns

1,5 1 0,5 0 1 2 3 4 5 6

Tin ns
7 8

Figure 8: Characteristics of a the used inverter

Tin ns
0,3 0,04 0,08 0,12 0,16 0,2 0,24 0,28

0,18 0,14

D ns

We observe in figure 7 and 8 exactly the same behavior but, obviously, for different values of slope and delay. This clearly proves that a larger than minimum inverter can be used to characterize the delay detection of GOS if simulation results are interpreted in a relative way. Consequently, in the following additional delays due to the defect will be expressed in percentage of the nominal delay.

0,1 0,06 0,02 0 0,08 0,16 0,24 0,3

Tin ns
0,4

3.2. D23 and T3 vs parameters Characteristics

We simulate now the cascade of inverters and we draw the T3 and D23 versus resistance and location characteristics.
D23
2 1,5 1 0,5

Figure 7: Characteristics of a minimum inverter In order to simulate a faulty inverter, we use for the faulty transistor the bi-dimensionnal model presented in the previous section because this model has been proved very realistic and accurate. However, this model suffers from a limitation when delay testing is considered. In the bi-dimensionnal model, the simulated network and the original modeled transistor are electrically equivalent; the network is here just to allow injection of the defect. Obviously, transistors in the network are smaller than the original modeled transistor. And so, for a minimal transistor it is not possible to define this equivalent network. Indeed the transistors in the network should be smaller than the minimum allowed by the technology. Consequently, the inverters simulated here are made of transistors larger than the minimum. In our simulated inverters, transistor sizes are wp=11m wn=3.5m Lp,n=2.1m. Figure 8 gives Ti and Di of our inverter with CL=0.21pF.
Proceedings of the 12th Asian Test Symposium (ATS03) 1081-7735/03 $17.00 2003 IEEE

S To=0.2ns

D
0 0 4 8 12 16

Rgos (kohm)

20

24

28

a)

fast input

D23

S To=6ns

1,5 1 0,5 0 0

D
4 8 12

Rgos (kohm)

16

20

24

28

strategy. Indeed, we observe that the relative increase of the delay can be up to 2 and the relative increase of the slope can be up to 9. In absolute, this means that the original delay can be multiplied by 3 and the original slope multiplied by 10. This increase in delay is quite important if we remind that the original delay D23 corresponds to the sum of 2 delays, the daly of gate #2 and gate #3. This is a very important result of this study. Note that the impact of the defect increases for a low resistance and for a defect close to the source. Note also that the relative increase both for D23 and T3 does not depend on the speed of the input signal.

b) Slow input Figure 9: Relative increase of the delay

T3
8 6
1,2

3.3. Tout vs Tin Characteristics

As previously commented T4 is modified due to the modification of T3. In order to characterize this effect. Figure 11 gives the Tout versus Tin of a fault-free inverter. This effect can be view as the penetration of the slope modification into the succeeding logic.
Tout
1 0,8

S To=0.2ns

4 2 0

ns

Falling Edge Rising Edge

D
4 8 12 16 20

0,6 0,4

28

Rgos (kohm)

24

0,2 0 0 1 2 3 4

a)
T3
8 6 4 2 0

Fast input

Tin
5

ns
6

S To=6ns

Figure 11: Tout vs Tin Characteristics In figure 10.a, for example, we observe that a fast slope of 0.2ns can have a relative increase of 9, resulting in an absolute slope of 2ns, i.e. multiplied by up to 10. In figure 11, we deduce now that an input slope of 2ns will produce an output slope of 0.6ns which is still higher than the standard slope of 0.2ns. This implies 2 comments: - this additional delay makes the defect even more detectable using delay testing, - the effect penetration is small due to high gain of the gates. After the first driven gate (inverter #4), the slope become nominal.

D
4 8 12 16 20

Rgos (kohm)

24

b) Slow input Figure 10: Relative increase of the slope Figure 9 gives the relative increase of the delay given by D23 = (D23*-D23)/D23 and Figure 10 the relative increase of the slope T3 = (T3*-T3)/T3. The x axis represents the defect resistance and the y axis the location in percentage of the distance from source to drain. It is clear here that the defect has a strong effect on the delay and can be detected by a delay test
Proceedings of the 12th Asian Test Symposium (ATS03) 1081-7735/03 $17.00 2003 IEEE

28

4. Discussion and Conclusion

rom the previous study we can make the following remarks concerning the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective was to give a detailed, complete and realistic analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and location.

We have demonstrated that a GOS can be easily detected using a delay test technique. Remember that this defect is extremely difficult to detect using a Boolean test technique. The defect heavily modifies the potential distribution inside the channel of the faulty transistor and we note that a low resistance or a short close to the transistor source makes the defect easier to detect.

[15] M. Renovell, J.M. Gallire, F. Azas, Y. Bertrand,

"Analysing the Characteristics of MOS Transistors in the Presence of Gate Oxide Short", Design & Diag. of Electr. Circuits and Syst., pp. 155-161, 2001 [16] M. Renovell, J.M. Gallire, F. Azas, Y. Bertrand, "Boolean and Current Detection of MOS Transistor with Gate Oxide Short", Int. Test Conf., pp. 1039-1048, 2001

5. References
[1] C. F. Hawkins and J. M. Soden, "Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs" Int. Test Conference, pp 544-555 1985 [2] C J. M. Soden and F. Hawkins, "Test considerations for Gate Oxide Shorts in CMOS ICs" IEEE Design and Test of computers, pp 56-64 1986 [3] C. F. Hawkins and J. M. Soden, "Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs" Int. Test Conference, pp 443-451 1986 [4] M. Syrzycki, "Modeling of Spot Defects in MOS Transistors" Int. Test Conference, pp 148-157 1987 [5] M. Syrzycki, "Modeling of Gate Oxide Shorts in Mos Transistors" Tr. On Computer-Aided Design vol. 8, pp. 193202, March 1989 [6] S. I. Syed and D.M. Wu, "Defect Analysis, Test Generation and Fault Simulation for Gate Oxide Shorts in CMOS ICs" Int. Symp. Circuits and Syst., pp2705-2707, 1990 [7] J. Segura, A. Rubio and J. Figueras, "Analysis and Modeling of MOS Devices with Gate Oxide Short Failures" Int. Symp. Circuits and Syst., pp. 2164-2167, 1991 [8] V. H. Champac, R. Rodriguez-Montanes, J. A. Segura, J. Figueras and J. A. Rubio, "Fault Modeling of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS Circuits" Europ. Test Conf., pp. 143-148, 1991 [9] R. Rodriguez-Montanes, J. A. Segura, V. H. Champac, J. Figueras and J. A. Rubio, "Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures " Int. Test Conference, pp 510-519, 1991 [10] J. Segura, J. Figueras and A. Rubio, "Approach to the Analysis of Gate Oxide Shorts in CMOS Digital Circuits" Microeletron. Reliab.,Vol. 32, N 11, pp. 1509-1514, 1992 [11] J. A. Segura, V. H. Champac, R. Rodriguez-Montanes, J. Figueras and J. A. Rubio, "Quiescent Current Analysis and Experimentation of Defective CMOS Circuits" JETTA N3, pp.51-62, December 1992 [12] J. Segura, C. De Benito, A. Rubio and C. F. Hawkins, "A Detailed Analysis of GOS Defects in MOS Transistors : Testing Implications at Circuit Level" Int. Test Conference, pp 544-551, 1995 [13] J. Segura, C. De Benito, A. Rubio and C. F. Hawkins, "A Detailed Analysis and Electrical Modeling of Gate Oxide Shorts in MOS Transistors" JETTA N8, pp. 229-239, 1996 [14] M. Renovell, J.M. Gallire, F. Azas, Y. Bertrand,

"A Complete Analysis of the Voltage Behaviour of MOS Transistor with Gate Oxide Short", Defect-Based Testing Work., pp. 5-10, 2001.

Proceedings of the 12th Asian Test Symposium (ATS03) 1081-7735/03 $17.00 2003 IEEE