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Digital Integrated Circuits

A Design Perspective
Bassam Mohd Saed Abed

Implementation Strategies

The Design Productivity Challenge


.10m 1,000,000 100,000 .35m 10,000 1,000 100
X x X
X X X

Transistor/Staff Month
58%/Yr. compound Complexity growth rate

10,000,000 1,000,000 100,000 10,000 1,000 100 10

2.5m

10 1
1981 1985 1987

21%/Yr. compound Productivity growth rate


1991 1993 1995 1997 1999 2003 2005 2007
2001 2009

A growing gap between design complexity and design productivity


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1989

1983

Productivity (Trans./Staff-Month)

10,000,000

Logic Transistors/Chip

100,000,000

Logic Transistors per Chip (K)

Composition of a Generic Processor


MEMORY (Data Storage)

INPUT/OUTPUT

CONTROL
(FSM: Reg+Logic)

DATAPATH (computations)

A System-on-a-Chip (SoC) : Example


SoC integrates processors, large onchip memories and peripherals.

Impact of Implementation Choices


100-1000 Energy Efficiency (in MOPS/mW) Domain-specific processor (e.g. DSP) Embedded microprocessor

10-100

Configurable/Parameterizable

Hardwired custom

1-10

0.1-1

None

Somewhat flexible

Fully flexible

Flexibility (or application scope)

Programmability provides flexibility but comes with overhead (less efficient design)

Implementation Choices
Digital Circuit Implementation Approaches

Custom

Semicustom

Cell-based

Array-based

Standard Cells Compiled Cells

Macro Cells

Pre-diffused (Gate Arrays)

Pre-wired (FPGA's)

Trade-offs: performance/time-to-market/cost Main disadvantage: expensive

Custom Circuit Design


Custom design is handcrafted. Great performance results. But at high cost. Recent processors and designs uses less and less of custom designs.

Intel 4004

Cell-based Design (or standard cells)


Cell-based design shorten the design time by : Automation Reusing limited set of cells. The cells are designed and verified once, and are used many times.

Cell-based design can be partitioned into number of classes: Standard cell Compiled cells Macro cells
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Standard Cell Example


Standard cell approach uses library of cells. Designs are converted to gates, which are placed by tools as shown. This approach is very popular to design chips, except for high performances or low power designs. This approach has benefited advancement in place and route tools and synthesis tools.

Routing channel requirements are reduced by presence of more interconnect layers

Compiled Cells
The standard cell library has several disadvantages. It requires reruns every time the technology changes. It limits the designer to selected cells.

The compiled cell approach converts cell netlist drawn by designer to efficient layout.

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Macro Cells
Macro cell is much more complex than a standard cell. Examples: memory arrays, multipliers, adders, ect. Two types: Hard macro contains the physical design of the module. The design is optimized for speed, area and power. But it is hard to port from one technology to another. Soft macro does not contain the physical design (only synthesized gates). They are easily ported from one technology to another. 11

Semicustom Design Flow


Design Capture Behavioral

HDL
Design Iteration

Pre-Layout Simulation

Structural

Logic Synthesis

Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical

Tape-out
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Array-based implementation
Array-based approach generate the final product quicker and with less cost. However, it has lower integration and performance, higher power.

Array-based

Pre-diffused (Gate Arrays)

Pre-wired (FPGA's)

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Prediffused Arrays

Wafers are manufactured ahead of time. Wafers contain primitive cells. The desired interconnect (wiring) is added later by extra manufacturing steps. There are two approaches Gate array: places cells in rows separated by channels Sea of gates: gates are placed anywhere. There are no routing channels (channel-less.)

Gate Array Sea-of-gates


polysilicon VD D

rows of uncommitted cells

metal GND possible contact

Uncommited Cell

In 1 In 2

In 3 In4

routing channel

Committed Cell (4-input NOR)


Out

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Sea-of-gate Primitive Cells


Oxide-isolation PMOS PMOS

NMOS

NMOS NMOS

Using oxide-isolation

Using gate-isolation
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Prewired Arrays (Field Programmable Gate Arrays: FPGAs)

All the implementation (programming) is done in the field. However, the design are less efficient in the speed, power and design density. Classification of prewired arrays:
Based on Programming Technique
Fuse-based (program-once) Non-volatile EPROM (flash) based RAM based

Programmable Logic Style


Array-Based (programmable logic array: PLA): implement functions expressed in SOP format. Cell-based programmable arrays

Multiplexers method Lookup table method

Programmable Interconnect Style


Array-based programmable wiring (Channel-routing) Switch-box-based programmable wiring (Mesh networks)
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Array-Based Programmable Logic


I5 I4 I3 I2 I1 I0 Programmable OR array I3 I2 I1 I0 Programmable OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array O 3O 2O 1O 0

Fixed AND array


O3O2O1O0

Programmable AND array


O 3O 2O 1O 0

PLA

PROM
Indicates programmable connection Indicates fixed connection

PAL
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Programming a PROM
1 X2 X1 X0

: programmed node NA NA f 1 f 0

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More Complex PAL

i inputs, j minterms/macrocell, k macrocells


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From Smith97

2-input mux as programmable logic block


Configuration A
0 0 0 0 X Y Y 1 1 1

B
0 X Y Y 0 0 1 0 0 1

S
0 1 1 X Y X X X Y 1

F=
0 X Y XY XY XY X1 Y X Y 1

A
B

0
F 1

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Look-up Table Based Logic Cell


In Out 00 01
10 11 ln1 ln2
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Memory

Out 00 1
1 0

Array-Based Programmable Wiring


M

Interconnect Point

Programmed interconnection

Input/output pin

Cell

Horizontal

tracks

Vertical tracks

Interconnect is established by:


. Short circuiting . Fuse . Anitfuse

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Mesh-based Interconnect Network


Switch Box

Connect Box

Interconnect Point

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Courtesy Dehon and Wawrzyniek

Transistor Implementation of Mesh

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Courtesy Dehon and Wawrzyniek

Hierarchical Mesh Network

Use overlayed mesh to support longer connections Reduced fanout and reduced resistance

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Courtesy Dehon and Wawrzyniek