EE141 Digital Integrated Circuits

2nd
Wires
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Digital Integrated
Circuits
A Design Perspective
The Wire
Bassam Jamil & Saed Abed
EE141 Digital Integrated Circuits
2nd
Wires
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The Wire
transmitters
receivers
schematics
physical
Impact of wiring on circuit:
- Increases area
-Increases propagation delay
-Impacts power dissipation
-Introduces extra noise
EE141 Digital Integrated Circuits
2nd
Wires
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Wire Models
All-inclusive model
- Hard to analyze but accurate
Capacitance-only
-Simple and easy to analyze
- But it results in significant
errors in long wires or
short channel circuits.
EE141 Digital Integrated Circuits
2nd
Wires
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Simplifying the Wire Model
Inductive effects can be ignored at
the current technologies.
In short wire, the resistance can be
ignored.
When neighboring wires are far,
coupling capacitance can be
ingnored.
EE141 Digital Integrated Circuits
2nd
Wires
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INTERCONNECT
EE141 Digital Integrated Circuits
2nd
Wires
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Capacitance of Wire Interconnect
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
C
db2
C
db1
C
gd12
C
w
C
g4
C
g3
V
out2
Fanout
Interconnect
V
out
V
in
C
L
Simplified
Model
EE141 Digital Integrated Circuits
2nd
Wires
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Capacitance: The Parallel Plate Model
Dielectric
Substrat e
L
W
H
t
di
Electrical-field lines
Current flow
WL
t
c
di
di
int
c
=
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2nd
Wires
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Permittivity
EE141 Digital Integrated Circuits
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Fringing Capacitance
W - H/2 H
+
(a)
(b)
W/H has been steadily dropping.
Hence, fringe capacitance
has increased and a new model
is needed.
The fringing capacitance model
can be approximated as sum
of two caps.
Note w= W- (H/2)
EE141 Digital Integrated Circuits
2nd
Wires
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Fringing versus Parallel Plate
(from [Bakoglu89])
- For W/H smaller than 1.5
the fringing capacitance
becomes dominant.
-Total capacitances levels
off for W<H.
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2nd
Wires
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Interwire Capacitance
fringing parallel
Wires area coupled
with wires in higher
and lower layers.
Cwire includes:
- Cinterwire
- Cground
- Cparallelplate
EE141 Digital Integrated Circuits
2nd
Wires
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Impact of Interwire Capacitance
(from [Bakoglu89])
Interwire capacitances become
more dominant in higher layer
interconnect, which are farther
away from ground.
EE141 Digital Integrated Circuits
2nd
Wires
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Wiring Capacitances (0.25 m CMOS)
EE141 Digital Integrated Circuits
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Wires
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INTERCONNECT
EE141 Digital Integrated Circuits
2nd
Wires
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Wire Resistance
W
L
H
R =

H W
L
Sheet Resistance
R
o
R
1
R
2
In a particular process, usually H is fixed.
EE141 Digital Integrated Circuits
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Interconnect Resistance
Al is widely used because of:
- Low cost
- Compatibility with fabrication
process
EE141 Digital Integrated Circuits
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Wires
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Sheet Resistance
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Polycide Gate MOSFET
n
+
n
+
SiO
2
PolySilicon
Silicide
p
Silicide is composed of silicon and metal. It has 8-10 times lower resistivity
compared with poly. Polycide (above) combines the advantages of poly and
Silicide:
- Good adherence and coverage
- Low resisitivity
EE141 Digital Integrated Circuits
2nd
Wires
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Dealing with Resistance
Use Better Interconnect Materials
reduce average wire-length
e.g. copper, silicides
More Interconnect Layers
reduce average wire-length
EE141 Digital Integrated Circuits
2nd
Wires
Skin Effect
At high frequency, the current tend to flow primarily on the
surface of a conductor with the current density falling off
exponentially with depth into the conductor. This is referred
to as Skin Effect.
Skin depth () is the depth where the current falls off e
-1
of its
nominal value.
Skin effect usually an issue for wider wires (e.g. clock wires).
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EE141 Digital Integrated Circuits
2nd
Wires
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Interconnect
Modeling
Simulated Wire Delays
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)
V
in
V
out
L
L/10 L/4 L/2 L
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EE141 Digital Integrated Circuits
2nd
Wires
Wire Delay Models
Ideal wire
same voltage is present at every segment of the wire at every point in time - at equi-
potential
only holds for very short wires, i.e., interconnects between very nearest neighbor gates
Should not be used in short-channel technology.
Lumped C model
When the resistive component is small and the switching frequency is low to medium, can
consider only C; the wire itself does not introduce any delay; the only impact on
performance comes from wire capacitance
c
wire
Driver
capacitance per unit length
V
out
C
lumped
R
Driver
V
out
good for short wires; pessimistic and inaccurate for long wires
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Wire Delay Models, cont
Lumped RC model
total wire resistance is lumped into a single R and total capacitance into
a single C
good for short wires and simple
Has two problems:
pessimistic and
inaccurate for long wires
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Lumped RC Network/Tree
RC tree characteristics
A unique resistive path exists
between the source node and any
node of the network
- Single input (source) node, s
- All capacitors are between a node
and GND
- No resistive loops
Shared path resistance (resistance shared along the paths from the input
node to nodes i and k)
r
ik
= r
j
(r
j
e [path(s i) path(s k)])
N
j=1
Path resistance (sum of the resistances on the path from the
input node to node i)
r
ii
= r
j
(r
j
e [path(s i)]
i
j=1
s
r
1
1
2
3
4
i
r
2
r
4
r
3
r
i
c
1
c
2
c
4
c
i
c
3
A typical wire is a chain network with (simplified) Elmore
delay of
t
Di
= c
k
r
ik
N
k=1
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Lumped RC Network/Tree
R
44
= R
1
+ R
3
+ R
4
R
i4
= R
1
+ R
3
R
i2
= R
1
t
Di
= r
1
(c
1
+ c
2
)
+ ( r
1
+ r
3
) (c
3
+ c
4
)
+ ( r
1
+ r
3
+ r
i
) c
i
s
r
1
1
2
3
4
i
r
2
r
4
r
3
r
i
c
1
c
2
c
4
c
i
c
3
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EE141 Digital Integrated Circuits
2nd
Wires
Chain (Non-Branching)Network Elmore Delay
c
1
c
2
c
i-1
c
i
c
N
r
1
r
2
r
i-1
r
i
r
N
V
in
V
N
1 2 i-1 i N
t
D1
=c
1
r
1
t
D2
=c
1
r
1
+ c
2
(r
1
+r
2
)
t
Di
=c
1
r
1
+c
2
(r
1
+r
2
)++c
i
(r
1
+r
2
++r
i
)
So, for wire with length L and N identical segments, total
capacitance of C, and total resistance of R:
t
DN
= RC (N+1)/(2N)
When N is large, then
t
DN
= RC/2
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EE141 Digital Integrated Circuits
2nd
Wires
Distributed RC Model and Wire Length
A length L RC wire can be modeled by N segments of
length L/N
The resistance and capacitance of each segment are given by
r L/N and c L/N
t
DN
= (L/N)
2
(cr+2cr++Ncr) = (crL
2
) (N(N+1))/(2N
2
) = CR((N+1)/(2N))
where R (= rL) and C (= cL) are the total lumped resistance and
capacitance of the wire
For large N t
DN
= RC/2 = rcL
2
/2
Delay of a wire is a quadratic function of its length, L
The delay is 1/2 of that predicted (by the lumped model)
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Wire Delay Models, cont
Distributed RC model
circuit parasitics are distributed along the length, L, of the wire
c and r are the capacitance and resistance per unit length
AL 0
No closed form solution exists.
(r,c,L)
V
N
V
in
rAL
V
in
V
N
rAL rAL rAL rAL
cAL cAL cAL cAL cAL
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Step Response Points
Voltage Range Lumped RC Distributed RC
0 50% (t
p
) 0.69 RC 0.38 RC
0 63% (t) RC 0.5 RC
10% 90% (t
r
) 2.2 RC 0.9 RC
0 90% 2.3 RC 1.0 RC
Example: Consider a Al1 wire 10 cm long and 1 m wide
Using a lumped C only model with a source resistance (R
Driver
) of 10 kO and
a total lumped capacitance (C
lumped
) of 11 pF
t
50%
= 0.69 x 10 kO x 11pF = 76 ns
t
90%
= 2.2 x 10 kO x 11pF = 242 ns
Using a distributed RC model with c = 110 aF/m and r = 0.075 O/m
t
50%
= 0.38 x (0.075 O/m) x (110 aF/m) x (10
5
m)
2
= 31.4 ns
t
90%
= 0.9 x (0.075 O/m) x (110 aF/m) x (10
5
m)
2
= 74.25 ns
Poly: t
50%
= 0.38 x (150 O/m) x (88+254 aF/m) x (10
5
m)
2
= 112 s
Al5: t
50%
= 0.38 x (0.0375 O/m) x (5.2+212 aF/m) x (10
5
m)
2
= 4.2 ns
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EE141 Digital Integrated Circuits
2nd
Wires
Putting It All Together
R
Driver
V
in
V
out
r
w
,c
w
,L
Total propagation delay consider driver and wire
t
D
= R
Driver
C
w
+ (R
w
C
w
)/2 = R
Driver
C
w
+ 0.5r
w
c
w
L
2
and t
p
= 0.69 R
Driver
C
w
+ 0.38 R
w
C
w
where R
w
= r
w
L and C
w
= c
w
L
The delay introduced by wire resistance becomes
dominant when (R
w
C
w
)/2 > R
Driver
C
W
(when
L > 2R
Driver
/R
w
)
For an R
Driver
= 1 kO driving an 1 m wide Al1 wire, L
crit
is 2.67 cm
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EE141 Digital Integrated Circuits
2nd
Wires
Simulation Models For Distributed RC Line
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EE141 Digital Integrated Circuits
2nd
Wires
Scaling Wires: Ideal Scaling
Ideal scaling: scale all dimensions of the wire with the
same scale, except length.
Scaling the length
Local wires scales similar to transistors.
S
L
= S >1
Constant length scaling
S
L
= 1
Global wires increase in length every generation
S
L
= S
c
< 1
Ideal scaling results in significant increase wire
resistance
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EE141 Digital Integrated Circuits
2nd
Wires
Scaling Wires
We have to differentiate between local and
global wires.
We will consider three models:
local wires (SL = S > 1) : the wire length decreases
constant length wires (SL = 1),
global wires (SL = SC < 1): the wire length increases
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EE141 Digital Integrated Circuits
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Wires
Scaling Wires: Ideal Scaling
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EE141 Digital Integrated Circuits
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Wires
Constant Resistance Scaling
Constant Resistance scaling does not
scale wire thickness (H)
While this approach does not increase
resistance, it increases fringing
capacitance by a scaling factor
This scaling scenario offers a slightly
more optimistic perspective, assuming
of course that
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EE141 Digital Integrated Circuits
2nd
Wires
Constant Resistance Scaling
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