ITC Program 2008

Plenary & Technical Special Ancillary Intro At-a-Glance Tutorials Exhibits Addresses Papers Tracks Panels Workshops Events
Registration Venue
ITC Test Week 2008
Intro At-a-Glance Tutorials Exhibits Addresses
Plenary &
Technical Special Ancillary Papers Tracks Panels Workshops Events Registration Venue
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Welcome Message
Highlights
ITC Test Week 2008
On behalf of the over 100 volunteers, International Test Conference (ITC) is proud to present our 39th technical program featuring a fullweek of test-focused technical activities. The volunteer organizers work tirelessly to bring you a comprehensive program that includes papers, panels, lectures, advanced industrial practices, exhibits, tutorials and workshops on IC test, board test and system test. The 2008 technical program will also include embedded tutorials and a poster session. Some of the week's highlights include: Tutorials: Test Week opens with 17 tutorials covering such diverse topics as high-speed interface testing, design-for-manufacturing, silicon debug and diagnosis, statistical screening, delay test, scan compression, failure mechanisms and high-quality test methods for nanometer technologies, analog mixed-signal and RF test, memory test, IEEE Std. 1500, system-in-package test, and wafer-probe. Leading industry experts provide a wide breadth of knowledge to assist the test engineer in keeping up with new and changing technologies. Keynote Address: The conference opens with the plenary session. Mike Lydon, Cisco, will deliver the keynote address Managing Test in the End-to-End, Mega Supply Chain. Exhibits: After the plenary session, be sure to visit our dynamic exhibit floor where major industry suppliers will be displaying their latest products and technologies. Invited Talks: There will be three invited speakers making their presentations after lunch on Tuesday, Wednesday and Thursday Tuesday: Jan Rabaey, University of California, Berkeley, delivers the invited address Computing at the Crossroads (and What Does it Mean to Verification and Test?) Wednesday: Bob Pease, National Semiconductor, has an interactive conversation on Having FUN with Analog Test Thursday: Jeff Rearick, AMD, discusses the issue This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company
Technical Program: Our exciting technical program begins after the invited address on Tuesday, and extends for three days and 35 sessions. Find out the latest advances in such hot topics as design-formanufacturability, power-aware test, recent advances in delay test, logic diagnosis, silicon debug, and high-quality test methods. Learn more about whats going on in traditional topics such as analog, mixed-signal, RF, microprocessor test and DFTas well as defects, memory, ATE and board test. Lecture Series and Advanced Industrial Practices: We continue to supplement the program with the lecture series and advanced industrial practices sessions. This year we have sessions on high-speed interface testing, board testing, automotive test, practical test engineering, and a special joint session with the Autotestcon conference on system test. Embedded Tutorials: New for 2008, we will be having on Tuesday two tutorials as part of the regular technical program. One will be on mixed-signal production test, and the other on defect-based test. Posters: Another new feature for 2008 is a poster session during the post-panel party on Wednesday. The poster session provides an opportunity for presenting late-breaking results and getting feedback on innovative methods. It allows for greater interaction between the attendee and presenter. Workshops: Closing out Test Week are three workshops on design for reliability and variability, defect- and data-driven testing, and ATE vision 2020. As you can see, Test Week 2008 is packed with numerous opportunities for education and the exploration of exciting new technologies. We encourage you not to miss the industry's leading test conference. You can find more at our Web site http://itctestweek.org. We look forward to seeing you in Santa Clara this October.
Douglas Young General Chair
Nur Touba Program Chair
Sponsors
Corporate Supporters
Diamond
Test Technology Technical Council
Platinum
Philadelphia Section
Gold
Silver
Intro At-a-Glance Tutorials Exhibits Addresses
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Test Week Highlights
Welcome Message
ITC Test Week 2008
WEDNESDAY
THURSDAY
TUESDAY
MONDAY
SUNDAY
Seventeen New or Updated Full-Day Tutorials

A great way to prepare for the ITC Technical program
Six Panels Two Embedded Tutorials Plenary Session and Keynote 100 Technical Papers Three Invited Addresses
Hot topics of current interest
Lecture Series
Special sessions containing introductory and broadening material
Advanced Industrial Practices

Real-world solutions to tough problems
Hot Topic Background Sessions

An early-morning prep for the sessions to follow
Poster Session World-Class Exhibits

Free exhibits-only admission on Wednesday afternoon and All day on Thursday
Corporate Presentations
The latest technical innovations from or exhibitors and corporate supporters
Workshops
Finish your Test Week experience with a choice of three
Fringe Technical Meetings Networking and Social Events
Become an ITC corporate supporter Take advantage of numerous advertising opportunities.
http://www.itctestweek.org
FRIDAY
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Test Week At-a-Glance
WednesdayFriday
ITC Test Week 2008
SUNDAY, OCTOBER 26 FULL-DAY TUTORIALS

8:30 a.m. 4:30 p.m. Tutorial 1 Topics and Advances in Silicon Debug and Diagnosis Tutorial 2 Delay Testing: A Practical Approach Tutorial 3 IEEE 1500 Building a Compliant Wrapper Tutorial 4 Advanced Memory Testing Tutorial 5 Microelectronic Wafer Test Technology Tutorial 6 Design for Manufacturability, Yield and Reliability Tutorial 7 Design-forTestability for RF Circuits and Systems Tutorial 8 Scan Compression TechniquesTheory and Practice
MONDAY, OCTOBER 27 FULL-DAY TUTORIALS

8:30 a.m. 4:30 p.m. Tutorial 9 DFT Fundamentals for Digital Test Tutorial 10 DFx: The Convergence of Test, Manufacturing and Yield Tutorial 11 Analog, MixedSignal and RF Testing Tutorial 12 Digital Becomes Analog: Interfaces in High-Speed Test Tutorial 13 Delay Testing: Theory and Practice Tutorial 14 Memory Test: Practical and Implementation Viewpoint Tutorial 15 Scan-based Yield Improvement, Debug and Diagnosis Tutorial 16 Statistical Screening Methods for Quality & Reliability Tutorial 17 Test Strategies for System-inPackage
MONDAY, OCTOBER 27 SPECIAL PANEL

5:00 p.m. 6:30 p.m. Panel 1 Power-aware DFTDo We Really Need It?
TUESDAY, OCTOBER 28 TECHNICAL SESSIONS

8:00 a.m. 9:15 a.m. 9:30 a.m. 10:30 a.m. 10:30 a.m. 5:45 p.m. 11:00 a.m. 4:30 p.m. 12:00 p.m. 1:15 p.m. 1:15 p.m. 1:45 p.m. 2:00 p.m. 3:30 p.m. Embedded Tutorial E1 Outliers and the Testing Tools that Reveal Them: A Fair and Balanced Introduction to Statistics in Test Embedded Tutorial E2 A Brief Overview of Mixed-Signal Production Test for the Beginner
Plenary Session / Keynote Address: Managing Test in the End-to-End, Mega Supply Chain Exhibits Corporate Presentations Lunch - Complimentary Lunch in Exhibit Hall at Noon Invited Address: Computing at the Crossroads (And What Does it Mean to Verification and Test?) Session 1 Dealing with Outliers and Variation in Today's ICs Session 5 Defect Avoidance and Cost Modeling Session 2 Microprocessor Test Session 3 Embedded Memory Diagnosis and Characterization Session 7 ATPG and SAT Session 4 High-Speed I/O Testing in the Real World Session 8 High-Performance Interfacing Advanced Industrial Practices 1 Automotive Test Practices Lecture 1 Basics of Test Engineering Series
4:15 p.m. 5:45 p.m.
Session 6 Delay Testing and Chip Performance Maximization
TUESDAY, OCTOBER 28 WELCOME RECEPTION

6:15 p.m. 8:00 p.m. Hyatt Regency Hotel - Santa Clara Ballroom
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ITC Test Week 2008
WEDNESDAY, OCTOBER 29 TECHNICAL SESSIONS

8:00 a.m.8:30 a.m. 8:30 a.m.10:00 a.m. Hot-Topic Background Session Overview of Power and Its Impact on Test Session 9 Power-aware DFT Methods Session 10 Opens + Shorts Session 11 Advances in Board Interconnect Test Technology Session 12 System-level Microprocessor Online Test Lecture 2 Jitter and Signal Integrity for Gbps I/O
8:30 a.m.4:30 p.m. 9:30 a.m.5:45 p.m. 10:30a.m.12:00 p.m.
Corporate Presentations Exhibits Free entry 1:00 p.m. 5:45 p.m. Session 14 Diagnostics Session 15 Access and Opens at Board Test Session 16 Innovative Solutions to Complex SOCs Lecture 3 Elevator Talks
Session 13 Power Impact on Compression and At-Speed Scan
12:00 p.m.1:00p.m. 1:00 p.m.1:45 p.m. 2:00 p.m.3:30 p.m.
Lunch - Complimentary Lunch in Exhibit Hall at Noon. Invited Address: Having FUN with Analog Test Session 17 Advances in Defect Diagnosis and Silicon Debug Panel 2 Analog Test Technology: Stable or Open Loop Session 18 Industry Experience with Complex Designs Panel 3 Will Test Compression Run out of Gas? Session 19 Poster Previews Session 20 RF Testing Lecture 4 Practical Issues in Board Test Panel 6 The University DFT Tool Showdown
4:15 p.m.5:45 p.m.
Panel 4
Panel 5 Yield LearningWho Gains, Who Picks Up the Tab?
WEDNESDAY, OCTOBER 29 POSTER SESSION/OCTOBERFEST PARTY

5:45 p.m. 7:15 p.m. Posters Party Santa Clara Convention Center Great America Ball Room
THURSDAY, OCTOBER 30 TECHNICAL SESSIONS

8:00 a.m.8:30 a.m. 8:30 a.m.10:00 a.m. Hot-Topic Background Session Overview of Test Generation and Analysis for Reducing Test Escapes Session 21 Test Quality Defects, DPPM and Patterns, Oh My! Exhibits Session 26 Reliability and Power Supply Noise Analysis Session 22 Software to the Rescue! Session 23 "Outside the Box" DFT Solutions Session 24 Systems Effects of Errors and Protection Methods Session 25 Embedded Memory Test Advanced Industrial Practices 2 STDF Failed Datalog Std
9:30 a.m. 2:00 p.m. 10:30 a.m. 12:00 p.m.
Free entry 9:30 a.m. 2:00 p.m. Session 27 ATE Instrumentation Design Ideas Session 28 Path and SmallDelay Fault ATPG Session 29 Test Standards I Session 30 Test for Physical Defects in Memories Advanced Industrial Practices 3 New Frontiers in Test
12:00 p.m. 1:00 p.m. 1:15 p.m. 1:45 p.m. 2:00 p.m. 3:30 p.m.
Lunch - Complimentary Lunch in Exhibit Hall at Noon Invited Address: This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company Session 31 Emerging Technologies Test Session 32 Data Converter Testing Session 33 Testing for Interconnect Opens and Crosstalk Session 34 Test Standards II Session 35 Scan-based Compression and Transition Tests Advanced Industrial Practices 4 ITC/AUTOTESTCON Session
THURSDAY, OCTOBER 30 WORKSHOPS

4:00 p.m. 6:30 p.m. 7:00 p.m. 9:00 p.m. Automated Test Equipment Vision 2020 Reception Design for Reliability and Variability Defect- and Data-driven Testing
FRIDAY, OCTOBER 31 WORKSHOPS

8:00 a.m. 4:00 p.m. Automated Test Equipment Vision 2020 Design for Reliability and Variability Defect- and Data-driven Testing
Intro At-a-Glance
Tutorials Exhibits Addresses
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TTTC Full-Day Tutorials

SundayTuesday Wednesday
Monday TTTC Full-Day
ITC Test Week 2008
Thursday-Friday
TTTC TEST TECHNOLOGY EDUCATION PROGRAM (TTEP) 2008

The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes a comprehensive set of Test Technology Tutorials to be held in conjunction with several TTTC-sponsored technical meetings worldwide. The mission of the Test Technology Educational Program (TTEP) is to serve test and design professionals by offering fundamental education and expert knowledge in state-of-the-art test technology topics. TTEP offers tutorial participants the opportunity to earn official certification from IEEE Computer Society TTTC. Each full-day tutorial corresponds to four TTEP units. Upon completion of sixteen TTEP units, official recognition in the form of an IEEE TTTC Test Technology Certificate will be presented to the participant. For further information regarding TTEP, please visit http://tab.computer.org/tttc/teg/ttep/ At ITC08, TTTC/TTEP is pleased to present seventeen full-day tutorials on topics of current interest to test professionals and researchers. All tutorials qualify for credit towards IEEE TTTC certification under the TTEP program. Eight tutorials are held on Sunday, October 26th, and nine on Monday, October 27th. Each tutorial requires a separate registration fee (see ITC registration form or www.itctestweek.org for further information). Admission for on-site registrants is subject to availability. Tutorial attendees receive study material, breakfast, lunch, and coffee breaks. The study material includes a hardcopy of the presentation and bibliographical material. Tutorial registration, coffee and pastry are available at 7:00 a.m. on Sunday and Monday.
Sunday 8:30 a.m. 4:30 p.m. more Sunday tutorials >

TUTORIAL 1 Advanced Topics and Recent Advances in Silicon Debug and Diagnosis Presenters S. Venkataraman, M. Abramovici, R. Aitken Description Silicon debug and TUTORIAL 3 IEEE 1500Building a Compliant Wrapper Presenters T. McLaurin, T. Waayers, F. Da Silva Description The purpose of this tutorial is to
educate the audience with the challenges and benefits associated with implementing IEEE 1500 compliant wrappers for core test. It will also give an understanding of the reasons behind some of the rules in the standard. A 1500 wrapper, with CTL, is built piece-bypiece around an example bare core for illustration purposes. The pros and cons of different choices that are available to the user of the 1500 standard, all rules, integration of cores and SOC test scheduling are all discussed. timing stresses. The results give the attendant a good insight into the effectiveness of the algorithms and stresses.
TUTORIAL 5 Microelectronic Wafer Test Technology Presenters J. Broz, W. Mann Description This is broad tutorial covering
mechanical and electrical aspects of wafer sort and the impact wafer sort practices can have on assembly and device reliability. A general overview of wafer processing, device testing, and package assembly demonstrates importance of wafer sort and exactly where sort fits into the overall manufacturing process. General probe requirements discuss probe/bond pad configurations on the DUT needed for wafer sort, good/bad die identification, feedback to the fab, thoroughness of test, temperature effects, and cost pressures. Each component of a wafer test cell, e.g., the probe cards, the prober, and the ATE, are individually discussed in detail. High-volume manufacturing (HVM) sort-floor challenges discuss probe-card metrology, online cleaning to maintain high yield and throughput, and I/O damage control.
defect diagnosis activities have become a timeconsuming phase in the development cycle of a new design. This tutorial covers the state of the art in silicon debug and defect diagnosis ranging from the basic concepts to advanced applications and new DFD techniques. After a brief review of the basic concepts and applications of diagnostics over the life-cycle of a product, design for debug and silicon debug methods are discussed. Next, recent enhancements and advanced diagnosis topics are covered, including methods for at-speed debug and implementing assertions in silicon, diagnosis for delay-faults, debug of clocking and power networks, and establishing correlation between simulation and silicon. The tutorial finishes with scan-chain diagnosis, BIST-based diagnosis, and diagnosis for yield learning.
TUTORIAL 4 Advanced Memory Testing Presenter A. van de Goor Description The tutorial covers SRAM fault
modeling, test generation, tests and stresses, DFT, BIST and BISR. Spice simulation and IFA establishes faults in SRAMs; e.g., SAFs, transition and coupling faults. The fault space is established; address and data scrambling are addressed together with data backgrounds and addressing schemes, speed-related and peripheral circuit faults require nonlinear tests such as MOVI, GalRow, etc. A large set of SRAM tests (GalPat, MATS+, March C-, March LR, etc.) are covered; DFT, BIST and BISR are presented. The tutorial ends with a case study, in which a set of tests is applied to high speed industry SRAMs, using algorithm stresses, such as Fast-X/Fast-Y, different data backgrounds, etc.; together with voltage and
TUTORIAL 2 Delay Test: A Practical Approach Presenters A. Cron, B. Cory Description This tutorial provides an introduction to path and transition delay test techniques. It concentrates on design, vector generation methods, and vector application requirements. Attendees of the tutorial should be able to dive right into their next delay test challenge.
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Intro At-a-Glance
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Monday TTTC Full-Day
SundayTuesday Wednesday Thursday-Friday Sunday 8:30 a.m. 4:30 p.m. < previous Sunday tutorials
TUTORIAL 6 Design for Manufacturability, Yield and Reliability Presenters Y. Zorian, J.-A. Carballo Description In addition to designing the
TUTORIAL 7 Design-for-Testability for RF Circuits and Systems Presenters M. Margala, S. Osev Description As the level of integration
continues to increase, the test cost escalates. This issue only becomes aggravated as ICs are being designed with faster speed, more complexity, and higher density. Traditional testing mechanisms are specification-based and incapable of meeting current trends in test cost reductions. In addition, with the rapid growth of the wireless telecommunications industry, testing of RF circuitry has gained significant attention. The test costs associated with RF systems is considerable, affecting both time-tomarket and product cost requirements. The number of ATEs available with RF testing capabilities is sparse, and, therefore, these testers are exorbitantly expensive. The purpose of this tutorial is to educate the audience with efficient embedded DFT methods for RF circuits and systems. Its main focus is on practical and implementation aspects. The presented techniques and methodologies are extensively supported by silicon data.
TUTORIAL 8 Scan Compression Techniques: Theory and Practice Presenters R. Parekhji, T. W. Williams, R. Kapur, J. Abraham Description This tutorial provides
functionality, todays SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SOC design methodology. Techniques for enhancing manufacturability, yield, and reliability, or DFX, include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called Infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SOC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques and provides related examples.
a comprehensive coverage of scan compression. It begins with cost models to help designers understand the choices available to them. Thereafter, a more detailed view of compression with mathematical underpinning of the different techniques is presented. Implementation techniques and tradeoffs are described. Diagnostics, which is an important part of deep-submicron designs, are also discussed within the realm of compression. Finally, compression results are be presented to illustrate how best the theory and practice fit together.
Monday 8:30 a.m. 4:30 p.m.

TUTORIAL 9 DFT Fundamentals for Digital Test Presenter G. Perry Description Digital component test has
undergone significant change over the past few years. Circuit complexity, reliability requirements, the cost of test, and many other factors are demanding improvements in test methodologies. This tutorial has been developed to help test, product and applications engineers better understand the various disciplines and motives that have contributed to the advances in test technology. Design-fortestability (DFT) is now included in most digital circuits. Although information on DFT is available, the majority of it focuses on chip design, rather than test. The goal of this tutorial is to provide a fundamental understanding of DFT test-related issues. Subjects include: fault models, automatic test pattern generation, logic scan, boundary scan, BIST, DFT test techniques and analysis, and reduced-pin-count testing.
more Monday tutorials >

TUTORIAL 10 DFx: The Convergence of Test, Manufacturing and Yield Presenter R. Aitken Description The tutorial goal is to show how
design-for-yield (DFY) and design-formanufacturability (DFM) are tightly coupled into what we conventionally think of as test, and that as process geometries shrink, the line between defects and process variation blurs to the point where it is essentially nonexistent. In DFM/DFY circles, it is common to speak of defect-limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g., IDDQ testing, delay testing). This tutorial provides background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.
TUTORIAL 11 Practices in Analog, Mixed-Signal and RF Testing Presenters S. Abdennadher, S. Shaikh Description The objective of this tutorial is to
present existing industry ATE solutions and alternative solutions to ATE testing for mixedsignal and RF SOCs. These techniques greatly rely upon DFT and BIST structures. The tutorial presents the basic concepts in analog and RF measurements (eye diagram, jitter, gain, power compression, harmonics, noise figure, phase noise, BER, etc.). Several industrial examples of production testing of mixed-signal and RF devices, such as, SERDES transceivers, PHYs, HSIO, and RF transceivers are also presented. The block-DFT solutions are presented for PLLs, CDR, equalizers, filters, mixers, AGC, LNAs, DACs and ADCs. The testing of high-speed IO interfaces, such as, PCIe, and SATA, etc, and the new design trends in RF systems such as MIMO and SIPbased systems and their testability are also presented.
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Sunday TTTC Full-Day
ITC Test Week 2008
Thursday-Friday
Monday 8:30 a.m. 4:30 p.m.

TUTORIAL 12 When Digital Becomes Analog Interfaces in High-Speed Test Presenter W. Maichen Description Successful high-speed digital
test requires understanding the behavior of all components involved (device, test equipment, interface), as well as the interaction between them. The boundaries between digital and analog disappear. Connections have to be treated as transmission lines, with every little imperfection impacting system performance, deteriorating test accuracy, and reducing yield. Maintaining signal integrity is paramount in order to achieve meaningful results, and it requires good knowledge of signal-path behavior, proper choice of termination techniques, and good design of the interface. While the tester itself is usually given and not easily modified, large improvements are possible by careful design of the interconnecting load board or probe interface. Apart from theoretical knowledge, methods to quantify the performance of a given design by measurements are necessary as well.
< previous Monday tutorials

TUTORIAL 14 Memory Test from a Practical and Implementation Viewpoint Presenters V. Jayaram, S. Lai Description The task of optimally
configuring memory BIST and implementing it is becoming increasingly difficult in todays deep-submicron designs. Design and test engineers are facing issues with test planning, design integration and silicon debug flows. All of these are coupled with reduced development cycle-times, and that is making the overall process harder. In this tutorial, options available to test memories are covered at a high level and challenges associated with implementing memory BIST are covered in detail. Topics include test approaches used in the industry, algorithm effectiveness, BIST architecture, implementation techniques, physical design challenges, verification, silicon debug and memory repair. Emphasis is given to both compile-time and run-time programmable memory BIST solutions.
TUTORIAL 16 Statistical Screening Methods Targeting "Zero Defect" IC Quality and Reliability Presenter A. Singh Description Integrated circuits have
traditionally all been tested identically in the manufacturing flow. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by adaptively subjecting suspect parts to more extensive testing. The idea is similar to security screening at airports. Such methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on real production circuits by key manufacturers.
TUTORIAL 13 Delay Testing: Theory and Practice Presenters S. Patil, S. Chakravarty Description The goal of this tutorial is to
provide the background and knowledge of DFT methods, tools/methodologies and bestknown industry practices necessary for implementation of delay-test methodology on both custom and ASIC designs. To that end, it covers the following key aspects of delay tests: delay-test models and test application techniques, incorporating environmental conditions such as cross-talk and power droop in delay tests, DFT design techniques to support scan-based delay test, relevant tools and methodologies and representative test case studies from the industry. The focus of the tutorial is primarily scan-based delay tests with emphasis on real-world implementation using industrial case studies. On the theory front, the emphasis is on the easy-tounderstand theoretical concepts related to delay test, and not on the complicated algebra and theory which accompanies many theoretical works on delay test.
TUTORIAL 15 Scan-based Yield Improvement, Debug and Diagnosis Presenters G. Eide, A. Crouch Description Most digital IC designs today
use DFT techniques like internal scan and BIST to increase the designs testability and automate the test generation process. This tutorial is an investigation into detecting and isolating design errors, implementation errors, logic and manufacturing problems using structural techniques and scan architectures. When implemented correctly, scan and other DFT techniques can be used to simplify debug and diagnosis of silicon during device bringup on the tester, characterization, failure analysis and initial and ongoing yield analysis. The tutorial covers how to utilize existing DFT structures as well as how to successfully apply design-for-debug (DFD) and design-for-yield (DFY) techniques and how to collect and relate fail data from the test process to reduce the time to identify the problem or its root cause.
TUTORIAL 17 Test Strategies for System-inPackage Presenter Y. Zorian Description Todays miniaturization and
performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use. This tutorial provides comprehensive knowledge of test solutions for advanced packages by placing particular emphasis on: test and debug approaches for bare dies; testing schemes for flip-chips used in direct-chip attach, CSP and SIP packages; testing bare substrates, and finally, test, diagnosis and repair techniques for assembled modules.
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Embedded Tutorials
Sunday TTTC Full-Day Thursday-Friday
ITC Test Week 2008
Tuesday 8:00 a.m. 9:15 a.m.

These two tutorials are part of the ITC technical program, and are provided free-of-charge to all registered ITC conference attendees.
TUTORIAL E 1 Outliers and the Testing Tools that Reveal Them: A Fair and Balanced Introduction to Statistics in Test Presenter Robert Daasch, ICDT Laboratory, Portland State University
This tutorial is an introduction to statistics and their uses in semiconductor test specifically, outlier screening. Outlier parts are revealed because their test response differs from a statistical model. The tutorial is grouped into three sections each with three ideas. The tutorial starts with a review of three common statistics used in screening outliers; mean and its nonparametric cousin median, variance (inter-quartile range) and correlation. Next are the three components of any statistical model; input, output and error. Third, there are three steps to compute a model; selection of input and output, estimation of model parameters and evaluation of performance. The statistics are combined with the modeling basics to show how regression models detect outliers. Finally, an introduction to statistics is incomplete without a few words of caution such as undersampling, overuse, and overgeneralization. The presenter is not related to Al Franken despite a passing resemblance of the tutorial's title to a book by the comedian, critic, and most recently Democratic candidate for the US Senate. About the speaker: Dr. Robert Daasch is Professor of Electrical and Computer Engineering at Portland State University and Co-Director of the Integrated Circuits Design and Test Laboratory. His research interests are digital and analog IC design and test. He has three patents. Dr. Daasch and his team have received two best paper awards at International Test Conference 2001 and VLSI Test Symposium 2003, and honorable mention at the ITC in 2004. Dr. Daasch presented plenary addresses at ITC in 2006 and the Defectbased Testing Workshop in 2007. He was coordinator and coauthor of the ITC Outstanding Lecture Series in 2005.
TUTORIAL E 2 A Brief Overview of Mixed-Signal Production Test for the Beginner

Presenter Gordon Roberts, McGill University
This tutorial will attempt to describe the basics of mixed-signal production test in less than 1-1/2 hours. Well start by having a brief look at ATE hardware and the importance of the tester interface in the role of mixed-signal test. This will then be followed by a discussion of the three fundamental impairments of analog and mixed-signal circuitsthese being: signal transmission loss, noise, and distortion and how each are tested using ATE. As accuracy and precision are central to any discussion on production test, well look at the implication of these issues on the test process (yield and test time). Finally, well look specifically at the ways in which amplifiers, filters, data converters, SERDES and RF-type devices are tested in production. We shall close out on a short discussion on design-for-test and BIST techniques for mixed-signal testing. About the speaker: Dr. Gordon Roberts is a professor and James McGill Chair of Electrical and Computer Engineering at McGill University. He has co-written five textbooks related to analog IC design and mixed-signal test and he has contributed numerous chapters to industrially focused textbooks. Dr. Roberts together with his students have won numerous awards including the ITC 2000 Best Paper Award, ITC 1994 Honorable Mention Paper Award and the ITC 1993 Honorable Mention Paper Award. He has also won several awards for teaching including the 2000 Best Tutorial Award from the Test Technology Technical Council of the IEEE Computer Society. In 2003 he took leave from McGill to help start DFT Microsystems, Inc., a company specializing in high-speed timing measurement. Dr. Roberts received the B.A.Sc. degree from the University of Waterloo in 1983 and the M.A.Sc. and Ph.D. degrees from the University of Toronto, in 1986 and 1989, respectively. Dr. Roberts is a Fellow of the IEEE.
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Exhibits
Monday: 9 to 11 SundayTuesday
Exhibitors
ITC Test Week 2008
Monday: 12 to 16 Wednesday Thursday-Friday
Visit the international exhibition that includes the latest high-technology test, design and service products.
Exhibits opening: Tuesday 10:30 a.m. 5:45 p.m. Wednesday 9:30 a.m. 5:45 p.m., Thursday 9:30 a.m. 2:00 p.m.
ITC is offering free exhibits-only registration to visit the exhibit hall on Wednesday from 1:00 p.m. to 5:45 p.m. and on Thursday from 9:30 a.m. to 2:00 p.m. On-site registration for this special opportunity begins on Wednesday at 1:00 p.m. at the ITC registration area in the Santa Clara Convention Center.
Intro At-a-Glance Tutorials
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Participating Exhibitors*
Monday: 9 to 11 Monday: 12 to 16
Exhibits Schedule
ITC Test Week 2008
Aehr Test Systems SundayTuesday Wednesday Thursday-Friday Antares Advanced Test Technologies Ardent Concepts, Inc. ARM, Inc. Asset InterTech, Inc. Atrenta, Inc. Azimuth Electronics, Inc. Asterion BucklingBeam Cadence Design Systems, Inc. Carsem Cascade Microtech Centellax, Inc. Chip Scale Review CMR Summit Silicon Valley Corad Technology, Inc. Corelis, Inc. Credence Systems Corp. Dynamic Test Solutions EE Evaluation Engineering Electroglas, Inc. ELES Semiconductor Equipment Spa Evans Analytical Group Everett Charles Technologies Exatron Finley Design Services, Inc. Focused Test, Inc. FormFactor, Inc. GE Fanuc Intelligent Platforms Geotest-Marvin Test Systems, Inc. GOEPEL electronic GmbH Hamamatsu Corp HiLevel Technology, Inc. Inovys Corporation Integra Technologies Integrated Test Corporation Intellitech Corporation inTest Silicon Valley JD Instruments, LLC Johnstech International JTAG Technologies, Inc. Lambda Americas LogicVision, Inc.
M&M Specialties, Inc. MEI Mentor Graphics Corporation Micro Control Company MicroProbe Nano Integrated Solutions, Inc. NHK Spring Company, Ltd. OptimalTest Phoenix Test Arrays, LLC Pickering Electronics Ltd. Pickering Interfaces Ltd. Pintail Technologies Presto Engineering, Inc. Proligent Protos Electronics Q-Star Test QualiSystems R&D Circuits Ried-Ashman Manufacturing Roos Instruments, Inc. Rucker and Kolls, Inc. Sanyu Electric, Inc. Semiconductor Test Consortium SiliconAid Solutions Simutest, Inc. Springer Science & Business Media, Inc. SV Probe, Inc. Synopsys, Inc. SynTest Technologies, Inc. Taconic Teledyne Relays TeraVicta Technologies Teseda Corporation Test Coach Corp. Test Insight Test & Measurement World Tokyo Electron America, Inc. TSSI Unitechno USA, Inc. Virage Logic World Test Systems Yamaichi Electronics USA, Inc.
* As of publication date.
Intro At-a-Glance Tutorials Exhibits
Ancillary Plenary & Technical Special Addresses Papers Tracks Panels Workshops Events Registration Venue Invited Addresses
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Plenary & Keynote Address

Tuesday
Monday: 9 to 11
ITC Test Week 2008
9:30 a.m. 10:30 a.m.
Monday: 12 to 16
SundayTuesday Wednesday Thursday-Friday Opening Remarks Douglas Young, ITC General Chair
ITC 2007 Paper Awards Presentation Janusz Rajski, ITC 2007 Program Chair Keynote Address Managing Test in the End-to-End, Mega Supply Chain Mike Lydon, Vice President, Technology and Quality, Global Supply Chain Management, Cisco
Todays connected environment has created significant growth opportunities in the electronics industry. Products have never been so diverse, ranging from phones that can play movies and give directions to super routers that can move terabits worth of data around the world instantly. It is now possible to access the internet from areas which once had little to no contact at all with the rest of the world. This growth in opportunities has spurred significant supply chain growth with significant growth in both consumers and suppliers. The challenges for todays supply chain have also grown significantly with much greater diversity in products; increasing customer requirements (lower cost, faster deliver, better quality and faster time-tomarket); smaller, denser, faster and more complex technology and a supply chain that now consists of thousands of suppliers and thousands of customers all over the world. All of this with a totally virtual, global supply chain. Mike Lydon will highlight these challenges and discuss how test, and the data produced by test can either enable or disrupt these virtual supply chains. He will talk about communication in the virtual supply chain and how test can enable real time, end-to-end adjustments over the product lifecycle. Mike will conclude by presenting his vision of the test and data managed, optimized, end-to-end, global, virtual supply chain. About the speaker: Mike Lydon, Vice President of Technology and Quality (T&Q), oversees the advanced manufacturing engineering, test, and technology process definition and management. This includes component engineering management, central test development, and manufacturing quality process oversight. Mike has been with Cisco Manufacturing for nine years where hes held a number of roles of increasing responsibility. Prior to his current role, he was in the Product Operations group where he led a team responsible for manufacturing product and test engineering, DfX, lifecycle margin management, value engineering, and product supply strategy for Internet Systems Business Unit (ISBU), Application Delivery Business Unit (ADBU), and the Security Technologies Group (STG). Mike has extensive experience in production operations, product introduction, and R&D at Cisco and elsewhere. In 1998 Mike arrived at Cisco through an acquisition where he reported to the CEO, responsible for the entire supply chain and sourcing strategies, quality oversight, manufacturing engineering, and product cost accountingafter building these capabilities from the ground up. Mike earned a BSME degree from the University of California, Davis.
Intro At-a-Glance Tutorials Exhibits
Ancillary Plenary & Technical Special Addresses Papers Tracks Panels Workshops Events Registration Venue
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Invited Addresses
Monday: 9 to 11 SundayTuesday
Plenary Session
ITC Test Week 2008
Monday: 12 to 16 Wednesday Thursday-Friday About the speaker: Jan Rabaey received the EE and Ph.D degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium. From 1983-1985, he was connected to the UC Berkeley as a Visiting Research Engineer. From 1985-1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. From 1999 until 2002, he was the Associate Chair of the EECS Dept. at Berkeley. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the MARCO GigaScale Systems Research Center (GSRC). He is an IEEE Fellow, and recipient of the 2008 IEEE CAS Mac Van Valkenburg Award.
Tuesday, 1:15 p.m. 1:45 p.m.

Computing at the Crossroads (And What Does it Mean to Verification and Test?)
Jan N. Rabaey, Donald O. Pederson Distinguished Professor, University of California at Berkeley
When looking back over the past six or seven decades, one can only be awed by the tremendous strides computation has made. The nature of the problems we can tackle today is truly astounding. Yet, when speculating about what the coming decades will bring, one cannot escape a perception that some fundamental changes in the computation arena are afoot. Today, we are interpreting computation as the execution of complex algorithms that are executed in sequential fashion and are bound to deliver deterministic answers. A number of factors are conspiring to fundamentally change that model, namely the scaling of technology to the nanoscale dimensions; the emergence of distributed computation and the changing nature of computation and the underlying hardware platforms from a cognitive/perceptive model to statistical model. These trends will have a profound effect on the way we verify and test designs. It is paramount that we start to explore what all of this means today if we want to be prepared for what tomorrow will bring.
Wednesday
1:00 p.m. 1:45 p.m.

Having FUN with Analog Test
Robert A. Pease, Staff Scientist, National Semiconductor
Bob Pease is a legend in the analog design community. Bob has designed analog circuits for over 48 years, including 25 linear ICs and dozens of op amps and discrete circuits. As a designer for 48 years, Bob understands the importance of test engineers, test plans and test design. He also understands the implications of not getting the test done right. Bob will share the good, the bad and the ugly test experiences he's had over the years (in a way that only Bob can do). Bob will also answer pre-submitted questions during the session, making this the first interactive invited talk in ITC history. About the speaker: Robert A. Pease graduated from MIT in 1961 with a BSEE degree. He was originally employed by Philbrick Research, designing several operational amplifiers and analog computing modules. Pease joined National Semiconductor in 1976. He has designed over 25 analog ICs including power regulators, voltage references, and temperature sensors. He has written about 65 magazine articles and holds about 21 US patents. Pease is a Senior Member of the IEEE and is the self-declared Czar of Bandgaps since 1986. He was also inducted into the Electronic Engineers Hall of Fame in October, 2002. He has written the definitive book, Troubleshooting Analog Circuits (May 1991), now in its 17th printing. It has been translated into French, German, Dutch, Russian, Chinese, and Polish. Pease is a columnist in Electronic Design magazine, with over 250 columns published. The column, PEASE PORRIDGE, covers a wide range of technical topics. Many of Pease's recent columns are posted at Electronic Designs web site.
Wednesday
1:15 p.m. 1:45 p.m.

This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company
Jeff Rearick, AMD Fellow, Mile High Design Center, AMD
As cost pressures on electronic products continually increase, the urge to trim investment in test-related circuitry, activity, and equipment increases correspondingly. Not only can this strategy backfire if taken too far, but it also ignores the opportunity for test to actually add value to products. This presentation will examine the positive role that test can play and give audience members a set of guidelines to take back to their own companies so that they can perform their own analyses. Numerous examples from a variety of different electronic industries show a wide range of possible solutions.
About the speaker: Jeff Rearick leads the Design For Testability Center of Expertise at Advanced Micro Devices. He has been an AMD Fellow since 2006 and works at AMDs Mile High Design Center in Fort Collins, Colorado. Prior to joining AMD, Jeff worked for 22 years at HP and Agilent Technologies. Jeff has been active in the test community, serving on the working groups for IEEE1149.6 and IEEE P1687 (for which he is the editor) as well as the ITC program committee. He has published numerous technical papers and has received over 20 patents. He holds a BSEE from Purdue University and a MSEE from the University of Illinois.
Plenary & Intro At-a-Glance Tutorials Exhibits Addresses
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Tuesday
Wednesday A.M.
Wednesday P.M.
ITC Test Week 2008
2:00 p.m. 3:30 p.m.

SESSION 1 Dealing with Outliers and Variation in Invited Today's ICs Addresses SESSION 4 High-Speed I/O Testing in the Real World M. Li, Altera (Chair) SESSION 7 APG and SAT I. Polian, Albert-Ludwigs-University of Freiburg (Chair) 7.1 CONCAT: Conflict-driven Learning in ATPG for Industrial Designs S. Bommu, K. Chandrasekar, R. Kundu, S. Sengupta, Intel 7.2 SAT-based State Justification with Adaptive Mining of Invariants W. Wu, M. Hsiao, Virginia Tech 7.3 RTL Error Diagnosis Using a Wordlevel SAT-Solver S. Mirzaeian, K-T. Cheng, University of California- Santa Barbara; F. Zheng, Zhejiang University
P. Maxwell, Aptina Imaging (Chair) 4.1 External Loopback Testing Monday: 9 to 11 Monday: 12 to 16 Experiences with High-Speed Serial 1.1 A Study of Outlier Analysis Techniques Interfaces for Delay Testing A. Meixner, S. Bedwani, A. Kakizawa, S. Wu, D. Drmanac, L-C. Wang, University of SundayTuesday Wednesday Thursday-Friday B. Provost, Intel California-Santa Barbara 1.2 Production Multivariate Outlier Detection Using Principal Components P. O'Neill, Avago Technologies 1.3 Unraveling Process Variability for Process/Product Improvement A. Gattiker, IBM 4.2 Low-Cost Testing of Multi-GBit Device Pins with ATE-assisted Loopback Instrument W. Fritzsche, A. Haque, Credence Systems 4.3 Efficient High-Speed Interface Verification and Fault Analysis T. Nirmaier, J. Zaguirre, Infineon; E. Liau, A. Rettenberger, W. Spirkl, Qimonda; D. Schmitt-Landsiedel, Technological University of Munich
SESSION 2 Microprocessor Test D. Josephson, Intel (Chair) 2.1 The Test Features of the Quad-Core AMD OpteronTM Microprocessor T. Wood, G. Giles, C. Kiszely, M . Schuessler, D. Toneva, J. Irby, M. Mateja, AMD 2.2 DFx Features of a 3rd-Generation, 16Core/32-Thread, UltraSPARC CMT Microprocessor I. Parulkar, S. Anandakumar, G. Agarwal, G. Liu, K. Rajan, F. Chiu, Sun Microsystems; R. Pendurkar, RMI 2.3 Test Access Mechanism for Multiple Identical Cores G. Giles, J. Wang, A. Sehgal, K. Balakrishnan, J. Wingfield, AMD
4:15 p.m. 5:45 p.m.

SESSION 5 Defect Avoidance and Cost Modeling S. Patil, Intel (Chair) 5.1 Implementation Update: Logic Mapping On SPARC Microprocessors A. Vij, R. Ratliff, Texas Instruments 5.2 Failing-Frequency Signature Analysis J. Lee, E. McCluskey, Stanford University 5.3 A Cost Analysis Framework for Multicore Systems with Spares S. Shamshiri, P. Lisherness, S-J. Pan, K-T. Cheng, University of California-Santa Barbara
SESSION 8 High-Performance Interfacing H. Zhang, Texas Instruments (Chair) 8.1 Embedded Power Delivery Decoupling in Small Form Factor Test Sockets O. Vikinski, S. Lupo, G. Sizikov, C-Y. Chung, Intel 8.2 Measurement Repeatability for RF Test Within the Loadboard Constraints of High-Density and Fine-Pitch SOC Applications T. Warwick, EPE; G. Rivera, D. Waite, J. Smith, Qualcomm; J. Russell, R&D Circuits 8.3 Wafer-level Characterization of Probecards Using NAC Probing G-Y. Kim, E-J. Byun, K-S. Kang, Y-H. Jun, Samsung Electronics; B-S. Kong, Sungkyunkwan University
SESSION 3 Embedded Memory Diagnosis and Characterization R. Adams, Magma Design Automation (Chair) 3.1 High-Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST J. Tyszer, A. Pogiel, Poznan University of Technology; N. Mukherjee, J. Rajski, Mentor Graphics 3.2 A History-based Diagnosis Technique for Static and Dynamic Faults in SRAMs A. Ney, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, LIRMM; M. Bastian, Infineon Technologies 3.3 Analysis of Retention Time Distribution of Embedded DRAM A New Method to Characterize Across-Chip Threshold Voltage Variation W. Kong, P. Parries, G. Wang, S. Iyer, IBM Semiconductor R & D Center
SESSION 6 Delay Testing and Chip Performance Maximization M. Tehranipoor, University of Connecticut (Chair) 6.1 Scan-based Testing of Dual/Multicore Processors for Small Delay Defects A. Singh, Auburn University 6.2 On-Chip Programmable Capture for Accurate Path Delay Test and Characterization R. Tayade, J. Abraham, The University of Texas at Austin 6.3 An Automatic Post-Silicon Clock Tuning System for Improving Chip Performance Based on Tester Measurements K. Nagaraj, S. Kundu, University of Massachusetts
Discover a papers key feature by placing your mouse over the paper number. 2.2
Wednesday P.M. Thursday A.M. Thursday P.M.
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Wednesday A.M.
8:30 a.m. 10:00 a.m.
Tuesday A.M.
ITC Test Week 2008
8:00 a.m. 8:30 a.m. Hot-Topic Background Session

Overview of Power and Its Impact on Test M. Kassab, Mentor Graphics
SESSION 9 Invited Addresses Power-Aware DFT Methods L. Basto, Cadence Design Systems (Chair)
SESSION 12 System-level Microprocessor Online Test S. Seshadri, Intel (Chair)
12.1 Low-Energy Online SBST of Monday: 9 to 11 Monday: 12 to 9.1 A Power-aware Test Methodology for 16 Embedded Processors Multisupply Multi-Voltage Designs A. Merentitis, N. Kranitis, V. Chickermane, P. Gallagher, J. Sage, A. Paschalis, University of Athens; SundayTuesday Wednesday P. Yuan, K. Chakravadhanula, Cadence Thursday-FridayGizopoulos, University of Piraeus D. Design Systems 9.2 Peak Power Reduction Through Dynamic Partitioning of Scan Chains S. Almukhaizim, O. Sinanoglu, Kuwait University 9.3 Power-aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks B. Nadeau-Dostie, K. Takeshita, J-F. Ct, LogicVision 12.2 Online Failure Detection in Memory Order Buffers J. Carretero, X. Vera, P. Chaparro, J. Abella, Intel 12.3 VAST: Virtualization-assisted Concurrent Autonomous Self-Test H. Inoue, NEC; Y. Li, S. Mitra, Stanford University
14.3 Efficiently Performing Yield Enhancements by Identifying Physical Root Cause from Test Fail Data M. Sharma, B. Benware, L. Ling, D. Abercrombie, L. Lee, M. Keim, H. Tang, W-T. Cheng, T-P. Tai, Mentor Graphics; Y-J. Chang, R. Lin, UMC; A. Man, AMD SESSION 15 Access and Opens at Board Test J. Burgess, Intel (Chair) 15.1 Solder Bead on High-Density Interconnect Printed Circuit Board B. Chu, Intel 15.2 Finding Power/Ground Defects on ConnectorsCase Study S. Hird, R. Weng, Agilent Technologies
10:30 a.m. 12:00 p.m.

SESSION 13 Power Impact on Compression and AtSpeed Scan K. Arabi, PMC Sierra (Chair) 13.1 Reducing Power Supply Noise in Linear-Decompressor-based Test Data Compression Environment for AtSpeed Scan Testing M-F. Wu, J-L. Huang, National Taiwan University; X. Wen, K. Miyase, Kyushu Institute of Technology 13.2 Low-Power Scan Shift and Capture in the EDT Environment J. Tyszer, D. Czysz, Poznan University of Technology; M. Kassab, X. Lin, G. Mrugalski, J. Rajski, Mentor Graphics 13.3 Frequency and Power Correlation Between At-Speed Scan and Functional Tests S. Sde-Paz, E. Salomon, Freescale Semiconductor SESSION 14 Diagnostics M. Ward, LSI (Chair) 14.1 Deterministic Diagnostic Pattern Generation for Compound Defects F. Wang, Y. Hu, H. Li, X. Li, Institute of Computing Technology, CAS; Y. Huang, Mentor Graphics, Y. Jing, Peking University 14.2 Diagnosis of Design-Silicon Timing Mismatch with Feature Encoding and Importance RankingThe Methodology Explained P. Bastani, N. Callegari, L- C. Wang, University of California-Santa Barbara; M. Abadir, Freescale Semiconductor
SESSION 10 Opens + Shorts C. Henderson, Semitracks (Chair) 10.1 Time-dependent Behavior of Full-Open Defects in Interconnecting Lines R. Rodrguez-Montas, D. Arum, J. Figueras, Universitat Politcnica de Catalunya; S. Eichenberger, C. Hora, B. Kruseman, NXP Semiconductors 10.2 Statistical Yield Modeling for Subwavelength Lithography A. Sreedhar, S. Kundu, University of Massachusetts at Amherst 10.3 Detection of Internal Stuck-Open Faults in Scan Chains F. Yang, S. Reddy, University of Iowa; S. Chakravarty, N. Devta-Prasanna, LSI; I. Pomeranz, Purdue University SESSION 11 Advances in Board Interconnect Test Technology R. Jukna, Jabil Circuit (Chair) 11.1 Engineering Test Coverage on Complex Sockets M. Schneider, Agilent Technologies; A. Shafi, Advanced Micro Devices 11.2 Solving In-Circuit Defect Coverage Holes with a Novel Boundary-Scan Application J. Grealish, B. Van Dick, D. Dubberke, Intel 11.3 Augmenting Boundary-Scan Tests for Enhanced Defect Coverage D. Norrgard, K. Parker, Agilent Technologies
SESSION 16 Innovative Solutions to Complex SOCs S. Pendharkar, Advanced Micro Devices (Chair) 16.1 Architecture for Testing Multi-VoltageDomain SOC L. Souef, C. Eychenne, E. Ali, NXP Semiconductors 16.2 Integration of Hardware Assertions in Systems-on-Chip J. Geuzebroek, B. Vermeulen, NXP Semiconductors 16.3 Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs H-F. Ko, A. Kinsman, N. Nicolici, McMaster University
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2:00 p.m. 3:30 p.m.
Tuesday A.M.
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ITC Test Week 2008
SESSION 17 SESSION 19 Invited Addresses Advances in Defect Diagnosis and Silicon Poster Previews Debug R. Datta, The University of Texas at Austin (Chair) E. Amyeen, Intel (Chair) Monday: 9 to 11 Monday: 12 to 16 Each poster presenter will give a five17.1 An Effective and Flexible Multipleminute summary of their work. The Defect Diagnosis Methodology Using posters SundayTuesday Wednesday Thursday-Friday session will take place during the Error Propagation Analysis Oktoberfest reception following the X. Yu, R. Blanton, Carnegie Mellon University
Wednesday afternoon panels.

17.2 Detection and Diagnosis of Static Scan Cell Internal Defect R. Guo, L. Lai, Y. Huang, W-T. Cheng, Mentor Graphics 17.3 Optical Diagnostics for IBM POWER6 Microprocessor P. Song, S. Ippolito, F. Stellari, J. Sylvestri, T. Diemoz, G. Smith, P. Muench, N. James, S. Kim, H. Saenz, IBM SESSION 20 RF Testing Y. Makris, Yale University (Chair) 20.1 Octal-Site EVM Tests for WLAN Transceivers on Very Low-Cost ATE Platforms G. Srinivasan, H-C. Chao, F. Taenzler, Texas Instruments 20.2 Optimized EVM Testing for IEEE 802.11a/n RF ICs E. Acar, S. Ozev, Duke University; G. Srinivasan, F. Taenzler, Texas Instruments 20.3 Efficient EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms V. Natarajan, H. Choi, D. Lee, R. Senguttuvan, A. Chatterjee, Georgia Institute of Technology
SESSION 18 Industry Experience with Complex Designs D. Belete, Freescale Semiconductor (Chair) 18.1 Functional Test and Speed/Power Sorting Enablement of the IBM POWER6 and Z10 Processor T. Pham, F. Clougherty, G. Salem, J. Crafts, J. Tetzloff, P. Moczygemba, T. Skergan, IBM 18.2 Transition Test on UltraSPARC T2 Microprocessor L-C. Chen, P. Dickinson, P. Mantri, M. Gala, P. Dahlgren, S. Bhattacharya, O. Caty, K. Woodling, T. Ziaja, D. Curwen, W. Yee, E. Su, G. Gu, T. Nguyen, Sun Microsystems 18.3 DFT Architecture for Automotive Microprocessors Using On-Chip Scan Compression Supporting Dual Vendor ATPG H. Ahrens, R. Schlagenhaft, H. Lang, Freescale Semiconductor; E. Bruzzano, V. Srinivasan, STMicroelectronics
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September 29
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Thursday A.M.
8:30 a.m. 10:00 a.m.
Tuesday A.M.
Wednesday A.M.
ITC Test Week 2008
8:00 a.m. 8:30 a.m. Hot-Topic Background Session

Overview of Test Generation and Analysis for Reducing Test Escapes J. Dworak, Brown University 24.2 Using Implications for Online Error Detection K. Nepal, Bucknell University; N. Alves, J. Dworak, R. Bahar, Brown University 27.3 An Electronics Module for 12.8-Gbps Multiplexing and Loopback Test D. Keezer, A. Majid, Georgia Institute of Technology; D. Minier, P. Ducharme, IBM SESSION 28 Path and Small-Delay Fault ATPG S. Chakravarty, LSI (Chair) 28.1 On Accelerating Path Delay Fault Simulation of Long Test Sequences I-D. Huang, Y-S. Chang, S. Natarajan, R. Sharma, Intel; S. Gupta, USC 28.2 Implicit Identification of Nonrobustly Unsensitizable Paths Using the Bounded Delay Model D. Jayaraman, E. Flanigan, S. Tragoudas, Southern Illinois University Carbondale 28.3 Interconnect-aware and Layoutoriented Test-Pattern Selection for Small-Delay Defects M. Yilmaz, ; K. Chakrabarty, Duke University; M. Tehranipoor, University of Connecticut SESSION 29 Test Standards I A. Cron, Synopsys (Chair) 29.1 Boundary-Scan Testing of Power/Ground Pins K. Parker, Agilent Technologies; N. Jacobson, Xilinx 29.2 IEEE 1500 Core Wrapper Optimization Techniques and Implementation B. Mullane, M. Higgins, C. MacNamee, University of Limerick 29.3 Turbo1500: Toward Core-based Design for Test and Diagnosis Using IEEE Std. 1500 L-T. Wang, R. Apte, S. Wu, B. Sheu, H-J. Chao, J. Guo, J. Liu, Y. Niu, Y-C. Sung, C-C. Wang, F .Li, SynTest Technologies; K-J. Lee, National Cheng Kung University; X. Wen, Kyushu Institute of Technology; W-B. Jone, University of Cincinnati; C-H. Yeh ,W-S. Wang, Silicon Integrated Sys. SESSION 30 Test for Physical Defects in Memories A. Virazel, LIRMM (Chair) 30.1 Defect-oriented Testing of the Strap Problem Under Process Variations in DRAMs Z. Al-Ars, S. Hamdioui, A. van de Goor, Delft University of Technology; G. Mueller, Qimonda 30.2 A New Wafer-level Latent-Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method J. Nam, S. Chun, S. Kang, Yonsei University; G. Koo, Y. Kim, B. Moon, J. Lim, J. Joo, S. Kang, H. Kim, K. Shin, K. Kang, Samsung Semiconductor 30.3 A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories O. Ginez, J-M. Portal, H. Aziza, AixMarseille Universit, IM2NP
SESSION 21 Test QualityDefects, DPPM and Patterns, Oh My! K. Kim,Invited Addresses Intel (Chair) 21.1 Towards a World Without Test Escapes: The Use of Volume Diagnosis Monday: Test QualityMonday: 12 to 16 to Improve9 to 11 S. Eichenberger, J. Geuzebroek, C. Hora, B. Kruseman, A. Majhi, NXP Semiconductors
24.3 A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors Used in Information Systems M. Baradaran Tahoori, S. Shazli, M. AbdulSundayTuesday Wednesday Aziz, 21.2 Modeling Test Escape Rate as a Thursday-Friday D. Kaeli, Northeastern University Function of Multiple Test Coverages SESSION 25 K. Butler, J. Carulli, Jr., J. Saxena, Texas Instruments Embedded Memory Test M. Sonza Reorda, Politecnico di Torino (Chair) 21.3 Evaluating the Effectiveness of Physically-aware N-Detect Test Using 25.1 Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Real Silicon Cell-Bias-Voltage Modulation Y-T. Lin, O. Poku, S. Blanton, Carnegie A. Katayama, T. Yabe, O. Hirabayashi, Mellon University; P. Nigh, V. Iyengar, Y. Takeyama, K. Kushida, T. Sasaki, P. Lloyd, IBM N. Otsuka, Toshiba 25.2 A Shared Parallel Built-in Self-Repair Scheme for Random Access Memories in SOCs T-W. Tseng, J-F. Li, National Central University 25.3 Testing Methodology of Embedded DRAMs C-T. Chao, C-M. Chang, National Chaio-Tung University, R-F. Huang, MediaTek; D-Y. Chen, TSMC
SESSION 22 Software to the Rescue! R. Arnold, Infineon (Chair) 22.1 A Method to Generate a Very LowDistortion, High-Frequency Sine Waveform Using an AWG A. Maeda, Verigy 22.2 Leveraging IEEE 1641 for Testerindependent ATE Software B. Van Wagenen, J. Vollmar, D. Thornton, Teradyne 22.3 Bridging the Gap Between Design and Test Engineering for Functional Pattern Development H. Ahrens, E. Aderholz, M. Rohleder, Freescale Semiconductor SESSION 23 "Outside-the-Box" DFT Solutions A. Jas, Intel (Chair) 23.1 Plug & Test at System Level via Testable TLM Primitives H. Alemzadeh, F. Refan, Z. Navabi, University of Tehran; S. Di Carlo, P. Prinetto, Politecnico di Torino 23.2 Design-for-Test of Asynchronous NULL Convention Logic (NCL) Circuits W. Al-Assadi, S. Kakarla, Missouri University of Science and Technology 23.3 Noncontact Testing for SOC (SIPs) and RCP at Advanced Nodes B. Moore, C. Sellathamby, M. Reja, T. Weng, B. Bai, E. Reid, S. Slupsky, Scanimetrics; M. Mangrum, Freescale Semiconductor; I. Filanovsky, University of Alberta SESSION 24 Systems Effects of Errors and Protection Methods K. Mohanram, Rice University (Chair) 24.1 On the Correlation between Controller Faults and Instruction-level Errors in Modern Microprocessors M. Maniatakos, Y. Makris, Yale University; N. Karimi, University of Tehran; A. Jas, Intel
10:30 a.m. 12:00 p.m.

SESSION 26 Reliability and Power Supply Noise Analysis M. Sachdev, University of Waterloo (Chair) 26.1 Optimized Circuit Failure Prediction for Aging: Practicality and Promise M. Agarwal, AMD; V. Balakrishnan, W. Wang, B. Yang, Y. Cao, Arizona State University; A. Bhuyan, K. Kim, B. Paul, S. Mitra, Stanford University 26.2 SOC Test Architecture Design and Optimization Considering Power Supply Noise Effects F. Yuan, Q. Xu, The Chinese University of Hong Kong 26.3 Observation of Supply-Voltage-Noise Dispersion in Subnanosecond K. Takeuchi, G. Tanaka, H. Matsushita, Renesas Technology; K. Yoshizumi, Y. Katsuki, T. Sato, Hitachi ULSI Systems SESSION 27 ATE Instrumentation Design Ideas D. Oka, LOA Technology (Chair) 27.1 A Hybrid A/D Converter with 120-dB SNR and 125-dB THD M. Tamba, Yokogawa Electric 27.2 Generating Test Signals for Noisebased NPR/ACPR-type Tests in Production S. Aouini, G. Roberts, McGill University
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SESSION 31 Emerging Technologies Test Invited Addresses V. Iyengar, IBM (Chair)
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ITC Test Week 2008
SESSION 33 Testing for Interconnect Opens and Crosstalk D. Walker, Texas A&M University (Chair)
SESSION 35 Scan-based Compression and Transition Tests G. Mrugalski, Mentor Graphics (Chair) 35.1 Increasing Scan Compression by Using X-Chains P. Wohl, JA. Waicukauski, F. Neuveux, Synopsys 35.2 Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors O. Sinanoglu, Kuwait University 35.3 Launch-on-Shift-Capture Transition Tests I. Park, E. McCluskey, Stanford University
Monday: 9 to 11 Monday: 12 to 16 31.1 Fabrication Defects and Fault Models 33.1 Test Generation for Interconnect for DNA Self-Assembled Opens SundayTuesday Thursday-Friday Nanoelectronics Wednesday X. Lin, J. Rajski, Mentor Graphics V. Mao, C. Dwyer, K. Chakrabarty, Duke University 33.2 A Novel Pattern Generation Framework for Inducing Maximum 31.2 Built-in Self-Test and Fault Diagnosis Crosstalk Effects on Delay-sensitive for Lab-on-Chip Using Digital Paths Microfluidic Logic Gates J. Lee, M. Tehranipoor, University of Y. Zhao, T. Xu, K. Chakrabarty, Duke Connecticut University 31.3 Testing Techniques for Hardware Security M. Majzoobi, F. Koushanfar, Rice University; M. Potkonjak, University of California, Los Angeles 33.3 Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model S. Hillebrecht, I. Polian, P. Engelke, B. Becker, Albert-Ludwigs University M. Keim, W. Cheng, Mentor Graphics
SESSION 32 Data Converter Testing D. An, CMC Microsystems (Chair) 32.1 Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter Estimation L. Jin, National Semiconductor
SESSION 34 Test Standards II C. Barnhart, Cadence Design Systems (Chair)
34.1 The Advantages of Limiting P1687 to a Restricted Subset J. Doege, AMD; A. Crouch, ASSET InterTech 34.2 A New Language Approach for IJTAG M. Portolan, S. Goyal, Bell Labs Ireland; B. Van Treuren, C-H. Chiang, T. Chakraborty, T. Cook, Alcatel-Lucent Bell Labs 34.3 Problems Using Boundary-Scan for Memory Cluster Tests B. Van Treuren, C-H. Chiang, K. Honaker, Alcatel-Lucent
32.2 Built-in Self-Calibration of On-Chip DAC and ADC W. Jiang, V. Agrawal, Auburn University 32.3 A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing T. Yamaguchi, M. Kawabata, M. Ishida, K. Uekusa, Advantest Laboratories; M. Soma, University of Washington
Free
Exhibits Admission
Wednesday 1:00 p.m.5:30 p.m. Thursday 9:30 a.m. 2:00 p.m.
Plenary & Technical Intro At-a-Glance Tutorials Exhibits Addresses Papers
Special Ancillary Tracks Panels Workshops Events Registration Venue

Corporate Presentations Posters
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Lecture Series
ITC Test Week 2008
ITC's Lecture Series provides a showcase for topics that are important to the test industry either because they are at the leading edge of technology or because they are foundational in nature. This year's series again provides a bit of both, beginning with introductory material covering the basics of test engineering, or what they dont teach in the textbooks. The second lecture covers jitter test for high performance I/O, while the third Invited Addresses introduces an elevator talk format for ITC: a series of brief talks covering active research areas from top test academics. The last session covers practical aspects of board test. All four sessions will provide a solid background for as well as a snapshot of the current state of the art.
SundayTuesday LECTURE 1
Wednesday
Thursday-Friday LECTURE 3 Tuesday 4:15 p.m.5:45 p.m. Elevator Talks S. Mitra, Stanford University (Chair) Elevator talks from eight test professors about the top test research areas, including reliability, FPGA based testers, new fault models and error tolerance. Presenter list: L. Anghel, TIMA M. Breuer, USC K. Iwasaki, Tokyo Metropolitan University C. Metra, University of Bologna K. Mohanram, Rice University C. Stroud, Auburn Uuniversity C.-W. Wu, STC Taiwan H.-J. Wunderlich, University of Stuttgart Wednesday 10:30 a.m.12:00 p.m.
Basics of Test Engineering Series J. Rearick, AMD (Chair) L 1.1 What the Text Books Didnt Teach You About Test Engineering (Part 1: Beginnings) Z. Conroy, Cisco Systems L 1.2 What the Text Books Didnt Teach You About Test Engineering (Part 2: Advanced) Z. Conroy, Cisco Systems L 1.3 The Pros and Cons of Logic BIST G. Giles, AMD
LECTURE 2 R. Aitken, ARM (Chair)
Wednesday 8:30 a.m.10:00 a.m.
LECTURE 4 Practical Issues in Board Test A. Ley, ASSET InterTech (Chair)
Wednesday 2:00 p.m.3:30 p.m.
Jitter and Signal Integrity for Gbps I/O
L 2.1 Jitter and Signaling Verification at Multiple Gbps M. Li, Altera L 2.2 Jitters in High-Performance Microprocessors T. Mak, Intel Corp L 2.3 Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment J. Moreira, H. Barnes, B. Roth, Verigy; H. Kaga, NEC Electronics; M. Comai, Advanced Micro Devices; M. Culver, Agilent Technologies
L 4.1 Challenges of Implementing Bead Probe Technology in HighVolume Manufacturing C. Tee, Intel L 4.2 Embedded Testing in an In-Circuit Test Environment J. Malian, W. Eklow, Cisco Systems L 4.3 Hardware-based Error Rate Testing of Digital Baseband Communication Systems A. Alimohammad, S. Fouladi Fard, B. Cockburn, University of Alberta

Corporate Presentations Posters
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Lecture Series
ITC Test Week 2008
Advanced Industrial Practices sessions provide an opportunity for attendees to learn the latest methods and techniques used by industry leaders in addressing some of todays most important test challenges. This years AIP sessions include an introduction to automotive test, including DFT, Invited Addresses production flow, and zero defects practices, followed by a tutorial on the STDF Fail Datalog Standard, and a session covering diverse topics such as optical test, high performance probe test, and the test implications of new design techniques. The final session outlines practical methods for Monday: DFT at the system level12 to 16 Monday: justifying 9 to 11
SundayTuesday AIP SESSION 1 Automotive Test Practices K. Mandl, Teradyne (Chair) Wednesday Thursday-Friday Tuesday 2:00 p.m.3:30 p.m. AIP SESSION 3 New Frontiers in Test R. Aitken, ARM (Chair) Thursday 10:30 a.m.12:00 p.m.
A 1.1 DFT Implementations for Striking the Right Balance Between Test Cost and Test Quality for Automotive SOCs R. Parekhji, Texas Instruments (India) A 1.2 A Cooperative Effort Between Design and Production Flows to Meet Automotive Quality Requirements F. Melchiori, D. Pandini, S. Pugliese, D. Appello, STMicroelectronics; P. Bernardi, Politecnico di Torino A 1.3 Achieving Zero Defects for Automotive Applications R. Raina, Freescale Semiconductor
A 3.1 Parametric Testing of Optical Interfaces B. Achkir, B. Eklow, Cisco Systems A 3.2 POWER6 Reliability Screens and Test Methodology F. Clougherty, J. Crafts, J. Dery J. VanHorn IBM A 3.3 New Circuit Design Techniques that Every Test Engineer Should Know About S. Naffziger, AMD
AIP SESSION 2 STDF Fail Datalog Standard R. Aitken, ARM (Chair)
Thursday 8:30 a.m.10:00 a.m.
AIP SESSION 4
Thursday 2:00 p.m.3:30 p.m.
Special Joint ITC/AUTOTESTCON Session A. Ambler, University of Texas at Austin A 4.1 Justifying DFT with a Hierarchical Top-Down Cost Model S. Davidson, Sun Microsystems A 4.2 The Economics of Harm Prevention Through Design for Testability L. Ungar, A.T.E. Solutions A 4.3 DFT, Starting at the Beginning with Knowledge of the End J. Lauffer, C. dePaul, DSI International
A 2.1 A Tutorial on STDF Fail Datalog Standard A. Khoche, P. Burlison, Verigy; J. Rowe, Teradyne; G. Plowman, Qualcomm

Advanced Industrial Practices Posters
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Tuesday 11:00 a.m. 4:30 p.m.
Lecture Series
ITC Test Week 2008
Wednesday 8:30 a.m. 4:30 p.m.
The corporate track allows you to stay on top of the latest commercial products in the semiconductor test industry and helps you Invited Addresses understand how the innovations behind the products can add value to your employer. Whereas the technical program allows you to gain an in-depth understanding of the latest technical innovations, the corporate track allows you to actually gain an in-depth understanding Monday: 9 to technology innovations impact the product portfolios of companies. In this interactive forum, executives of ITC Monday: 12 to 16 of how some of the11 exhibitors or sponsors will present their latest products and sometimes product roadmaps. Moreover, company representatives are free to hand out relevant literature such as Thursday-Friday papers or marketing material. Typical presentations include case studies, best practices, and SundayTuesday Wednesday testimonials. For example, last years corporate track covered innovative products in the area of EDA, ATE, test software, yield learning, adaptive test, probe-cards, high-speed test, boundary scan, STIL, and switching technologies. Attendance to the sessions will be open to all conference attendees.
Thirty-six companies participated in 2007, and we expect a similar representation this year. Check future issues of this advance program to obtain further information and a schedule.

Corporate Presentations ITC Test Week 2008
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Posters
Lecture Series
Wednesday 5:45 p.m.7:15 p.m. held in conjunction with the Oktoberfest reception. Poster previews will be given in Session 19 on Wednesday at 2:00 p.m. Invited Addresses
N. Touba, University of Texas at Austin (Chair/Coordinator)
Monday: 9 to 11 Monday: 12 to 16 PO 1 Overview of IEEE P1450.6.2 Standard: Creating CTL Models for Memory Test and Repair SundayTuesday Wednesday Thursday-Friday S. Adham, LogicVision PO 2 IEEE P1581 Drastically Simplifies Connectivity Test for Memory Devices H. Ehrenberg, GOEPEL Electronics PO 3 Low-Power Test S. Bahl, R. Sakar, A. Garg, STMicroelectronics PO 4 IEEE 1500-compatible Secure Test Wrapper for Embedded IP Cores J. Li, G-M. Chiu, National Taiwan University PO 5 Test-Access Solutions Three-Dimensional SOCs X. Wu, Y. Chen, Y. Xie, Penn State University; K. Chakrabarty, Duke University PO 6 SOC Test Optimization with Compression Technique Selection A. Larsson, X. Zhang, E. Larsson, Linkping University; K. Chakrabarty, Duke University PO 7 SOC Yield Improvement: Redundant Architectures to the Rescue? J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, LIRMM PO 8 Platform-independent Test Access Port Architecture Margulis, T. Wood, S. Metsis, Advanced Micro Devices; D. Akselrod, McMaster University PO 9 NoC Reconfiguration for Utilizing the Largest Fault-free Connected Substructure A. Alaghi, M. Sedghi, N. Karimi, Z. Navabi, University of Tehran PO 10 VLSI Test Exercise Courses for Students in EE Department S. Komatsu, University of Tokyo PO 11 Hardware Overhead Reduction for Memory BIST M. Arai, K. Iwasaki, Tokyo Metropolitan University; M. Nakao, I. Suzuki, Renesas Technology PO 12 A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances C-F. Lin, C-F. Huang, D-C. Lu, C-C. Hsu, W-T. Chiu, Y-W. Chen, Y-J. Chang, Faraday Technology PO 13 The Importance of Functional-like Access for Memory Test J. Phelps, C. Johnson, C. Goodrich, A. Kokrady, Texas Instruments PO 14 An Efficient Secure Scan Design for an SOC Embedding AES Core J. Song, T. Jung, J. Lee, H. Jeong, B. Kim, S. Park, Hanyang University PO 15 Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains J. Ye, F. Wang, Y. Hu, X. Li, Institute of Computing Technology, CAS PO 16 Diagnosis of Logic-to-Chain Bridging Faults J. Li, W-C. Liu, W-L. Tsai, H-T. Lin, National Taiwan University PO 17 Power Distribution Failure Analysis Using Transition-Delay Fault Pattern Generation J. Lee, J. Ma, M. Tehranipoor, University of Connecticut; PO 18 Is It Cost-effective to Achieve Very High Fault Coverage for Testing Homogeneous SOCs with Core-level Redundancy? L. Huang, Q. Xu, The Chinese University of Hong Kong PO 19 System JTAG Initiative Group Advancements B. Van Treuren, Alcatel-Lucent PO 20 A Generic Framework for Scan Capture Power Reduction in Test Compression Environment X. Liu, F. Yuan, Q. Xu, The Chinese University of Hong Kong PO 21 High Test Quality in Low-Pin-Count Applications J. D'Souza, S. Mahadevan, N. Mukherjee, G. Rhodes, Mentor Graphics; T. Droniou, J. Moreau, P. Armagnat, D. Sartoretti, STMicroelectronics PO 22 Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise H-T. Lin, J-Y. Wen, J. Li, National Taiwan University; M-T. Chang, M-H. Tsai, S-C. Huang, C-M. Tseng PO 23 Test Quality Improvement with Timing-aware ATPG: Screening Small Dely Defect Case Study J. Chang, AMD; T. Kobayashi, Mentor Graphics PO 24 FPGA-based Time Measurement Module: Preliminary Results W. Bowhers, Merrimack College PO 25 Wireless Test Structure for Integrated Systems Z. Noun, P. Cauvet, NXP Semiconductors; M-L. Flottes, D. Andreu, S. Bernard, LIRMM PO 26 Overview of a High-Speed Topside Socket Solution J. Stewart, T. Animashaun, Intel PO 27 Improving the Accuracy of Test Through Adaptive Test Update S. Biswas, Nvidia; R. Blanton, Carnegie Mellon University
Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Papers Tracks
Panels Workshops
Ancillary Events Registration Venue
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Panels
Monday, 5:00 p.m. 6:30 p.m. Panel 1 Power-aware DFTDo We Really Need It?
Invited Addresses K. Butler, Texas Instruments (Moderator) N. Mukherjee, Mentor Graphics (Organizer)
ITC Test Week 2008
Scan-based vectors dissipate much more power compared to the functional operation of a device. These vectors are known to cause IR drop, voltage droop, hot spots, etc. 11 Monday: 9 to Consequently, there is an increase in demand for power reporting, insertion of DFT logic to control power dissipation during shift Monday: 12 to 16 as well as capture, design partitioning, imposing power threshold limits during ATPG, etc. But there are some basic questions that need to be answered. Is there a real power dissipation problem during test mode? Is it impacting yield today? How do we make sure that power dissipation during test SundayTuesday Wednesday Thursday-Friday correlates well with the functional mode? Are we under-testing our design if we restrict power? This panel provides a forum to ask these tough questions to the experts and help us understand how to address the challenges in the near future. Panelists: R. Galivanche, Intel W. Huott, IBM P. Krishnamurthy, LSI B. Pouya, Freescale Semiconductor J. Rearick, AMD
Wednesday, 4:00 p.m. 5:30 p.m.

Panel 2 Analog Test Technology: Stable and Grounded, or Open Loop and Spurious? T. Lee, Stanford University (Moderator) M. Purtell, Intersil (Organizer) Reuse spanning decades of analog test circuits (Op-amp measurement loops), ATE, and test methodology will be discussed with solutions for the future. DSP, BIST, ATE vs. load board solutions, trimming, precision measurements and other analog topics will be discussed. Panelists: T. Anderson, Teradyne S. Goyal, National Semiconductor T. Schmitz, Intersil S. Sunter, LogicVision Panel 3 Will Test Compression Run Out of Gas? J. Rearick, AMD (Moderator) E. Marinissen, NXP Semiconductors, S. Goel, LSI (Organizers) This panel addresses the question if test data compression was only a temporary fix, or a truly future-proof solution. Interoperability, low-power test, high-volume diagnosis, digital vs. analog testing, built-in self-test and low-cost ATEs will all be discussion in the scope of the future of test compression. Panelists: S. Bhatia, Cadence Design Systems S. Pateras, LogicVision J. Rajski, Mentor Graphics J. Rivoir, Verigy
Panel 4 Debug War Stories

M. Abadir, Freescale Semiconductor (Moderator) L. Winemberg, Freescale Semiconductor (Organizer) A panel of experts in silicon debug will describe their most difficult/challenging debug scenarios. While describing their scenarios they will stop at various points and ask the audience what they think the next step should be. Are you ready to match wits with our panelists to help debug this war? Panelists: R. Aitken, ARM R. Antley, Texas Instruments D. Carder, Freescale Semiconductor J. Carulli, Texas Instruments
Panel 5 Yield LearningWho Gains, Who Picks Up The tab?

R. Nelson, Reed Business Information (Moderator) P. Burlison, Verigy (Organizer) Expanding the role of test into improved yield learning has been a recent hot topic. This panel of executives representing fabless, foundry, outsourced semiconductor assembly and test (OSAT) and ATE segments will discuss who gains from this effort and how, and perhaps more controversially, who should pick up the tab. Panelists: D. Ahlgren, Verigy C. Cheung, ASE
Panel 6 The University DFT Tool Showdown

S. Davidson, Sun Microsystems (Moderator/Organizer) Think that university DFT work can't handle real designs? Think again. This panel highlights work by four university researchers on the OpenSparc T1 and T2 processors, open source versions of commercially available multicore microprocessors. Come see which universities can best beat industry in handling real designs. Panelists: D. Gizopoulos, University of Piraeus I. Polian, Albert-Ludwigs-University of Freiburg I. Parulkar, Sun Microsystems M. Sonza Reorda, Politecnico di Torino L. Wang, University of California
Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Papers Tracks Panels
Workshops
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Registration & Schedules
Workshop Summaries
ITC Test Week 2008
IEEE Computer Society Test Technology Technical Council Workshops

Thursday Addresses Invited and Friday
General Workshop Information
Monday: 9 to 11
Three workshops are being held in parallel immediately following ITC 2008 at the Santa Clara Convention Center. They start with an opening address on Thursday afternoon, October 30, followed by a technical session. A reception for all workshop participants will be held Thursday-Friday on Thursday evening. The remaining the technical sessions will be held on Friday, SundayTuesday Wednesday October 31. The technical scope of each workshop is described below.
Monday: 12 to 16
Workshop Registration
All workshop participants require registration. To register in advance for one of the workshops, do so online or by faxing the download form. Otherwise, register on-site at regular rates during Test Week at the ITC registration counter at the Santa Clara Convention Center. Admission for on-site registrants is subject to availability. Discount workshop registration rates apply until September 29, 2008. See pages 25 and 26 for details. Workshop registration includes the opening address, technical sessions, digest of papers, workshop reception, break refreshments, continental breakfast and lunch.
Digest of Papers
A digest of papers will be distributed only to attendees at the workshops as an informal proceedings.
Workshop Schedule
All three workshops will adhere to the same schedule: Thursday, October 30 Registration 2:00 p.m. 7:00 p.m. Opening Address 4:00 p.m. 4:30 p.m. Technical Session 4:30 p.m. 6:30 p.m. Reception 7:00 p.m. 9:00 p.m. Note: Workshop schedule is subject to change Friday, October 31 Registration 7:30 a.m. 10:00 a.m. Technical Sessions 8:00 a.m. 4:00 p.m.
Further Information
For more information on the three workshops contact their organizers by e-mail or check the TTTC Web site http://computer.org/tttc
Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Papers Tracks Panels
Workshops
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Workshop Summaries
Registration & Schedules
ITC Test Week 2008
ATE Vision 2020: IEEE International Workshop on Automated Test Equipment Vision 2020
Scope: This workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuits get denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test quality target.Invited Addresses Certain dies require known-good-die (KGD) quality levels, whereas more complex failure modes already challenge our yield learning curves. These issues, when added to increasing cost-of-test (COT), time-to-volume (TTV), and time-to-market (TTM) pressures, driven by todays high-volume market applications, pose significant challenges to the ATE industry. To meet those challenges the 9 to 11 needs to innovate16 areas such as test methodologies, interconnection technologies, architectures, and designMonday: industry Monday: 12 to in for-testability (DFT) technologies. The goal of this workshop is to create an informal forum to discuss those innovations relevant to ATE developers and users. We are looking for solutions to the issues of 2020 and beyond, not those of 2008. Are our roadmaps SundayTuesday addressing future test Wednesday Do we have the right business models in place to succeed in the future? Join the discussion. challenges? Thursday-Friday Representative topics include, but are not limited to the following:
ATE for statistical test ATE/EDA link Lost-cost ATE Adaptive design techniques RF and high-speed I/O test Test methods for future defects
General Chair: Erik Volkerink, erik.volkerink@verigy.com Program Chair: Scott Davidson, Scott.Davidson@sun.com
DRV: IEEE Workshop on Design for Reliability and Variability
Scope: As silicon-based CMOS technologies are fast approaching their ultimate limits reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation-induced soft-errors and crosstalk. These problems are creating barriers to further technology scaling and are forcing the introduction of new process and design solutions aimed at maintaining acceptable levels of reliability. As elimination of these issues is becoming increasingly difficult, various design techniques including self-calibration and fault tolerance are emerging as the most promising design approaches to circumvent them. However, these techniques may incur significant area, power or performance penalties. Thus, to enable their adoption by industrial teams, there is need for new solutions which minimize these penalties, together with automation tools. The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost. Topics to include:
Reliability issues in advanced CMOS Variability-aware design Radiation effects in advanced CMOS Design-for-Reliability Fault-tolerant architectures Variability mitigation Self-calibrating architectures Online monitoring of circuit parameters Design automation for fault tolerance Variability-insensitive architectures Reliability assessment tools
General Chairs: Yervant Zorian, zorian@viragelogic.com, Michael Nicolaidis, Michael.nicolaidis@imag.fr
D3T: IEEE Workshop on Defect- and Data-driven Testing
Scope: New test-data-based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-50nm technology nodes. Data-driven testing (DDT) has been in practice for a number of years. It is now gaining attention more than ever in adaptive test. DDT can provide feedbacks on which tests to add/remove, or test subsets (e.g., reduced MINVDD test sets.) It can also be utilized for improving quality of logic test patterns (e.g., small delay defect, defect-based) vs. outlier analysis tests (e.g., MINVDD, IDDQ). However, test data has not been easily accessible by smaller companies and researchers in academia. These issues will be discussed in this years D3T workshop. The D3T is aimed at addressing these issues and others related to this years theme DataDriven Testing (DDT). Paper presentations on topics related to the workshops theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade:
Outlier identification Data-driven testing Test data analysis Adaptive testing Data mining methods for test data processing Low voltage testing Noise and crosstalk testing Nanometer test challenges Defect coverage and Metrics Mixed-current/voltage testing Economics of defect-based testing Fault localization and diagnosis
General Chair: Rob Aitken, rob.aitken@arm.com Program Chair: Mohammad Tehranipoor, tehrani@engr.uconn.edu
Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Tracks Panels Workshops Papers
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Networking and Social Events
ITC Test Week 2008
Invited Addresses Monday: 9 to 11 SundayTuesday
Welcome Reception
Tuesday, October 28, 6:15 p.m. 8:00 p.m. Hyatt Regency Hotel Monday: 12 to 16 Santa Clara Ballroom
Wednesday Thursday-Friday All registered ITC attendees and registered exhibitors are cordially invited to attend. Beverages and light refreshments will be served. Come and meet your colleagues at this special social event. Renew your contacts and build your professional network by making valuable new connection.
Continue your debates and examine the poster presentations at the complimentary beer and snack event that follows the panels.
Oktoberfest Party
Santa Clara Convention Center Great America Ballroom Wednesday, October 29 5:45 7:15 p.m.
Workshop Reception
Santa Clara Convention Center
Thursday, October 30
7:00 9:00 p.m.
Ancillary Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Tracks Panels Workshops Events Papers
Registration Venue
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Categories & Fees
Registration Hours
Publications
Hotel Reservations
ITC Test Week 2008
Register Online
or
Download Form
All Test Week activities require a registration badge for admittance. Register in advance online or by faxing the download form. Otherwise, register on-site at regular rates Invited Addresses during Test Week at the ITC registration counter at the Santa Clara Convention Center. See page 26 for registration hours. Monday: 9 to 11 To obtain a substantial Monday: 12on 16 discount to ITC Full-Conference Registration, Tutorial Registration and Workshop Registration, register Wednesday September 29, 2008. no later than Thursday-Friday SundayTuesday technical paper and panel sessions, lecture and advance industrial application series, exhibits, ITC welcome reception, break refreshments, ITC proceedings CD-ROM and ITC tote. Registration does not include the tutorials on Sunday and Monday or the workshops on Thursday and Friday. May purchase additional CD-ROM proceedings at $25 each; one presentation CD-ROM at $25.
Tutorial Registration includes one tutorial, study

material, continental breakfast, lunch and coffee breaks. The study material includes a hardcopy of the presentation material; and, when applicable, a relevant textbook (textbooks are provided to attendees who register at IEEE/CS member or nonmember rates). You may register for two tutorials (one on Sunday and one on Monday). Registration does not include the ITC technical program, exhibits, ITC CD-ROM proceedings, ITC tote or the workshops on Thursday and Friday.
ITC Full-Conference Registration includes ITC
Workshop Registration includes the items specified on

page 21. Registration does not include the ITC technical program, exhibits, ITC CD-ROM proceedings, ITC tote or the tutorials on Sunday and Monday.
Discount Rates for early registration apply only when

your completed registration form and payment are postmarked or faxed by September 29, 2008. Online registrations must also be received by this date. To receive IEEE/Computer Society member or student member reduced rates, you must include your member number.
Special on-site ITC registrations: One-Day; Three-Day Exhibits-only and Free Wednesday afternoon and Thursday Exhibits-only, are available only at the ITC registration counter at the Santa Clara Convention Center.
ITC One-Day Registration includes ITC technical

program activities, exhibits and refreshments for the day of registration only, and ITC proceedings CD-ROM. May purchase: additional CD-ROM proceedings at $25; one presentation CDROM at $25.
IEEE Design & Test of Computers Magazine You may subscribe during online registration or on the downloaded registration form that is to be faxed to BADGEGuys at +1 678.407.3237. ITC Free Exhibits-only Registration Wednesday
1:00 5:30 p.m. and Thursday 9:30 a.m. 2:00 p.m.
ITC Three-Day Exhibits-only Registration includes

the exhibits and lunches for all three daysTuesday through Thursday
Registration Fees
Discount Rates*
IEEE/CS Member Nonmember IEEE/CS Student Member Nonmember Student
Full Conference $495 $630 $240 $300 Full Conference $610 $770 $300 $380
1-Day-only Conference n.a. n.a. n.a. n.a. 1-Day-only Conference $255 $320 n.a. n.a.
3-Day Exhibits-only n.a. n.a. n.a. n.a. 3-Day Exhibits-only $65 $65 n.a. n.a.
One Tutorial $320 $400 $320 $320 One Tutorial $385 $485 $385 $385
Workshop $240 $300 $130 $165
Onsite Rates
IEEE/CS Member Nonmember IEEE/CS Student Member Nonmember Student
Workshop $295 $370 $160 $200
*not available after September 29, 2008
Refunds
Registration fees paid by September 29 are refundable on written request to ITC, c/o BADGEGuys, 1959 Jester Circle, Lawrenceville, GA 30043 USA, postmarked or faxed (+1 678.669.1802) by September 29, 2008. A $75 processing fee is charged for each refund.
Registration Venue
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Registration Hours
Categories & Fees
Publications
Hotel Reservations
ITC Test Week 2008
Invited Addresses
Conference and Tutorials
Workshops
Sat, Oct 25 Monday: 9 to 11 Monday: 12 to 16 Sun, Oct 26 7:30 a.m. 5:00 p.m. Mon, Oct 27 7:30 a.m. 5:00 p.m. SundayTuesday Wednesday Thursday-Friday Tues, Oct 28 7:30 a.m. 7:00 p.m. Wed, Oct 29 7:30 a.m. 5:00 p.m. Thurs, Oct 30 7:30 a.m. 1:00 p.m. Fri, Oct 31
2:00 p.m. 7:00 p.m. 7:30 a.m. 10:00 a.m.
Exhibitors 10:00 a.m. 5:00 p.m. 7:30 a.m. 5:00 p.m. 7:30 a.m. 5:00 p.m. 7:30 a.m. 5:00 p.m. 7:30 a.m. 5:00 p.m. 7:30 a.m. 1:30 p.m.
Need More Registration Information?

Contact the ITC office 2025 M Street, NW, Suite 800, Washington, DC 20036, USA Tel. +1 202.973.8665 Fax. +1 202.331.0111
Free Parking!
at the Santa Clara Convention Center
Registration Venue
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Publications
Categories & Fees
Registration Hours
Hotel Reservations
ITC Test Week 2008
Invited Addresses Monday: 9 to 11 SundayTuesday
ITC Proceedings Distribution
AllMonday: 12 to 16 and one-day attendees, including students, will receive free of full-conference charge at the conference the ITC proceedings on CD-ROM.
Wednesday Ordering Thursday-Friday Additional Proceedings During Advance Registration
Full-conference attendees may also order additional copies of the CD-ROM proceedings, beyond the free copy, at $25 each.
Purchasing Additional Proceedings at the Conference

Additional copies of the CD-ROM proceedings may be purchased on-site for $25 each.
A valuable option!
ITC Technical Paper Presentation CD-ROM

The ITC Program Committee has compiled the slides used for this years paper presentations and placed them in a CD-ROM*. You can review sessions that you attended and cover those that you could not attend. They will only be available at the conference to registered full- and one-day conference attendees, including studentsone per person. The cost for this very popular item is only is $25 each.The CDs may be ordered with your advance registration or purchased on-site. The paper presentation slides make the perfect complement to the full manuscripts in the proceedings, as they contain the latest data .
*Some authors have chosen not to participate. These papers will be indicated in a list provided in the Conference Guide Addendum.
Slides used in panel sessions and corporate presentations are not included.
Registration Venue
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Hotel Reservations
Categories & Fees
Registration Hours
Publications
ITC Test Week 2008
Online Hotel Reservations
Reserve a hotel room online. For further housing information, send e-mail to jay@connectionshousing.com or call 1.800.262.9974 or 404.842.0000
Invited Addresses
1. Reservations will be accepted starting July 10, 2008. Assignments will be made in the order of request. 2. Reservations may be made to 16 or by fax using the downloaded housing form. online Monday: 9 to 11 Monday: 12 3. All room must be guaranteed with a major credit card. 4. Reservations will be confirmed within three to five business days after the day that the reservation was made. If you SundayTuesday your form and do not hear from us within seven days, please contact Jay Pierce at 1.800.262.9974 or Thursday-Friday have faxed Wednesday 404.842.0000. 5. Cancellation: Guests must cancel their reservation more than 72 hours prior to arrival (three full days prior to the scheduled date of arrival). Cancellations may be subjected to a penalty fee equal to one nights room rate and tax if less than 72 hours notice is given. 6. If requesting double accommodations, please provide the name of the second guest and specify one or two beds. 7. Please verify the arrival and departure dates on the confirmation letter sent from Connections. The departure date is the day that you leave the hotelnot the last night of your stay. 8. Check-in time is 3:00 p.m. For any early arrival to be guaranteed, the room must be booked for the previous night. 9. Deadline date for housing submissions is October 3, 2008. After October 3, rooms at the ITC rate are subject to availability. 10. All reservation requests must be made through Connections, not with the individual hotels. 11. Changes and cancellations must be submitted in writing via e-mail to Jay Pierce.
Hotel Rates (exclusive of taxes) and distance to convention ctr.

1. Hyatt Regency Santa Clara (connected) 2. The Hilton Santa Clara (across street) 3. Santa Clara Marriott (0.8 mile, 1.3 km) 4. Holiday Inn Great America (0.8 mile, 1.3 km) $194
$179
$178
$154
Ancillary Plenary & Technical Special Intro At-a-Glance Tutorials Exhibits Addresses Tracks Panels Workshops Events Registration Papers
Venue
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Location & Travel Location
ITC Test Week 2008
The ITC conference and all associated Test Week events will be held at the Santa Convention Center, 5001 Great America Parkway (corner of Tasman Drive), Santa Clara, California 95054 and the adjacent Hyatt Monday: 9 to 11 Monday: 12 to 16 Regency Santa Clara Hotel. Santa Clara is the center of Silicon Valley, an hour south of San Fancisco. The convention center is adjacent to SundayTuesday Wednesday Thursday-Friday the Santa Clara Golf and Tennis Club. Also nearby is the interactive Intel Museum. There are many restaurants at the Mercado Santa Clara entertainment and food complex, Rivermark Plaza and Santana Row. For more information about Santa Clara, visit http://santaclara.org.
Invited Addresses
Travel
Air
Norman Y. Mineta San Jose International Airport (SJC) http://www.sjc.org is about a 10-minute drive south of the convention center. San Francisco International Airport (SFO) and Oakland International Airport (OAK) are about 30 miles north of the convention center. Driving instructions from the airports to the convention center can be found at http://www.santaclara.org/gettingaround/driving.cfm. There are several other options for traveling from San Jose Airport to the convention center and hotels: Taxi - Taxis are the most direct means available. They can be found at terminals A and C. The cost is about $18-$25. Click here to view a list of available taxi companies. Shuttle - Shuttles to hotels can either be arranged over the telephone or can be found waiting in one of two areas: Terminal A - In the Ground Transportation Center located south of the terminal garage. Terminal C On the street, just south of the baggage claim area. The approximate cost for one-way trip is $16.00 - $23.00 per person. Click here to view a list of available shuttle companies. Public Transportation via VTA Light Rail - Take the free Route 10 (Airport Flyer) shuttle at the San Jose Airport to the Metro/Airport Light Rail Station. Buy your ticket using the ticket machine, before boarding ($ 1.75 each way.) Take the Light Rail north toward the direction of Mountain View. Get off at the Great America stop, which is directly across the street from the Santa Clara Convention Center. The approximate time of travel is 45 minutes.
Car
Convention Center Parking - Parking at the convention center is FREE. Spaces are available in front of the convention center and in the multilevel parking garage behind the convention center. You can enter the convention center parking garage by exiting Great America Parkway at the driveway between the Hyatt Regency Hotel and Techmart (Bunker Hill Rd.) From the East Bay Take I-880 South and exit onto CA-237 West toward Mountain View. After 4 miles, take the Great America Parkway exit and turn left. After 1 mile, the convention center will be on your left at Bunker Hill Lane. From the Peninsula (including San Francisco International Airport) Take US-101 South and exit at Great America Parkway/Bowers Avenue and turn left onto Great America Parkway. After 1 mile, the convention center will be on your right just past Tasman Drive. From Bay Area South (including San Jose International Airport) Take I-880 North to US-101North and exit at Great America Parkway/Bowers Avenue, turn right onto Great America Parkway. After 1 mile, the convention center will be on your right just past Tasman Drive.
VTA Light Rail

The Santa Clara Convention Center is located at the Great America stop of the Mountain ViewWinchester and Alum RockSanta Teresa lines. Maps, schedules and fares can be found here.
Intro At-a-Glance
Ancillary Plenary & Technical Special Tutorials Exhibits Addresses Tracks Panels Workshops Events Registration Papers
Venue
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Information
1. The Advance Program was generated with Adobe Acrobat 8.0 on 12-August-2008. 2. Best viewed at 75% to 100%.
Invited Addresses
ITC Test Week 2008
3. The program will be updated periodically as new material is availablecheck back often. 4. Navigate using the tabs at the top of each page. 5.SundayTuesday links in the At-a-Glance to find specific items. Use underlined Wednesday Thursday-Friday 6. Most of the papers have a key feature. Place your cursor over the shaded paper number to see it. 31.3 7. For more information contact: Subject Advance Program Advanced Industrial Practices Corporate Presentations Exhibits and Exhibiting Fringe Technical Meetings Hotels Lecture Series Plenary and Invited Talks Registration Support and Advertising Technical Papers and Panels Tutorials Workshops All Other Questions Contact Don Denburg Rob Aitken Erik Volkerink Ron Press Courtesy Associates Connections Housing Rob Aitken Bill Eklow Courtesy Associates Amy Gold Nur Touba Dimitris Gizopoulos Yervant Zorian Courtesy Associates Email testweek@rcn.com rob.aitken@arm.com erik.volkerink@verigy.com ron_press@mentor.com ITC@courtesyassoc.com jay@connectionshousing.com rob.aitken@arm.com beklow@cisco.com pwagner@courtesyassoc.com a.gold@advantest.com touba@ece.utexas.edu dgizop@unipi.gr zorian@viragelogic.com pwagner@courtesyassoc.com

ITC Program 2008

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ITC Program 2008

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Plenary & Technical Special Ancillary Intro At-a-Glance Tutorials Exhibits Addresses Papers Tracks Panels Workshops Events

ITC Test Week 2008

Intro At-a-Glance Tutorials Exhibits Addresses

ITC Test Week 2008

Douglas Young General Chair

Nur Touba Program Chair

Test Technology Technical Council

Intro At-a-Glance Tutorials Exhibits Addresses

Test Week Highlights

ITC Test Week 2008

Seventeen New or Updated Full-Day Tutorials

Advanced Industrial Practices

Hot Topic Background Sessions

Poster Session World-Class Exhibits

Fringe Technical Meetings Networking and Social Events

Become an ITC corporate supporter Take advantage of numerous advertising opportunities.

At-a-Glance Tutorials Exhibits Addresses

Test Week At-a-Glance

ITC Test Week 2008

SUNDAY, OCTOBER 26 FULL-DAY TUTORIALS

MONDAY, OCTOBER 27 FULL-DAY TUTORIALS

MONDAY, OCTOBER 27 SPECIAL PANEL

TUESDAY, OCTOBER 28 TECHNICAL SESSIONS

4:15 p.m. 5:45 p.m.

Session 6 Delay Testing and Chip Performance Maximization

TUESDAY, OCTOBER 28 WELCOME RECEPTION

At-a-Glance Tutorials Exhibits Addresses

Test Week At-a-Glance

ITC Test Week 2008

WEDNESDAY, OCTOBER 29 TECHNICAL SESSIONS

8:30 a.m.4:30 p.m. 9:30 a.m.5:45 p.m. 10:30a.m.12:00 p.m.

Session 13 Power Impact on Compression and At-Speed Scan

12:00 p.m.1:00p.m. 1:00 p.m.1:45 p.m. 2:00 p.m.3:30 p.m.

4:15 p.m.5:45 p.m.

Panel 5 Yield LearningWho Gains, Who Picks Up the Tab?

WEDNESDAY, OCTOBER 29 POSTER SESSION/OCTOBERFEST PARTY

THURSDAY, OCTOBER 30 TECHNICAL SESSIONS

9:30 a.m. 2:00 p.m. 10:30 a.m. 12:00 p.m.

THURSDAY, OCTOBER 30 WORKSHOPS

FRIDAY, OCTOBER 31 WORKSHOPS

Tutorials Exhibits Addresses

TTTC Full-Day Tutorials

Monday TTTC Full-Day

ITC Test Week 2008

TTTC TEST TECHNOLOGY EDUCATION PROGRAM (TTEP) 2008

Sunday 8:30 a.m. 4:30 p.m. more Sunday tutorials >

Tutorials Exhibits Addresses

TTTC Full-Day Tutorials

Monday TTTC Full-Day

Monday 8:30 a.m. 4:30 p.m.

more Monday tutorials >

Tutorials Exhibits Addresses

TTTC Full-Day Tutorials

Sunday TTTC Full-Day

ITC Test Week 2008

Monday 8:30 a.m. 4:30 p.m.

< previous Monday tutorials

Tutorials Exhibits Addresses

Sunday TTTC Full-Day Thursday-Friday

ITC Test Week 2008

Tuesday 8:00 a.m. 9:15 a.m.

TUTORIAL E 2 A Brief Overview of Mixed-Signal Production Test for the Beginner

Intro At-a-Glance Tutorials