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First Encounter
Date: Fri, 14-Oct-2005 Section: Cadence
Cadence Encounter Tutorial

Cadence Encounter goes far beyond Silicon Ensemble. It oers a single cockpit for the entire physical implementation ow. Although some tools are run as external binaries (e.g. Nanoroute), the user never has to leave the GUI. In addition, the Common Timing Engine is integrated into Encounter, allowing for timing analysis every step of the way.
Download
This demo is based on the IIT cell library. In addition, download the following les: The The The The design conguration le: encounter.conf GDS mapping le: gds2_encounter.map SDC constraints le: nrd_05.sdc gate level netlist: nrd_05.v
(Note that you will need to edit the path to the IIT cell library in the "encounter.conf" le to match your local installation.) To prepare a design for Encounter, simply output a gate-level verilog netlist from the synthesis tool (e.g. Cadence PKS or Synopsys Design Compiler). In addition, for a timing driven ow also create a constraints le using the "write_sdc" command (in PKS or DC). Both the names of the netlist and constraint le, as well as all library les are summarized in "encounter.conf". Using a conf le is the perfect way to organize the many parts that make up a design. And the bulk of the conf le will be constant for a particular cell library.
Floorplanning
Start Encounter with the Unix command
encounter
The GUI will appear as in the following picture. To zoom in, draw a box with the right mouse button. To go back to full view, hit "f". (In this webpage, clicking on a screen shot will open the full image in a new window).
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The rst step is to import the design. Encounter uses conguration les to neatly organize the many pieces that make up a design. Do to "Design -> Import", hit "Load..." and load in the le called "encounter.conf". It should look like this:
Hit OK and the design as well as the library data is loaded. Next we need to create a oorplan. Do "Floorplan -> Specify Floorplan". Set the Core Utilization to 0.5 and the space between the core and the boundary to 30um on all sides. A utilization of 50% leaves enough room for buer insertion during optimization. Inside the 30um we will place supply rings.
Hit OK and the oorplan will look as follows:
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Next we add supply rings. Do "Floorplan -> Power Planning -> Add Rings". Set the top and bottom layer to Metal3 and set the ring width to 10um (Note:Choose 9.9um if you want a layout on the lambda grid) Finally, make the ring centered in the channel.
This will create 2 rings, for VDD and GND, around the core.
In addition to the rings, we add vertical stripes, which results in a power grid. This helps with IR-drop. Do "Floorplan -> Power Planning -> Add Stripes". Set the width to 5um, and the space from left to 100um.
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This will create vertical stripes in Metal2, 100um from the left edge and with 100um space between stripes.
Finally, now we are ready to route the power grid. Do "Route -> Sroute" and hit OK. The default values are okay. This will route all power tracks in Metal1 and will insert vias between the stripes, rings and tracks.
Placement
To place the cells, do "Place -> Place". Select "Timing Driven".
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The placement should look like this:
Now it is time for the rst timing analysis. Encounter will automatically run Trial-Route, extract RC parasitics and run static timing analysis. Do "Timing -> Timing Analysis". Disable the detailed report.
The result will be displayed in the command line window. Without any optimization, we get a dismal -2.6ns slack. But Encounter's timing closure ow will get us back to positive slack in no time.
Another nice tool is the slack histogram. It visually displays the slacks computed during timing analysis. Do "Timing -> Timing Debug -> Slack Browser" and hit okay to accept the default le name. Check "Report Non-Violating" to see all paths in the design. There are 2 distributions, a critical one, and a larger one with non-critical paths.
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Clock Tree Insertion

The rst step in timing optimization is to insert a clock tree. First we will have Encounter create a specication le. Do "Clock -> Create Clock Tree Spec" and put "buf" and "inv" as the footprints for the buer and inverter. Encounter uses footprints to up- and down-size instances of the same functionality.
One could now edit the spec le but we will accept the default. Do "Clock -> Specify Clock Tree" and accept the default le, which is the one we just created.
To create the clock tree do "Clock -> Synthesize Clock Tree" and accept the default values. After that, we can visually display the clock tree. Do "Clock -> Display -> Display Clock Tree".
Turn o the display using "Clock -> Display -> Clear". Next we can run timing optimization based on the clock tree we inserted. Do "Timing -> Optimization" and check "PostCTS".
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The result can be seen in the command window. We are down to -0.06ns slack violation.
Routing
We use "Nanoroute" to perform global and detail routing. It is an extremely powerful router and replaces the older WRoute tool. To route the design, to "Route -> Nanoroute" and hit OK.
Now we can run post-route optimization. This allows Encounter to optimize the design based on actual wires. Any modied net will automatically be re-routed by Nanoroute. To start, do "Timing -> Optimization" and select "postRoute" mode.
Now we have timing closure, with no violating path left.
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Verication and Export

The nal step is to add ller cells. These are empty cells that provide nwell continuity. Do "Place -> Filler -> Add Filler". Enter "FILL" as the cell name (in the IIT cell library this is the name of the ller cell). The value "FILLER" will be used as the prex for the instance name of each ller cell added.
After adding ller, hit "f" to redraw the window. It can be seen that the core area is completely covered with cell instances.
Encounter oers geometry violation check. Do "Verify -> Geometry" and hit OK. The result will be shown in the command line window. If there is a violation, use "Verify -> Violation Browser" to see a list of violations.
We can also check the connectivity of the design, i.e. missing or in-complete routes or oating pins. Do "Verify -> Connectivity" and hit OK. The result is shown in the command line window.
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The last step is to export the design to GDS. This is the format used by Layout Editors (e.g. Cadence Virtuoso) and IC foundries. It requires a map le, to map layer names to layer numbers. In this case we use a map le that matches Mosis layer numbers. Do "Save -> GDS", choose any name for the resulting le and select the map le.
Finally, do "Design -> Save Design" to save the entire design to disk. Then next time you run Encounter, you can do "Design -> Restore Design". Note that Encounter does not use a proprietary or binary data format.
Common Exports
These are some of the most commonly used export functions in Cadence Encounter. Note that some are only available as text commands, without an entry in the GUI. DEF: Design -> Save -> DEF Verilog: Design -> Save -> Netlist SDF: Timing -> Calculate Delay SPEF: Timing -> Extract RC LIB: Textcommand saveCharacterizedTiming TLF: Textcommand getTlfModel LEF: Textcommand generateLef
-lib
This concludes the GUI based ow of Encounter. Only a small fraction of all functionality could be shown. In addition, note that all tasks after oorplanning are typically run as batch jobs, using script les. The IIT ASIC ow includes a template script that can be used to achieve rst-time implementation success. And as a starting-point for other scripted ows.
This article comes from www.chiptalk.org http://www.chiptalk.org The URL for this article is: http://www.chiptalk.org/modules/wfsection/article.php?articleid=1
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Cadence Encounter Tutorial

Saturday 07 April 2012 12:45 PM

Hit OK and the oorplan will look as follows:

Saturday 07 April 2012 12:45 PM

Saturday 07 April 2012 12:45 PM

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The placement should look like this:

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Clock Tree Insertion

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Now we have timing closure, with no violating path left.

Saturday 07 April 2012 12:45 PM

Verication and Export

Saturday 07 April 2012 12:45 PM

Copyright (c) 2012 by www.chiptalk.org

Saturday 07 April 2012 12:45 PM

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