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CONFIDENTIAL

EE/OCT 2010/ECE351

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE DATE TIME

DIGITAL SYSTEMS I ECE351 OCTOBER 2010 3 HOURS

INSTRUCTIONS TO CANDIDATES 1. 2. 3. This question paper consists of five (5) questions. Answer ALL questions in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) ii) the Question Paper an Answer Booklet-provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO


This examination paper consists of 9 printed pages
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CONFIDENTIAL QUESTION 1 a) Answer the following question: i)

EE/OCT 2010/ECE351

Convert FED.CA16 into equivalent octal. (2 marks) Convert 0101 0111 0011 01 00BCD into equivalent hexadecimal. (2 marks)

ii)

iii)

Perform the arithmetic operation of 405.28 - 378 in octal number system (2 marks)

iv)

Perform the multiplication of 101102 and 11.012 in binary number system. (2 marks)

b)

Identify the equivalent octal number of each of the following signed binary number if the numbers are stored using 2's compliment system. i) ii) 11100101002 011001012 (4 marks)

c)

Answer the following question: i) Perform the operations of 8-bit 2's complement number of A + B and A - B for two binary numbers A= 011110002 and B=000101112. State the answers in decimal. (4 marks) Produce the equivalent hexadecimal number of the gray-coded number 10101101 gray. (4 marks)

ii)

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CONFIDENTIAL QUESTION 2 a) Answer the following question: i)

EE/OCT2010/ECE351

State TWO (2) methods that can be used to simplify Boolean expressions. (2 marks)

ii)

Produce the truth table for the expression F(A,B,C)

= AC + AB + B. (3 marks)

b)

Given F(A, B,C) = AB + C. Draw a minimal circuit using NAND gates ONLY. (4 marks)

c)

For the circuit shown in Figure Q2c i) ii) iii) Determine the output expression F(A,B,C). Simplify the output expression F(A,B,C) using K-Map method.

r>
B

>-T3> 5> ^o-J


Figure Q2c

F(A,B,C)

(6 marks) d) For ADC clock frequency of 500 Hz, find the full scale conversion time tc for: i) 5-bit Successive-Approximation ADC. ii) 5-bit digital ramp ADC. (5 marks)

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CONFIDENTIAL QUESTION 3 a)

EE/OCT 2010/ECE351

List TWO(2) types of adder and tabulate their truthtable respectively. Write the minterm function for each of truthtable output. (3 marks) Draw an 8-bit parallel adder by using 4-bit parallel adder as shown in Figure Q3b.
B A 1 A

b)

B3

B2

B1

Bo

A3

A2

A1

Ao

4 bit p a r a l l e l A d d e r

ln

c
0 3 2 1 ^0

'

''

''

'

"

~Y~

I Figure Q3b (2 marks) c) The inputs of the multiplier are two 2-bit numbers A1A0 and B1B0 and the product output are: Po = A0B0 Pi = AiBo+AoBi P2 = Carry out of Pi + A1B1 P3 = Carry out of P2

i)

Produce the truth table for a 2-bit multiplier and find the minterm function of each product output. (5 marks) Show the construction of a 2-bit multiplier using full-adders and AND gates. (3 marks)

ii)

iii)

Verify the circuit in part c(ii) by determining the logic states of each input and output terminals if A=3i 0 and B=2i0. (2 marks)

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CONFIDENTIAL d)

EE/OCT2010/ECE351

Based on Figure Q3d, find the values for l0, li, I2 ,U and the SOP expression of F(W,X,Y,Z). +5V

F (W,X,Y,Z)

X-[>

(5 marks)

QUESTION 4 a) Define an encoder and state an example of its application. Draw a typical block diagram for a decimal-to-BCD encoder. (4 marks) Answer the following question: i) Produce the truth table for an octal-to-binary encoder. Hence, draw the logic circuit to represent the encoder. (4 marks) Implement the following function using ONE(1) 8-input MULTIPLEXER.

b)

ii)

F(A, B,C) = AB + ABC + ABC


(2 marks)

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CONFIDENTIAL c)

EE/OCT 2010/ECE351

Figure Q4c shows the JK flip-flop with asynchronous inputs preset and clear, i) Complete the truth table given in Table Q4c. Assume Q is initially '1'

J
CLK" >
K

PRE

CLRQ

Figure Q4c

Table Q4c CLK 1 2 3 4 PRE 0 1 1 1 CLR 1 1 0 1 J 0 1 1 1 K 1 1 1 0 (4 marks) ii) Produce the truth table for the active high JK flip-flop and draw to show how this JK flip-flop can be converted into a T flip-flop. (2 marks)

Q
1

Qn+i

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CONFIDENTIAL d)

EE/OCT 2010/ECE351

Figure Q4d shows a T flip flop with active low Preset and Clear function. Complete the Table Q4d for the output Q of this flip-flop. Assume the output Q is initially zero.

PRE

CLK-C>

Figure Q4d

Table Q4d
Present state CLK 1 2 3 4 PRE 0 1 1 1 CLR 1 1 0 0 T 0 0 1 1 Qn 0 Qn Next state
Qn+1

Q n +i

(4 marks)

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CONFIDENTIAL QUESTION 5 a)

EE/OCT 2010/ECE351

What is the difference between Ring counter and Johnson counter. Draw a logic circuit of MOD 3 synchronous Ring counter using D-flip flop with positive edge triggered clock that has the counting sequence as shown in Figure Q5a.

c
b) PRE

100> 001 >010


Figure Q5a (4 marks)

For the sequential circuit in Figure Q5b(i), complete the timing diagram for the sequential circuit based on timing diagram in Figure Q5b(ii).

CLK CLR Figure Q5b(i)

CLK

PRE

CLR

Qo

Figure Q5b(ii) (6 marks)


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CONFIDENTIAL c)

EE/OCT 2010/ECE351

Table Q5c shows the state table of a synchronous counter which is designed using active high JK-Flip flops with negative triggered clock. Draw the transition state diagram from the data shown in the table and determine the counting sequence of the counter. Produce the excitation table for active high JK-flip flops. Hence complete the state table shown in Table Q5c. Simplify the output equations and draw the counter circuit.

Table Q5c PRESENT STATE C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 NEXT STATE C B'A' 1 0 0 1 0 0 1 0 1 0 0 0 " Jc Kc


JB KB JA KA

1 1 0 1 1 0 0 1 0 1 1 0 (10 marks)

END OF QUESTION PAPER

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