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From Wikipedia, the free encyclopedia This article does not cite any references or sources. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. (October 2007) In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar. Although adders can be constructed for many numerical representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an addersubtractor. Other signed number representations require a more complex adder.

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1 Half adder 2 Full adder 3 More complex adders o 3.1 Ripple carry adder o 3.2 Carry-lookahead adders o 3.3 Lookahead carry unit 4 Multiple Bit Addition 5Applications -1 IC implementation -2 compressors

Example half adder logic diagram The half adder is an example of a simple, functional digital circuit built from two logic gates. A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. Half adders cannot be used compositely, given their incapacity for a carry-in bit.

Schematic symbol for a 1-bit full adder with Cin and Cout drawn on sides of block to emphasize their use in a multi-bit adder A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in (in theory from a past addition). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a two-bit output sum typically represented by the signals Cout and S, where . The one-bit full adder's truth table is: Inputs Outputs

A B Cin Cout 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1

S 0 1 1 0 1 0 0 1

Example full adder logic diagram; the AND gates and the OR gate can be replaced with NAND gates for the same results A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and .

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as .

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Cout could be made the three-bit majority function of A, B, and Ci.

[edit] Ripple carry adder

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder. The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 3 (for carry propagation in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays.

4-bit adder with carry lookahead To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders. They work by creating two signals (P and G) for each bit position, based on if a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry-lookahead architectures are the Manchester carry chain, BrentKung adder, and the KoggeStone adder. Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block. Other adder designs include the carry-save adder, carry-select adder, conditional-sum adder, carry-skip adder, and carry-complete adder.

A 64-bit adder By combining multiple carry lookahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.

In the previous section we said how we could add two one-bit binary numbers, taking into account any carried digits from the previous binary order of magnitude (BOOM) and any digits carried to the next BOOM. By concatenating (stringing together) these one-bit adders, we can make an adder to add an arbitrary length binary number. To do this, connect the carry in of the first stage to ground, as no bits are carried in from before the least significant bit. Then connect the carry out of the first stage to the carry in of the next, and so on for as many stages as you like. Below is the layout for a 4-bit adder:

Bear in mind that the result will only be complete when the carry output have registered in each of the stages in turn. This ripple effect is why this kind of adder is called a ripple carry adder. This takes a small amount of time, and for large (32-bit or more) adders it may take several hundred nanoseconds, which may be a problem if high speed is needed. There are much faster adders that can be made that don't have a ripple effect, such as carry lookahead adders.

The 4008 IC is a 4-bit full adder, which can in turn be concatenated with others to provide any length of number.

We can view a full adder as a 3:2 lossy compressor: it sums three one-bit inputs, and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs. Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.

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