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Example half adder logic diagram The half adder is an example of a simple, functional digital circuit built from two logic gates. A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. Half adders cannot be used compositely, given their incapacity for a carry-in bit.

A B Cin Cout 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1

S 0 1 1 0 1 0 0 1

Example full adder logic diagram; the AND gates and the OR gate can be replaced with NAND gates for the same results A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and .

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as .

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Cout could be made the three-bit majority function of A, B, and Ci.

## 4-bit adder with logic gates shown

A 64-bit adder By combining multiple carry lookahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.

In the previous section we said how we could add two one-bit binary numbers, taking into account any carried digits from the previous binary order of magnitude (BOOM) and any digits carried to the next BOOM. By concatenating (stringing together) these one-bit adders, we can make an adder to add an arbitrary length binary number. To do this, connect the carry in of the first stage to ground, as no bits are carried in from before the least significant bit. Then connect the carry out of the first stage to the carry in of the next, and so on for as many stages as you like. Below is the layout for a 4-bit adder:

Bear in mind that the result will only be complete when the carry output have registered in each of the stages in turn. This ripple effect is why this kind of adder is called a ripple carry adder. This takes a small amount of time, and for large (32-bit or more) adders it may take several hundred nanoseconds, which may be a problem if high speed is needed. There are much faster adders that can be made that don't have a ripple effect, such as carry lookahead adders.

## Applications  IC Implementation

The 4008 IC is a 4-bit full adder, which can in turn be concatenated with others to provide any length of number.

##  3:2 compressors

We can view a full adder as a 3:2 lossy compressor: it sums three one-bit inputs, and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs. Such compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.