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Code No: A5706 Jawaharlal Nehru Technological University Hyderabad M. Tech I-Semester Supplementary Examinations September-2009 CPLD & FPGA ARCHITECTURE & APPLICATIONS (VLSI System Design) Time : 3 Hours Max.Marks: 60 Answer Any Five Questions All Questions Carry Equal Marks ---1.a] b] c] What are the various interconnect technologies used for the purpose of programming PLPS? Describe each one them. Determine the size of PROM required to implant a i) 16 to 1 Mux ii) 4-bit binary adder. Compare in terms of speed and in system programmability of lattice PLSIs architecture and CYPRES FLASH 370. Draw a basic block diagram of Xilinx Spartan FPGA and explain briefly about CLB, LUT of their FPGA. State how a CPLD such as Altuas MAX 7000s deflect from a density PAL of GAL. We have two 2-bit binary number A1A0 and B1B0. Design a PLA to implant a magnitude comparator to produce output for equal to, not equal to, less than and greater that A1A0 with respect to B1B0. How does the architecture of a typical FPGA device differ from that of a CPLD? In what way does the architecture affect the timing performance in the two cases?
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What are the possible ways of implementation programming links at the single length interconnects and long interconnects in the arrays. List out the characteristics that describe a CPLD of FPGA. List the links to be programmed for a synchronous counter of 4-bit using CLBs of XC4000. Design an FSM which detects 1011 sequence using one hot encoding and realize it on PAL. Design a system which counts number of 0s in a register A using shift operation. Draw ASM chart for the design of control logic and implant the same on PLA. Draw the data path diagram of the above design. Design a parallel adder unit with carry look ahead principle. Write HDL code to be simulated using FPGA advantage. Show the simulated output that is excepted. Contd -2-

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Code No: A5706 8.

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Write short notes on: a) Design flow for FPGA implementation. b) Meta stability. --ooOoo--

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