SIGNAL PROCESSING LAB

I Year I Sem M.Tech.(DECS)

1. Basic Operations on Signals, Generation of Various Signals and finding its FFT. 2. 3. 4. 5. Program to verify Decimation and Interpolation of a given Sequences. Program to Convert CD data into DVD data. Generation of Dual Tone Multiple Frequency (DTMF) Signals. Plot the Periodogram of a Noisy Signal and estimate Psd using Periodogram and Modified Periodogram methods. 6. 7. 8. 9. Estimation of Power Spectrum using Bartlett and Welch methods. Estimation of Power Spectrum using Blackman-Tukey Methods. Verification of Autocorrelation Theorem. Parametric methods (Yule- Walker and Burg) of power Spectrum Estimation. 10. Estimation of data series using Nth order Forward Predictor and comparing to the Original Signal. 11. 12. Design of LPC filter using Levinson-Durbin Algorithm. Computation of Reflection Coefficients using Schur Algorithm.

ADVANCED COMMUNICATIONS LABORATORY

I Year II Sem M.Tech.(DECS)
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. AM,FM, Modulation and Demodulation. QPSK Modulation and Demodulation. Costas loop for Carrier recovery. TAMA (Time Division Multiple Access) technique. CDMA (Code Division Multiple Access) technique. Effect of Sampling and Quantization of Digital Image. Various Transforms (Fourier, Walsh, Hadamad). Enhancement technique in spatial frequency domain. Point line and edge detection techniques using derivative operators. Color image enhancement techniques. Echo cancellation in speech signal. Filters using LMS Algorithm.

HDL LABORATORY
I Year I Sem M.Tech.(DECS)
1.

Simulation and Verification of various gates like AND, OR, EXOR, NAND, NOR, and EXNOR.

2.

Design and simulate the HALF ADDER, SERIAL BINARY ADDER, MULTIPRECISION ADDER USING FULL ADDERS.

3.

Simulation and verification of DECODER(2X4), (4X16 using 2X4 DECODER) MULTIPLEXERS (8X1,16X1) PRIORITY ENCODER (4X2) with a VALID bit.
Using various modeling styles (Structural, Behavioral, and Data Flow modeling).

4.

Modeling of D, J-K, T Flip-flops with synchronous and asynchronous reset.

5.

Design and simulate of 4-bit COUNTER RING COUNTER, JOHNSON COUNTER UP- DOWN COUNTER

6.

Design a N-bit REGISTRARS performing SERIAL IN SERIAL OUT SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT PARALLEL IN PARALLEL OUT 7. Design MEALY AND MOORE FINITE STATE MACHINES for SEQUENCE DETECTOR-OVERLAPPING AND NONOVERALAPPING 8. 9. BUS COUNTER Design the hardware for MULTIPLICATION AND DIVISION(for 4 bit operands). 10.Design a ALU performing operations ADD,SUB, AND, OR,1s 2s COMPLEMENT, MULTIPLICATION AND DIVISION