VLSI Design

A Courseon

DesignofDigitalVLSISystems&Circuits

By PragnanChakravorty
AssociateProfessor&H.O.D(E&TC),CIET,Raipur Associate Professor & H O D (E&TC) CIET Raipur
M.Tech(IITKharagpur),MIEEE MemberIEEE(USA): Communication.Soc, MicrowaveTheoryandTechniquesSoc, Antenna&WavePropagation.Soc Antenna & Wave Propagation. Soc IEEEStandardsSoc.

INTRODUCTIONTOINTEGRATEDCIRCUITS

HowisaVLSICircuitDifferent?
Unlike conventional electronic circuits, Transistors in a VLSI/ Integrated Circuits are carved / sculpted over a singlewafer (Monolith) of semiconductor almost sculpted, semiconductor, concatenated so as to reduce the lengths of interconnects. The interconnects are made as the final layer of fabrication known as metallization layer. Metallizations are now done using polysilicon. The ability to manipulate the area/volume occupied by the carved transistors and the interconnects between them renders a tremendous scope of device miniaturization /scaling and a very large scale integration over a small space.

SSI,MSI,LSI,VLSI,ULSI:
There has been a tremendous rise in the number of devices integrated into a single chip (conventionally 10mm x 10mm area chip) in the past few decades as a result the scale of device integration has been categorized as follows: Device Integration Table: S.No 1 2 3 4 5 Category SmallScaleIntegration(SSI) Medium ScaleIntegration(MSI) Large ScaleIntegration(LSI) VeryLarge ScaleIntegration(VLSI) Year 1964 1967 1972 1978 Numberof Devices D i 05to 20 20to 200 200to 2000 2000to 20000 20000to ?

UltraLarge ScaleIntegration(ULSI) 1989

MoorsLaw:
In 1965, a Caltech Professor, Gordon Moore observed that plotting the number of transistors that can be most economically manufactured on a chip gives a straight line on a semi logarithmic scale. At the time, he found transistor count doubling every 18 months. This observation has been called Moores Law and has become a selffulfilling prophecy
Moors graph compared with actuality

Transistor Count

Date of Introduction

AdvantagesofHighScaleIntegration/DeviceMiniaturization:
The most important message here is that the logic complexity per chip has been p g g p yp p (and still is) increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides: Less area/volume and therefore, compactness Less power consumption Less testing requirements at system level Higher reliability mainly due to improved on chip interconnects reliability, onchip Higher speed, due to significantly reduced interconnection length Significant cost savings due to batch processing / g y p g Lesser fabrication error /Higher yield due to batch processing

VLSIDesignFlow
A VLSI system is a multi domain system where designs need to be carried out from behavioral levels to h i l layout l l With i each d b h i l l l t physical l t levels. in h domain th d i i the design can b be categorized into certain levels of abstraction and then the designs need to follow certain hierarchically categorized steps. DomainsofDesign:Domainsaredifferentdistinctcategoriesoverwhichany engineeringsystemspans.Therecanbethreesuchmajordomainsstatedbelow: Behavioraldomain:Whichdescribesthebehaviorofthesystemforexamplethe transmittingbehaviorofatransmittersystem. Structuraldomain:Whichdescribesthestructureofthesystemforexamplewhere andhowarethevariousamplifiers,oscillators,filtersetcarestructuredinthe transmittersystem. Geometricallayoutdomain.Describethephysicallayoutorplacementofdifferent componentsordevicesinasystemforexampletheplacementandconnections betweenvarioustransistors,RLCs,inamplifiersoscillatorsfiltersetc. b t i t it RLC i lifi ill t filt t

GeneralizedDesignFlow

TheYChart
The Ychart (first introduced by D. Gajski) shown in Fig. illustrates a design flow for most l i chips, using d i activities on th t logic hi i design ti iti three diff different axes (d t (domains) which i ) hi h resemble the letter Y.

LevelsofAbstraction
Domainscanfurtherbehierarchicallydividedintodifferentlevelsofdesign abstraction.Classically,thesehaveincludedthefollowing b t ti Cl i ll th h i l d d th f ll i fordigitalchips: Architecturalorfunctionallevel LogicorRegisterTransferLevel(RTL) Logic or Register Transfer Level (RTL) Circuitlevel The relationship between description domains and levels of abstraction is elegantly shown by the GajskiKuhn Y chart in Figure. Gajski Kuhn In this diagram, the three radial lines represent the behavioral, structural, and physical domains. p y The annular regions between concentric circles show different levels of abstraction.

DesignHierarchy
The levels of abstraction are generic divisions which can map designs of one domain into i t another. D th Domain specific di i i i ifi divisions of th l l of abstractions are called f the levels f b t ti ll d hierarchical divisions. The hierarchical design approach reduces the design complexity by dividing the large system into several submodules

Hierarchicaldivisionsinstructuraldomainofa4bitadder

ConceptsofRegularity,ModularityandLocality
Though the design complexity reduces down with hierarchical submodules, such sub module th b d l themselves must h l t have some consonance and i t it with each other d integrity ith h th so as to further simplify the design process and make them effective. Such consonance between the submodules are brought in by the following concepts: Regularity: Regularity is the division of the hierarchy into a set of similar building blocks (modules/submodules). Regularity can exist at all levels of the design hierarchy. At the circuit level, uniformly sized transistors can be used, while at the gate level, a finite library of fixedheight, variablelength logic gates can be used Modularity: Modularity states that modules/submodules have welldefined functions and interfaces. If modules/submodules are wellformed, the interaction with other modules/submodules can be well characterized. Locality: Locality is the localized composition of components with in a module/sub module so that they do not interact with other modules/submodules. Therefore internals of a module/submodules are unimportant to other modules/submodules. So, t S external i t f l interfaces d not affect i t do t ff t internal i t f l interfaces and visaversa. d i

VLSIDesignStyles/Methods
The VLSI design styles or methods depend upon the target IC platform or standard. Depending upon the IC standards the design style vary and have platform specific p g p g y y p p limitations and flexibility or advantages and disadvantages.

OverviewVLSIDesignStyles/Standards/Platforms

ComplexProgrammableLogicDevice(CPLD)
CPLD is a single device with multiple simple programmable logic devices(SPLDs) such as P Programmable A bl Array L i (PLA) or G Logic Generic A i Array L i (GLA) PAL and GAL are Logic (GLA). PALs d GALs based on sum of products (SOP) architecture with a programmable AND array and a fixed OR array
PLA/GLACKTView

CPLDBlockDiagram

PLA/GLABlockDiagram

FieldProgrammableGateArray(FPGA)Design
A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs) and programmable interconnect structures The (CLBs), structures. programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. General and detailed blocks of an FPGA are shown below.

TheLUTisa digitalmemory di i l thatstoresthe truthtableof theBoolean function. XILINXModelXC2000

Configurable Logic Block (CLB): A simple CLB (model XC2000 from XILINX) is shown above where it consists of four signal input terminals (A, B, C, D), a clock signal terminal, terminal userprogrammable multiplexers an SRlatch and a lookup table (LUT) multiplexers, SRlatch, (LUT). The LUT is a digital memory that stores the truth table of the Boolean function. It can generate any function of up to four variables or any two functions of three variables

GateArray/SeaofGatesDesign
While the design implementation of the FPGA chip is done with user programming, that of the gate array is done with metal mask design and processing. Gate array implementation requires a twostep manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array

StandardCellBasedDesign
In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells y yp y y including inverters, NAND gates, NOR gates, complex AOI, OAI gates, Dlatches, and flipflops. It is almost a full custom design but for the predesigned cells which cant be customized.

FullCustomDesign
In full custom design the customization starts at transistor level itself. Therefore different cells can be customized and optimized according to the various design specifications and constraints. Full custom designs are usually prevalent with analog designs and not digital.

GeneralPurposeIC&ASSPSystemDesign
System level digital designs are often practically done by programming general y g g p y y p g g g purpose ICs. These general purpose ICs are programmed using high level languages and are different from the ASICs described so far. These ICs include various microprocessors microcontrollers, MIPS , RISC and SISC processors. Application Specific System Processors(ASSPs) are also a kind of dedicated general purpose processors such as DSP processors which are programmed using high level languages.

DESIGN&FABRICATIONASPECTS
of StandardCellBasedDesignStyle

BasicStepsofFabricationProcess
Each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, a l l layer must b patterned b f t be tt d before th next the t layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography/Photolithography. Since each g p y/ g p y layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask Figure at the right shows simplified process sequence for fabrication of the nwell CMOS integrated circuit with a single polysilicon layer, showing only major fabrication steps.

LithographicStepsofPatterning

SetofMasksforPatterning
The crosssection view is of an inverter

In a CMOS circuit fabrication, the hypothetical set of six masks: n h h l f k well, polysilicon, n+ diffusion, p+ diffusion, contacts, and metal. Masks specify p y where the components will be manufactured on the chip. Figure shows a top view of the six masks.

DifferentDevelopmentStagesinCMOSFabrication

Fabrication ofNMOSFET &PMOSFET

FabricationofNWell Layingoutinterconnectsandthick insulatingoxides

2D & 3D Representations of NMOS & PMOS in CMOS Process

LayoutDesignRules
The physical mask layout of any circuit to be manufactured using a particular process must conform to a set of geometric constraints or rules, which are generally called g , g y layout design rules. These rules usually specify the minimum allowable line widths for physical objects onchip such as metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features. The main objective of design rules is to achieve a high overall yield and reliability while using the smallest possible silicon area, for any circuit to be manufactured with a particular process. The design rules are usually described in two ways : Micron rules: in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or, Lambda rules: These rules specify the layout constraints in terms of a single parameter (which is generally half the channel length and equal to the thickness of p y polysilicon layer) and, thus, allow linear, proportional scaling of all geometrical y ) , , , p p g g constraints. The design rules are usually given by Metal Oxide Silicon Implementation Service (MOSIS established in 1981).

BasicLambdaDesignRules

StickDiagram Sti k Di
As layout is timeconsuming, designers need fast ways to plan cells and estimate area before committing to a full layout. Stick diagrams are easy to draw because they do not need to be drawn to scale It is easy to estimate the area of a layout from the scale. corresponding stick diagram even though the diagram is not to scale. As an example stick diagrams of an inverter and 3 I/P NAND gate are shown below

MOSISDesignRule(SampleSet)
Rulenumber R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 Description Minimumactiveareawidth Minimumactiveareaspacing Mi i ti i Minimumpolywidth Minimumpolyspacing Minimumgateextensionofpolyoveractive Minimumpolyactiveedgespacing Mi i l ti d i (polyoutsideactivearea) Minimumpolyactiveedgespacing (polyinsideactivearea) Minimummetalwidth Mi i t l idth Minimummetalspacing Polycontactsize Minimumpolycontactspacing Minimumpolycontacttopolyedgespacing Minim m pol contact to pol ed e spacin Minimumpolycontacttometaledgespacing Minimumpolycontacttoactiveedgespacing Activecontactsize Minimumactivecontactspacing Minimum active contact spacing (onthesameactiveregion) Minimumactivecontacttoactiveedgespacing Minimumactivecontacttometaledgespacing Minimumactivecontacttopolyedgespacing Minimum active contact to poly edge spacing Minimumactivecontactspacing (ondifferentactiveregions) LRule 3L 3L 3L 2L 2L 2L 1L 1L 3L 3L 3L 3L 2L 2L 1L 1L 1L 3L 2L 2L 2L 1L 1L 3L 3L 6L

Illustration of some of the typical MOSIS layout design rules listed above

NMOS&PMOSTransistorsasSwitches(BinaryLogicGenerators)

NMOSTransistor

PMOSTransistor

An NMOS transistor is built with a ptype body and has regions of ntype p type n type semiconductor adjacent to the gate called the source and drain. They are physically equivalent and for now we will regard them as interchangeable. The body is typically g grounded. A PMOS transistor is just the opposite, consisting of ptype source and j pp g p yp drain regions with an ntype body. In a CMOS technology with both flavors of transistors, the substrate is either ntype or ptype. The other flavor of transistor must be built in a special well in which dopant atoms have been added to form the body of the opposite type.

Transistor in OFF state Considering NMOS transistor, the body is generally grounded so the pn junctions of the source and drain to body are reversebiased. If the gate is also grounded, no current flows through the reversebiased junctions. Hence, we say the transistor is OFF. Just the opposite happens with PMOS transistors. Transistor in ON state When the gate voltage is raised, it creates an electric field that starts to attract free electrons to the underside of the SiSiO2 interface. If the voltage is raised enough, the electrons outnumber the holes and a thin region under the gate called the channel i i h l is inverted to act as an ntype semiconductor. Hence, a conducting path of d i d d i h f electron carriers is formed from source to drain and current can flow. We say the transistor is ON. Similarly in case of PMOS the conditions are reversed

MOSTransistorsasSwitches

LayoutExamples:
CMOS Inverter

NOR2GATE

CircuitDiagramLayoutDiagram

NAND2GATE

CircuitDiagramLayoutDiagram

FullAdder

CircuitDiagram

LayoutDiagram

CalculationofCapacitances&Resistances
Capacitances and resistances are the most vital factors governing the performance of a digital VLSI circuit Perhaps the most significant aspect of a digital circuit is its circuit. speed of operation which can be determined through delay calculations. Resistances and capacitances in an IC form RC pairs and cause various delays in the signal flow. Resistances and capacitances in ICs can be categorized into two: Intrinsic RCs: Those resistances and capacitances which occur inside the transistors Extrinsic RCs: The resistances and capacitances which occur outside the transistors. i.e. those which are contributed from the interconnects. Resistance & Capacitance Calculation through RC Delay Model Effective resistance in transistors: A unit NMOS transistor is defined to have effective resistance R. The size of the unit transistor is arbitrary but conventionally refers to a transistor with minimum length and minimum contacted diffusion width (i e 4/2) Alternatively it may refer to the (i.e., 4/2). Alternatively, width of the NMOS transistor in a minimumsized inverter in a standard cell library. An NMOS transistor of k times unit width has resistance R/k because it delivers k times as much current A unit PMOS transistor has greater resistance generally in current. resistance, the range of 2R because of its lower mobility. R is typically on the order of 10 k for a unit transistor.

Effective capacitance in transistors: Each transistor also has gate and diffusion capacitance. We define C to be the gate capacitance of a unit transistor of either flavor. A transistor of k times unit width has capacitance kC Diffusion capacitance depends on the size of the source/drain region Using kC. region. the approximations we assume the contacted source or drain of a unit transistor to also have capacitance of about C. Wider transistors have proportionally greater diffusion capacitance. Increasing channel length increases gate capacitance proportionally but does not affect diffusion capacitance. Although capacitances have a nonlinear voltage dependence, we use a single average value. We roughly estimate C for a minimum length transistor to be 1 fF/micron of width. In a 65 nm process with a unit transistor being 0.1 micron wide C is thus about 0 1 fF wide, 0.1 fF.

EquivalentRCCircuitRepresentations

EquivalentCircuitforanInverter

Generalized model for MOSFET capacitances: The capacitances associated with a MOSFET are shown in Fig as lumped elements between the device terminals. Based on their physical origins, the device capacitances can be classified into two major groups: (1) oxide related capacitances and (2) junction oxiderelated capacitances. The gateoxiderelated capacitances are Cgd (gatetodrain capacitance), Cgs (gatetosource capacitance), and Cgb (gatetosubstrate capacitance). Notice that in reality, the gatetochannel capacitance is distributed and voltage dependent. Consequently, all of the oxiderelated capacitances described here change with the bias conditions of the transistor.

Effective resistance in interconnects: The resistance of a metal or polysilicon line also have a profound influence on the signal propagation delay over that line. The resistance of a line depends on the type of material used (polysilicon, aluminum, gold, ) (polysilicon aluminum gold ...), the dimensions of the line and finally the number and finally, locations of the contacts on that line. Consider the interconnection line shown in Fig. The total resistance in the indicated current direction can be found as

Where represents the characteristic resistivity of the interconnect material, and Rsheet represents the sheet resistivity of the line, in (ohm/square). For a typical polysilicon layer, the sheet resistivity is between 2040 ohm/square, whereas the sheet resistivity of silicide is about 2 ohm/square. 2 4 ohm/square Using the formula given above we can estimate the total parasitic resistance above, of a wire segment based on its geometry. Typical metalpoly and metaldiffusion contact resistance values are between 2030 ohms, while typical via resistance is about 0.3 ohms.

Effective capacitance in interconnects: A set of simple formulas developed by Yuan and Trick in the early 1980s can be used to estimate the capacitance of the interconnect structures in which fringing fields complicate the effective capacitance calculation The following two cases are considered for two different calculation. ranges of line width (w).

These formulas permit the accurate approximation of the parasitic capacitance values to within 10% error, even for very small values of (t/h).

Power Dissipation Static CMOS gates are very powerefficient because they dissipate nearly zero power while idle. For much of the history of CMOS design, power was a secondary consideration behind speed and area for many chips. As transistor counts and clock frequencies have increased, power consumption has skyrocketed and now is a primary design constraint We begin by reviewing constraint. some definitions. The instantaneous power P(t) drawn from the power supply is proportional to the supply current iDD(t) and the supply voltage VDD

TheenergyconsumedoversometimeintervalTistheintegraloftheinstantaneouspower

Static Power Dissipation Considering the static CMOS inverter shown in Figure 4 26 if the input = '0 ' the associated 4.26, 0, nMOS transistor is OFF and the pMOS transistor is ON. The output voltage is VDD or logic '1.'When the input = '1,' the associated nMOS transistor is ON and the pMOS transistor is OFF. The output voltage is 0 volts (GND). Note that one of the transistors is always OFF when the gate is in either of these logic states. Ideally, no current flows through the OFF transistor so the power dissipation is zero when the circuit is quiescent, i.e., when no transistors are switching. Zero quiescent power dissipation is a principle advantage of CMOS over competing transistor technologies. However, secondary effects including sub threshold conduction, tunneling, and leakage lead to small amounts of static current flowing through the OFF transistor. Assuming the leakage current is constant so instantaneous and average power are the same, the static power dissipation is the evaluation product of total leakage current and the supply voltage.

Dynamic Power Dissipation

Combinational&SequentialLogicDesign WithVHDL With VHDL

What is VHDL?
VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits) It is a hardware description language that can be Circuits). used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language + concurrent language + netlist language + timing specifications + waveform generation language => VHDL Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also be generated using th same constructs. All th above constructs may b combined t provide a i the t t the b t t be bi d to id comprehensive description of the system in a single model

Use of VHDL in digital logic design VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure while the external view specifies the interface of the structure, device through which it communicates with the other models in its environment. The Figure drawn below shows the hardware device and the corresponding software model.

What is an entity? Entity is an abstraction level of the hardware device in cosideration. The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models. For example, a device modeled at a higher level of abstraction may not have a clock as one of its inputs, since the clock may not have been used in the description. Also the data transfer at the interface may be treated in terms of say, integer values, instead of logical values. In VHDL, each device model is treated as a distinct representation of a unique device, called an entity .

Basic Terminologies The digital system can be as simple as a logic gate or as complex as a complete electronic system. A hardware abstraction of this digital system is called an entity. An entity X, when used in another entity Y, becomes a component for the entity Y. Therefore, a component is also an entity, depending on the level at which you are trying to model. To describe an entity, VHDL provides five different types of primary constructs, called design units. Th are i They 1. Entity declaration 2. Architecture body y 3. Configuration declaration 4. Package declaration 5. Package body An entity is modeled using an entity declaration and at least one architecture body. The entity declaration describes the external view of the entity, for example, the input and output signal names. The architecture body contains the internal description of the entity, for example, as a set of interconnected components that represents the structure of the entity, or as a set of concurrent or sequential statements that represents the behavior of the entity. Each style of representation can be specified in a different architecture body or mixed within a single architecture body .Figure given below shows an entity and its model Figure model.

A configuration declaration is used to create a configuration for an entity It specifies the entity. binding of one architecture body from the many architecture bodies that may be associated with the entity. It may also specify the bindings of components used in the selected architecture body to other entities. An entity may have any number of different configurations. A package declaration encapsulates a set of related declarations such as type declarations, subtype declarations, and subprogram declarations that can be shared across two or more design units. A package body contains the definitions of subprograms declared in a package declaration.

Once an entity has been modeled, it needs to be validated by a VHDL system. A typical VHDL system consists of an analyzer and a simulator. The analyzer reads in one or more design units contained in a single file and compiles them into a design library after validating the syntax and performing some static semantic checks The design library is a place in the host checks. environment (that is, the environment that supports the VHDL system) where compiled design units are stored. The simulator simulates an entity, represented by an entityarchitecture pair or by a configuration, by reading in its compiled description from the design library and then performing the following steps: 1. Elaboration 2. 2 Initialization 3. Simulation EXAMPLES Entity Declaration: The entity declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment.

HereisanexampleofanentitydeclarationforthehalfaddercircuitshowninFigabove entityHALF_ADDERis y port(A,B:in BIT;SUM,CARRY:out BIT); endHALF_ADDER; Thisisacommentline. The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies input port), and two output ports, SUM and CARRY (the mode out specifies output port). BIT is a predefined type of the language; it is an enumeration type containing the character literals '0' and '1'. The port types for this entity have been specified to be of type BIT, which means that the ports can take the values, '0' or '1'. Architecture Body: The entity declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment. architectureHA_Archbody ofHALF_ADDERis begin SUM<=Axor Bafter 8ns; CARRY<=AandBafter 4ns; end HA_Archbody;

Here a dataflow model is used where the HALF_ADDER is described using two concurrent signal assignment. In a signal assignment statement, the symbol <= implies an assignment of a value to a signal. The value of the expression on the righthandside of the statement is computed and is assigned to the signal on the left hand side called the target signal A lefthandside, signal. concurrent signal assignment statement is executed only when any signal used in the expression on the righthandside has an event on it, that is, the value for the signal changes. Configuration Declaration is used to select one of the possibly many architecture bodies that an entity may have, and to bind components, used to represent structure in that architecture body, to entities represented by an entityarchitecture pair or by a configuration, that reside in a design library Consider the following configuration declaration for the HALF ADDER entity library. HALF_ADDER entity.

The first statement is a library context clause that makes the library names CMOS_LIB and MY_LIB visible within the configuration declaration. The name of the configuration is HA_BINDING, HA BINDING and it specifies a configuration for the HALF ADDER entity The next statement HALF_ADDER entity. specifies that the architecture body HA_STRUCTURE is selected for this configuration. Since this architecture body contains two component instantiations, two component bindings are required.

The first statement (for X1: . . . end for) binds the component instantiation, with label X1, to an entity represented by the entityarchitecture pair, XOR_GATE entity declaration and the DATAFLOW architecture body, that resides in the CMOS_LIB design library. Similarly, component instantiation A1 is bound to a configuration of an entity defined by the configuration declaration, with name AND_CONFIG, residing in the MY_LIB design library. Package Declaration: A package declaration is used to store a set of common declarations like components, types, procedures, and functions. These declarations can then be imported into other design units using a context clause. Here is an example of a package declaration.

The name of the package declared is EXAMPLE_PACK. It contains type, component, constant, and function declarations. Notice that the behavior of the function INT2BIT_VEC does not appear in the package declaration; only the function interface appears The definition or body appears. of the function appears in a package body

Package Body: A package body is primarily used to store the definitions of functions and procedures that were declared in the corresponding package declaration, and also the complete constant declarations for any deferred constants that appear in the package p y pp p g declaration. Therefore, a package body is always associated with a package declaration; furthermore, a package declaration can have at most one package body associated with it

MODELINGSTYLES The architectural body which determines the internal characteristics of an entity can be modeled using different modeling styles as described below 1.Asasetofinterconnectedcomponents(torepresentstructuralstyle), 2.Asasetofconcurrentassignmentstatements(torepresentdataflowstyle), f q g ( p y ), 3.Asasetofsequentialassignmentstatements(torepresentbehavioralstyle), 4.Anycombinationoftheabovethree.

StructuralStyleofModeling In the structural style of modeling, an entity is described as a set of interconnected components. Such a model for the HALF_ADDER as discussed before, is described in an p , architecture body as shown below.

The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ADDER (presented in the previous section) specifies the interface ports for this architecture body. The architecture body is composed of two parts: the declarative part (before the keyword begin) and the statement part (after the keyword begin). Two component declarations are present in the declarative part of the architecture body. These declarations specify the interface of components that are used in the architecture body. The components XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they may later be bound to other components i a lib h in library. The d l d components are i h declared instantiated i the statement i d in h part of the architecture body using component instantiation statements. X1 and A1 are the component labels for these component instantiations.

The first component instantiation statement, labeled XI, shows that signals A and B (the input ports of the HALF_ADDER), are connected to the X and Y input ports of a XOR2 component, while output port Z of this component is connected to output port SUM of the HALF_ADDER entity. Similarly, entity Similarly in the second component instantiation statement signals A and B are statement, connected to ports L and M of the AND2 component, while port N is connected to the CARRY port of the HALF_ADDER. DataflowStyleofModeling In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this modeling style but it can be implicitly deduced Consider the following alternate style, deduced. architecture body for the HALF..ADDER entity that uses this style.

The dataflow model for the HALF_ADDER is described using two concurrent signal assignment statements ( t t t (sequential signal assignment statements are d ti l i l i t t t t described i th next section). I a ib d in the t ti ) In signal assignment statement, the symbol <= implies an assignment of a value to a signal. The value of the expression on the righthandside of the statement is computed and is assigned to the signal on the lefthandside, called the target signal. A concurrent signal assignment statement is executed only when any signal used in the expression on the righthandside has an event on it, that is, the value for the signal changes. Delay information is included in the signal assignment statements using after clauses.

BehavioralStyleofModeling In contrast to the styles of modeling described earlier, the behavioral style of modeling y g , y g specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality. f nctionalit A process statement is a conc rrent statement that can appear within an concurrent ithin architecture body. For example, consider the following behavioral model for the DECODER2x4 entity.

Basic language Elements These include data objects that store values of a given type, literals that represent constant values, values and operators that operate on data objects Every data object belongs to a specific objects. type. Data Objects

Data Types Data types categorically divides different forms of data to be associated with data objects. Subtypes are data types with constraints These constraints may specify a range of values constraints. values.

Scalar Types

Composite Types

Operators Operators are mathematical or logical functions which give action to data objects or relate two or more data objects

Logical Operators

Relational Operators

Adding Operators

Multiplying Operators

Miscellaneous Operators