May 2011

Q.1a) Design a 8086 microprocessor based system with the following specifications. 1. Working at 8 MHz. 2. 32 KB EPROM using 8 KB Chips. 3. 32 KB SRAM using 16 KB chips. Solution: Total EPROM memory: Chip size available : 32 KB 8 KB

No. of chips required : 32/8 =4 No. of sets SET 1 Starting add. : 00000 H Size of set 1 : 03FFF H Ending add. SET 2 Starting add. : 04000 H Size of set : 03FFF H : 00000 H + 03FFF H = 03FFF H :2

Ending add. : 04000H +03FFF H = 07FFF H Total SRAM size = 32 KB Chip size available = 16 KB No. of chips = 2 No. of sets = 1 SET 1 Starting add. =08000 H

Set size = 07FFF H Ending add. : 08000 H +07FFF H =0EFFF

Q1 b) compare 80286 & 80386 microprocessors on basis of 1)no of address lines 2)no of data lines 3)no of segment registers Ans= PARAMETERS 80286 80386

1)Size of address bus 2)size of data bus 3)no of segment registers

20 bit 16 bit 4 registers of 16 bit

32 bit 32 bit 6 registers of 16 bit

Q.1.C output.

WAP of PIC controller, PORTA for input and PORTB,PORTC for

#include<PIC18F8620> ORG 0x00 GOTO START ORG 0x08

RETFIE ORG 0x18 RETFIE Start CLRF TRISB,A CLRF TRISC,A SETF TRISA,A MOVF PORTA,W,A MOVWF PORTB,A MOVWF PORTC,A End

2. a) Draw PSW of 8086 microprocessor and explain setting of different bits with example. Flag register is part of EU. It is 16 bit register with each bit corresponding to a flipflop. OF DF IF TF SF ZF AF PF CF

There are a active flags out of 16. The remaining are undefined flags. Control flags: 1) Trap Flag (TF) It is used to set the trap mode i.e. start single stepping mode. Here the microprocessor is interrupted after every instruction so that program can be debugged.

2) Interrupt Flag (IF) It is used to mask (disable) or unmask (enable) the INTR interrupt. IF=1 - Interrupt enabled. IF=0 - Interrupt disabled. If user sets IF flag. CPU will recognize external interrupt request. Clearing IF disables these interrupts. 3) Direction Flag (DF) a) If this flag is set. SI and DI are in auto decrementing mode in string operations. b) If DF=1, the string instruction will automatically decrement pointer. c) If DF=0, the string instruction will automatically increment pointer. Conditional Flags (status): 1) Carry Flag (CF) a) It is set whenever there is carry (or borrow) out if MSB of a result. (D7 bit for an 8 bit operation and D15 bit for 16 bit operation) b) Flag is used by instruction that add and subtract multibyte numbers. 2) Parity Flag (PF) It is set if result has even parity. If parity is odd. PF is reset. This flag is normally used to checkfor data transmission errors. e.g: 10110101 => odd parity PF=0.

10010101 => even parity PF=1. 3) Auxiliary carry Flag (AF) a) It is set if carry is generated out of lower Nibble . b) It is used only in 8 bit operations like DAA and DAS. c) AF = 1 => carry out if bit 3 on addition or borrow into bit 3 on subtraction. AF = 0 => no carry out from bit 3 on addition nor borrow into bit 3 on subtraction. e.g: If we add, 0100 0000 + 0100 0010 1000 0010 As carry is not generated from lower nibble, AC=0. 4) Zero Flag (ZF) It is set if result is zero. e.g: 0000 0000 + 0111 1111 0111 1111 ZF =0 as result is non-zero 5) Sign Flag (SF) a) It is set if MSB of result is 1. b) SF indicates sign of result only in case of signed operation. c) In case of unsigned, sign bit has no significance. SF=1; MSB is 1. SF=0; MSB is 0.

Eg. Addition of positive numbers: 0100 0000 + 0100 0010 1000 0010 SF = 1 Addition of negative numbers. 1100 0000 + 1011 1110 0111 1110 SF =0. 6) Overflow Flag (OF) a) It will be set if result of signed operation is too large to fit in number of bits available to represent it. b) If result is not out of range, OF remains reset. Eg. 0010 0011 + 0011 0101 0101 1000 OF = SF = ZF = AF = PF = CF = 0. -40 + (-40) = -82

1100 0000 + 1011 1110 0111 1110

-40 + (-42) = -82

OF = 1, SF = 0, ZF = 0, AF = 0, PF = 1, CF = 1.

Q2b. Explain different data transfer modes of DMA controller IC 8257. Ans. Usually data transfer takes place between microprocessors and peripheral device by using a program stored memory which is known as microprocessor controlled data transfer. In this method, data transfer speed is less. The reason is each instruction has to be fetched from memory by microprocessor and then executed. Sometimes we dont want to process the data. During this time a DMA microcontroller is used to transfer data between peripheral devices. This is called as device controlled data transfer. Now there are three data transfer modes in DMAC 8257: 1] Byte or Single Mode:

In Byte or Single mode, after transferring one byte of data the bus control relinquished and handed over to the microprocessor. 2] Burst or Demand Mode:

In Burst or Demand mode, data is transferred till the time, the peripheral is ready. After this the bus control is handed over to the microprocessor.

3] Continuous or Block Mode:

In this mode, it is identical to the demand mode, but the bus control is not relinquished until the entire block of data has been transferred.

Q 2. C) Write functions of following 8086 pins. 1. Lock :i. ii. This pin in minimum mode carries WR (write) signal and carries LOCK signal in maximum mode. This is active low signal and it does not allow external bus master to take control of system bus. It is activated when 8086 executes an instruction with the LOCK prefix and remains active till the next instruction. iii. LOCK prefix : normally the bus request is serviced after the current machine cycle and an interrupt request is serviced after the current instruction cycle. But if we write LOCK prefix before any instruction then even if there is bus request the bus will be released only after cyrrent instruction. iv. Microprocessor will remain LOCK signal through out the instruction to indicate that it is performing instruction with LOCK prefix. v. LOCK signal is given to 8289 Bus Arbiter in loosely coupled systema, to prevent it from relaesing system bus to other bus masters.

2. QS0 and Qs1 :i. ii. iii. iv. This pin carries ALE signal in minimum mode and QS0 in maximum mode. Qs1 signal is carried in maximum mode and same pin carries INTA in minimum mode. These are active low pins. QS0 is used along with QS1 to indicate instruction queue status.

Q3a)Write addressing Rodes of following 8086 instructions. I. II. III. IV. V. MOVCL,25 MOV[SI],BX ADD BX,DX SUB CL,[BX+SI] IN AL,80H

I.

MOV CL,25H

Immediate operand Is nothing but constant data contained is instruction .Thus of a source operand is part of instruction of register or memory it is referred as immediate addressing rode. MOV CL,25H; CL<- 25H

{ii} MOV[SI],BX [SI]<- BX Register indirect addressing rode In this addressing rode the effective address of memory may be taken directly from one of the base register or index register. {iii} ADD BX,DX BX<-BX+DX Register Addressing rode In this mode of addressing, data is in the register ,and instruction specifies the particular register. Register may be used as source operand, destination or both. (iv) SUB CL, [BX+SI] CL<- CL- [BX+SI] Base indexed Addressing rode

In this Addressing rode, the effective address is sum of a base register and an index register, both of which are specified by the instruction. (v) IN AL,80H Direct port addressing rode In direct addressing, the port number is an 8-bit immediate operand. This allows fixed access to ports numbered o-255.

Q3.b)

Data And Program Memory Organisation of PIC18

The PIC18 microcontroller supports 4096 bytes of data memory locations. Hence it requires 12bits of address to select one of the data registers. Eight bits of PIC18 are used to specify the register to be operated on. As a result only 256 registers can be accessed i.e. 4096 registers are divided into 16 banks. Only 1 bank of 256 registers is active at any time selected by a 4 bit bank selector register (BSR). Function Registers (SFRs). GPRs are used to hold user random data when the PIC18 is executing the program. SFRs are control registers used for CPU and on chip peripheral devices. The SFRs begin from the highest address and go downwards whereas GPRs must be used from address 0 and go upwards. The first 98 bytes (i.e. is in bank 0,000H to 05FH) of the GPRs and the last 160 bytes (i.e. is in bank 15, F60H to FFFH) of the SFRs are grouped into a special bank called access bank. The PIC18 also has a 1KB of data EEPROM, which is readable and writeable during normal operation with no extra power supply. The data EEPROM memory is not directly mapped in the 4096 bytes of register file

space; instead it is indirectly addressed through a Special Function

Register.

Q3.C The PIC18 Pipelining

- The PIC18 Divide most of the instruction execution into two stages: instruction fetch and instruction execution. - Up Up to two instructions are overlapped in their execution One instruction is in to two instructions are overlapped in their execution. One instruction is in fetch stage while the second instruction is in execution stage.

- Because of pielining, each instruction appears to take one instruction cycle to complete and thus making microcontroller to work faster.

TCY0

TCY1

TCY2

TCY3

TCY4

fetch 1 execute 1 fetch 2 execute 2 fetch 3 execute 3 fetch 4 execute 4

fetch 3 execute 3 fetch 4 flush Instruction @address sub_1 fetch sub_1 execute sub_

Q4.a) Draw block diagram of I/O port pin of PIC 18.Which are the different registers involved in the operation of I/O port of PIC 18 and write their operations. Ans

PORT NAME A B C D E F G H J

NO OF PINS 7 8 8 8 8 8 5 8 8

PIN NAME RA6..RA0 RB7..RB0 RC7..RC0 RD7..RD0 RE7..RE0 RF7..RF0 RG4..RGO RH7..RH0 RJ7..RJ0

There are 3 registers for the operation of each I/O Port TRIS Register:-This register is used to control the data direction of port pins PORT Register:-This register is used to rad the data on the pins of the processor LAT Register:-This latch is used to latch the data for O/P port For E.g. Port A has TRISA, PORTA, LATA register

Q.4)b) Which are the different methods used for program loops? Explain each method in short. Ans: The programming technique used to instruct the p to repeat task is called looping. 8086 instruction set different instructions are available to implement the loops, which changes the program branch such a part of program is executed again to perform the task again. Loops can be of two types: 1. Continuous Loop: This loop repeats task continuously. It is implemented using unconditional JMP instruction. This loop can be considered as infinite loop, it repeats the task until the system reset. For example, if we want to generate continuous waveform of square wave or trigular wave, the program should be written with continuous loop.

Fig 1: Continuous loop.

Fig 2: Conditional loop

2. Conditional Loop: This loop repeats task only if particular condition satisfies. This loop is implemented using conditional JMP instructions. This loop repeats task n times or repeats task if certain condition is satisfied. The condition is checked using conditional flags like zero flag, parity flag, sign flag, carry flag, etc. For example, if we want to repeat task 10 times, we should write a program with counter initialized with count equal to 10. Every time the task is performed, the count should be decremented and program should check for the count, whether it has become zero. Once the reaches to zero the program stops.

Q.5a). Explain following instruction of PIC 18

i) CLRF F,a F,a v)BC,n

ii) BCF F,b,a

iii) DAW

iv) CPESEQ

Ans: i) CLRF F,a Operands : 0<=f<=255, a[0,1] Operation : 000hf, 1Z Status affected : Z Description : Clears the contents of the specified register. If a is 0 the access bank will be selected, overriding the BSR value. If a=1 then the bank will be selected as per the BSR value. Cycles: 1 Example: CLRF Flag_Reg,1.

ii) BCF F,b,a Operands : 0<=f<=255, 0<=b<=7, a[0,1] Operation : 0f<b> Status affected : None Description : Bit b in register f is cleared. If a is 0, the access bank will be selected overriding the BSR value. If a=1 then the bank will be selected as per the BSR value. Cycles : 1 Example : BCF Flag_reg,7,0.

iii) DAW Operands : None Operation : If [W<3:0>>9] or [DC=1] then (W<3:0>)+6W<3:0>; else (W<3:0>)W<3:0> If [W<7:4>>9] or [C=1] then (W<7:4>+6)W<7:4>; else (W<7:4>)W<7:4>.

Status affected : C Description : DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables & produces correct packed BCD result. Cycles : 1 Example : DAW If W=0xA5, C=0, DC=0 Then W=0x05, C=1, DC=0.

iv) CPFSEQ F,a Oprands : 0<=f<=255, a[0,1] Operation : (f)-(W), skip if (f)=(W) Status affected : None Description : Compares the contents of data memory location f to the contents of W by performing an unsigned substraction. If f=W, then instruction is discarded & NOP is executed. Cycles : 1(2) Example : CPFSEQ Reg,0.

v) BC, n Operands : -128<=n<=127 Operation : if carry bit is 1 (PC)+2+2nPC Status affected : None Description : If the carry bit 1 then the program will branch. The 2s compliment number 2n is added to the PC. New address is (PC)+2+2n. Cycles : 1(2) Example : BC 5

(PC)=PC+2+10=PC+12.

Q.5.b write and explain maximum mode operation of 8086.

The use of the bus controller IC 8288 along with the other support chips. Additional circuitry is required to translate the control signal. The additional circuitry converts the status (S2-S0) to I/O and memory transfer signal. The intel 8288 bus controller is used for this purpose. It generates the control signals required to direct the data flow and for controlling the latches 8288 and trans-receiver 8286.

It generates the signal MRDC, MWTC, AMWC, AIOWC, IORC, IOWC signal.

The MRDC and MWTC are memory read command and memory write command signal. They instruct the memory to accept or send data on the data bus.

The IORC and IOWC are I/O read command and I/O write command signal. They instruct the I/O device to read write data to and from address port on the data bus.

The AIOWC and AMWTC are advanced I/O write command and advanced memory write command signals. These signals are similar to the IOWC and MWTC signals except that, they are activated one clock signal earlier to the IOWC and MWTC signal.

Q 6 b] Explain different string premitives of 8086. : A string is series of bytes stored sequentially in the memory. String

instructions operate on such strings. The source string is at a location pointed by SI in the data segment. The destination string is at location pointed by DI in the extra segment. The count for string operation is alwys given by cx. Since cx is a 16 bit register we can transfer max 64kB using string instruction. SI and /or DI are incremented/decremented after each operation depending upon the direction flag DF in the flag register. If DF=0,it is auto increment. This is done by CLD instruction. If DF=1, it is auto decrement. This is done by STD instruction.

1]MOVS : MOVSB/MOVSW(move string) It is used to transfer a word/byte from data segment to extra segment. The offset of source in data segment SI. The offset of destination in extra segment is in DI.

SI and DI are incremented/decremented depending upon the direction flag. Eg. MOVSB ; ES:[DI] ; SI<- SI+1 ;DI<-DI +1 MOVSW ; {ES:[DI],ES:[DI+1]} ; SI<-SI+2 ;DI<-DI+2

2]LODS: LODSB/LODSW(load string) It is used to load AL(or AX) register with a byte (or word) from datav segment . The offset os t5he source in data segment in SI. SI is incremented/decremented depending upon direction flag(DF). Eg.LODSB; AL<-DS:[SI] ;SI<-SI+1 LODSW ;AL<-DS:[SI] ;AH<-DS:[SI+1] ; SI<-SI+2 3] STOPS: STOPSB/STOPSW(store string) It is used to store AL into a byte in the extra segment. The offset of the source in extra segment is in DI. Eg: STOPSB ; ES:[DI]<-AL ;DI<-DI+1 STOPSW ; ES:[DI]<-AL ;DI<-DI+2 4]CMPS: CMPSB/CMPSW(compare string ) It is used to compare a byte in the data segment with a byte in the extra segment. The offset of the byte in data segment is in SI. The offset of the in extra segment is in DI. Eg. CMPSB ;compare DS:[SI] with ES:[DI] ;SI<-SI+1 ;DI<-DI+1

CMPSW

;compare {DS:[SI], DS:[SI+1]} ;SI<-SI+2 ;DI<-DI+2

5]SCANS: SCANSB/SCANSW(scan string) It is used to compare the contents of AL with a byte in the extra segment. The offset of the byte in the extra segment is in DI. DI is incremented/decremented depending upon direction flag(DF). Eg. SCANSB SCANSW ;compare AL with ES:[DI] ;DI<-DI+1 ;compare{AX} with {ES:[DI]},ES:[DI+1]} ;DI<-DI+1

Q7 a) short note on instruction formats of PIC 18 Ans.) the instruction set is grouped into five basic categories. These categories and their instruction formats are A) Byte oriented file register operations: the format of byte-oriented instruction is as shown OPCODE 15 10 d 9 A 8 7 f(FILE#) 0

d=0 for result destination to be WREG register d=1 for result destination to be file register (f) a=0 to force Access Bank a=1 for BSR to select bank f= 8-bit the register address

Example instruction: ADDWF MYREG, W, B The 6-bit field opcode specifies the operation to be performed by the ALU. B) Byte to byte move operations (2 words): the format of the instruction in this category is as shown OPCODE 15 1111 15 f(Source FILE#) 12 11 f(Destination FILE#) 12 11 0 0

f= 12 bit file register address Example instruction: MOVFF MYREG1, MYREG2 There is one instruction that uses the format MOVFF F1, F2. This instruction allows one to move data from one file register to another. C) Bit oriented file register operation: the format of the instruction in this category is as shown OPCODE 15 b( BIT# ) 12 11 9 a 8 f( FILE# ) 7 0

b= 3 bit position of bit in file register (f) a=0 to force Access Bank a=1 for BSR to select bank f=8-bit file register address Example instruction: BSF MYREG, bit, B The format uses an 8-bit field (f) to specify a file register as operand. D) Literal operations: Instructions in this category specify a literal (an immediate value) as an operand. the format of the instruction in this category is as shown OPCODE 15 8 7 k(literal) 0

k=8-bit immediate value Example instruction: MOVLW 0x7F E) Control operations: the format of the instruction in this category is as shown

CALL, GOTO and Branch operations Example instruction: GOTO label OPCODE 15 1111 15 12 11 n= 20-bit immediate value Example instruction: CALL MYFUNC OPCODE 15 9 S n<7:0> (literal) 8 7 0 8 n <7:0>(literal) 7 0

n<19:8>( literal) 0

n<19:8> (literal) 15 12 11 S=Fast bit Example instruction: BRA MYFUNC OPCODE 15 11 n<10:0> (literal) 10 0 0

Example instruction: BC MYFUNC OPCODE 15 8 n<7:0> (literal) 7 0

The notation <7:0> stands for the bit 7 to bit 0 of 20-bit immediate number n, whereas the notation n <19:8> stands for the bit 19 to bit 8 of 20-bit

immediate number n. The number n <10:0> means that the number n is an 11-bit number. There are four different variations of this formats.

Q7.b: Write a short note on: What do you mean by object code compatibility in processors? How is it achieved in x86 processors. Ans: Object code compatibility refers to backward compatibility of the object code of earlier processor in a later version of the same architecture. From the date of the very first working sample of the 8086 microprocessor to the latest and greatest IA-64 CPU, Intel has had an important goal: as much as possible, ensure compatibility with software written for previous generations of the processor. This mantra existed even on the first member of the family, Intel chose to include compatibility with their previous 8-bit microprocessor, the 8085. The 8086 was not capable of running 8085 software, but Intel designed the 8086 instruction set to provide almost a one for one mapping of 8085 instructions to 8086 instructions. This allowed 8085 software developers to easily translate their existing assembly language programs to the 8086 with very little effort. Intel did not provide object code compatibility with the 8085 instruction set because the design of the 8085 instruction set did not allow the expansion Intel needed for the 8086. Since there was very little software running on the 8085 that needed to run on the 8086, Intel felt that making the software developers responsible for this translation was a reasonable thin to do.

The first real extension to the 8086 family the found its way into general purpose PCs was the 80286 that appeared in 1982. This CPU answered the second complaint by adding the ability to address up to 16 Mbytes of RAM. Unfortunately, it did not extend the segment size beyond 64 kilobytes. In 1985 Intel introduced the 80386 microprocessor. This chip answered most of the complaints about the x86 family, and then some, but people still complained about these problems for nearly ten years after the introduction of the 80386. The code written for 8086 can work on 80386 and further processors. This is how x86 processors achieved object code compatibility.

Q7.C

ASSEMBLER DIRECTIVES:

Assembly Language consists of 2 types of statements:1. Executable statements: all instructions 2. Assembler Directives: These are the statements that direct the assembler to do something. They are classified as: Simplified Segment Code Data Const Exit Model Stack Data Allocation equ db dw DD DF DQ,dt,org Segment assume end ends group segment Macros endm macro local Exitm Code Label align even label PROC Scope Com extrn public Listing Control Page Ttitle Misc

Includ Name

1.code: *It indicates the beginning of code segment. code(name)

*For tiny, small and compact models, the segment name is TEXT always. *The medium and large memory models use more than one code segments. 2.data: It indicates the beginning of data segment. 3.model: * This directive is used for selecting a standard memory model for the assembly language program. * eg. model (memory model) * The memory model is chosen based on the users requirement by referring to the size of memory. * The size of a memory model can be from small to huge. * The tiny model is meant for the COM programs because they have their code in only one 64 KB segment of memory. * The flat model is the biggest which defines one area upto 4 GB for code and data. * The small model is useful for the student level programs as for this model, the assembler assumes that the address are within a span of 64 KB and henceforth generates 16 KB offset addresses. * In the compact model, the assembler can use 32 Bit addresses. So, the execution time for this model is longer. * The huge model needs a larger space than 64 KB. 4. stack: * Is used for defining the stack. stack (size) * The size of the stack is 1024 Bytes by default but this size can be overridden. e.g. STACK 100 this reserves 100 byes for S.S.

5.equ:is used to generate some value or symbol in the program.each time when the assembler finds that name in the program it replaces that name with the value assigned to that variable Eg:factorial equ 05h 6.define byte(db) It defines the byte type variable Name db initial value 7:define word:it defines the byte type variable Eg:name db initial value 8:define word:the dw directive defines items that are not one word in length.the range is 0 to 65,535 for unsigned,for signed -128 o 127. 9:define quad word:it defines the assembler to declare variable in words in length of 4 words. 10:define ten bytes:used to define the data items that are 10 bytes long. 11:org (originate):it allows the location counter to set the starting address at any desired point in memory. 12:assume:it is used fr telling the assembler the name of logical statement to be used. Eg:cs:code,ds:data] 13:end:it is placed ta the end of program or statement to indicate end . 14:segment ends:indicates the end of segment. 15:group:it collects the segments of same type under one segment. 16:macro and endm:indicates macro directives. 17:align:it tells the assembler to align the next instruction to the address that is specified in the instruction. 18:even:it tells the assembler toa increment the program counter evenly.

19:label:it assigns name to the current value of location counter.the label directive must be followed by a term which specifies the type of associated with the symbolic name. 20:proc:this directive is used to indicate the start of a procedure. 21:extrn:it indicates that the names or labels that follow extrn directive are in some other assembly module. Eg:extrn disp:far. To call a procedure that is in the program module assembled at a different time from that which contains call instruction,the assembler has to be told that procedure is external. 22:public:it informs the assembler and linker hat theidentified variables in a program are to be refrenced by other modules. Eg: PUBLIC multiplier,divisor.

23:page:used to specify maximum no. of lines on a page and max no. of characters on a line. 24:title :it helps for controlling the format of listing of an assembled program it id usedc to give a title to program and print the title on every line. 25:include:is used to tell assembler to insert a block of source from the named fileinto current source module Eg:INCLUDE path :filename 26:name:assisns a specific ame to each assembly mpodule when program s consisting of several modules are written. 27:dup:it is use to allocate space for a table or array . 28:global:it can used instead of public directive. 29:length:it is an operator .it informs the assembler tpo find number of elements I a named data item Eg:mov cx,length of string. 30:offset:it is an operator.it informs assembler to determine offset of a named data item.

31:endp:is use with the named of the procedure to indicate the end of procedure. 32:label:it is an operator.is udsed to assign a specific type to a variable or label. 33:short:is an operator used to tell the assembler that only one byte displacement is needed to code a jump instruction. 34:type:it is an operator.it informs the assembler to fin d the type of a specified variable .the assembler actually finds the number of bytes in type of variable.for byte assembler is given a value 2 and for word is given a value 4.

THE END