Flip-Flops and Latches

An SR latch is shown in figure 13.3. The latch Truth table is shown in the following table. The two inputs, S and R denote ``set'' and ``reset'' respectively. The latch has memory, and the present output is dependent on the state of the latch. Thus the output at instant, denoted by is dependent on output at instant, denoted by .

Figure 13.3: Construction of a latch from NOR gates Students should verify the veracity of the truth table from the figure 13.3. S R 1 0 0 1 1 1 0 0 1 0 0 0 1 0

Note that in state, both and are 0, which seems absurd. Thus, conventionally, the state is said to be ``not allowed''. A similar latch, known as latch is constructed using NAND gates (as opposed to NOR gates for latch). The students should again check that the working of the latch coheres with that of the truth table. Figure 13.4: Construction of a latch from NAND gates

0 1

1 0

1 0

0 1

0 1

0 1

To avoid ``race'' between the inputs, to have a control on when the input affects the latch, the circuit 13.5 is often implemented.

Figure 13.5: Circuit to avoid ``race'' condition The inputs have an effect on the latch only when , otherwise, the previous state is maintained. The input may be a clock, so that whatever transitions in and take place before the clock changes to do not affect the outputs, and only when the inputs have become stable is the system affected.

Digital Circuits
Boolean Operators: Single Input Single Output: eg. NOT operation 12.1. Operation A and B take binary (0,1) values.

Figure 12.1: A NOT gate Multiple Inputs Single Output: Eg 1. OR operation 12.2. if either of B ``or'' is The truth table is as follows: A 0 C

0 0

0 1 1

1 0 1

1 1 1

Truth table for OR gate

Figure 12.2: An OR gate Eg 2. AND operation is shown in figure 12.3

Figure 12.3: An AND gate A 0 0 1 1 B 0 1 0 1 C 0 0 0 1

Truth table for AND gate These were basic gates which are implemented using transistor and other devices. The transistor implementation is shown if figure 12.4

Figure 12.4: Implementation using a BJT IC based gates are shown in figure 12.5

Figure 12.5: IC based gates Other functions NAND: Not + AND

Figure 12.6: NAND gate

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

Truth table for NAND gate NOR gate Not+OR gate

Figure 12.7: NOR gate A 0 0 1 1 B 0 1 0 1 C 1 0 0 0

Truth table for NOR gate X-OR gate Exclusive-OR gate

Figure 12.8: X-OR gate A B C

0 0 1 1

0 1 0 1

0 1 1 0

Truth table for X-OR gate X-NOR gate Exclusive NOR

Figure 12.9: X-NOR gate A 0 0 1 1 B 0 1 0 1 C 1 0 0 1

Truth table for X-NOR gate.

Using NAND gates

NOT

Figure 12.10: Realizing a NOT gate using a NAND gate OR The following statements are called DeMorgan's Theorems and can be easily verified and extended for more than two variables. (12. 1)

(12. 2)

In general: Thus :

(12. 3) (12. 4) (12. 5) (12. 6)

Now it is easy to see that , which can be checked from the truth table easily. The resulting realization of OR gate is shown in 12.11

Figure 12.11: Realization of OR gate by NAND gates AND gate

Figure 12.12: Realization of AND gate by NAND gates X-OR gate (12. 7) Clearly, this can be implemented using AND, NOT and OR gates, and hence can be implemented using universal gates.

Figure 12.13: X-OR gate X-NOR gate

(12. 8) Again, this can be implemented using AND, NOT and OR gates, and hence can be implemented using universal gates, i.e., NAND or NOR gates.

Figure 12.14: X-NOR gate

Boolean Expressions
A general realization of a Boolean expression is shown in 12.15

Figure 12.15: Realization of a Boolean Expression: shown as a black box Example: In a car, we have the following components: A Day-night sensor: Day-1, Night-0 B Lamps on: On-1, Off-0 C Ignition on: On-1, Off-0 D Warning light for lamps-on In this case, the truth table for the logic D would be A B C D 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0

1 1 0 1 1 1 1 1 Therefore,

, which can be written as in the sum of product form. We arrive at this by looking at the combinations when the outout is one. We can alternatively, express this in the product of sums form by looking at the combinatins when the outout is low as

Using SOP and POS, it can be implemented as follows:

Next, we will try to reduce the number of gates by combining terms suitably.

We can get the above by clubbing the

s in the k-map shown.

Now, if we club the zeroes together in the k-map,

Check that we get the same expression by simplifying the product of sums expression (by using (X+Y)(X+Z)=X+YZ) Multiplexer

The truth table for the multiplexer is as follows:

0 0 1 1

0 1 0 1

Multiplexers (MUX)
For logic function realizations, instead of logic gates, Multiplexers can also be used Consider a boolean function f={1,2,6,7}. Here input variables are A,B,C. Multiplexer schematic for multiplexer is shown in figure 13.1

Figure 13.1: ( ) multiplexer implementation of logic function Depending on the contorl input combination specfic input is connected to the single output of multiplexer. (13. 1)

When multiplexer is used to implement the above function. We connect boolean logic '1' at the inputs corresponding to control inputs ABC= 1, 2, 4, and 6. For all other input boolean logic '0' is connected. In case we take a multiplexer we can make as control input and then determine what should be connected at the inputs of multiplexer as shown below. (13. 2) (13. 3) (13. 4) (13. 5)

Multiplexers (MUX)
For logic function realizations, instead of logic gates, Multiplexers can also be used Consider a boolean function f={1,2,6,7}. Here input variables are A,B,C.

Multiplexer schematic for

multiplexer is shown in figure 13.1

Figure 13.1: ( ) multiplexer implementation of logic function Depending on the contorl input combination specfic input is connected to the single output of multiplexer. (13. 1)

When multiplexer is used to implement the above function. We connect boolean logic '1' at the inputs corresponding to control inputs ABC= 1, 2, 4, and 6. For all other input boolean logic '0' is connected. In case we take a multiplexer we can make as control input and then determine what should be connected at the inputs of multiplexer as shown below. (13. 2) (13. 3) (13. 4) (13. 5)

The realization is shown in figure 13.2 using a

Mux.

Figure 13.2: Multiplexer (

) Implementation

Flip-Flops and Latches

An SR latch is shown in figure 13.3. The latch Truth table is shown in the following table. The two inputs, S and R denote ``set'' and ``reset'' respectively. The latch has memory, and the present output is dependent on the state of the latch. Thus the output at instant, denoted by is dependent on output at instant, denoted by .

Figure 13.3: Construction of a latch from NOR gates Students should verify the veracity of the truth table from the figure 13.3. S R 1 0 0 1 1 1 1 0 0 0 1 0

0 0

Note that in state, both and are 0, which seems absurd. Thus, conventionally, the state is said to be ``not allowed''. A similar latch, known as latch is constructed using NAND gates (as opposed to NOR gates for latch). The students should again check that the working of the latch coheres with that of the truth table. Figure 13.4: Construction of a latch from NAND gates

0 1 0 1

1 0 0 1

1 0 1

0 1 1

To avoid ``race'' between the inputs, to have a control on when the input affects the latch, the circuit 13.5 is often implemented.

Figure 13.5: Circuit to avoid ``race'' condition The inputs have an effect on the latch only when , otherwise, the previous state is maintained. The input may be a clock, so that whatever transitions in and take place before the clock changes to do not affect the outputs, and only when the inputs have become stable is the system affected.

Sequential circuits

In the above circuit, we have the problem of multiple tranistions when the clock is active.

Master Slave Flip-Flop (S-R)

When , , and are both 1. Therefore, it is an undefined condition. This can be eliminated by proper feedback.

for the above circuit, the truth table is

1 0 1 0

1 1 0 0 0 1

The problem with the circuit shown above is that when clock =1, the feedback will cause oscillatinons and when clock goes zero, the predicting the ouput state is difficult. On the other hand, master slave configuration does not allow oscillation.

Edge triggered Flip-Flop

The above diagram shows a positive edge triggered flip-flop. The truth table is as follows

0 1 0 1

1 0 0 1

0 1

1 0