Anda di halaman 1dari 5

Overview of Nanoelectronic Devices

Nour EL-Din Safwat Saad

ECE Department, Ainshams University Cairo, Egypt

Abstract This paper surveys and explains MOSFET scaling limits, Nanoscale MOSFETs (SOI- FET, DG-FET) describing the structure, advantages and drawbacks and other nanoelectronics devices (RTD, SET Transistor) describing the quantum effects in this devices, its structure and operation
Keywords-component; FINFET; SOI-FET; SET transistor;

gate leakage current can not only increase standby power dissipation but also limit the proper device operation.
2) Sub-threshold leakage current: The Sub-threshold leakage



The silicon MOSFET has been scaled down for more than thirty years to obtain higher performance and higher levels of integration. Recently, the miniaturization rate has accelerated, and the gate length is now less than 40 nm .Further miniaturization of silicon metal-oxide semiconductor fieldeffect transistor (MOSFETs) into nanoscale complementary MOS (CMOS) will significantly affect advances in future information technology . The international Technology Roadmap for Semiconductors (ITRS) [1] predicts that gate lengths in mass-produced CMOS transistor will be less than 10 nm in year 2016.Howerver, it is recognized that it will be extremely difficult for bulk-Si MOSFET technology to meet industry-specified performance targets for both drive current and leakage current in a near future .New techniques and architecture to overcome the scaling and performance limits of conventional CMOS devices are urgently needed. This paper introduces overview on the nanoscale devices. The rest of this paper is organized as follows. Section 2 MOSFET Scaling Limits. Section 3 Nano-Scale MOSFETs. Section 4 Other Nan-Devices. Finally; conclusions are presented in section 5. 2. MOSFET SCALING LIMITS[2]
1) Direct tunneling gate leakage current: With the continuous device scaling, the gate oxide thickness has been accordingly reduced to maintain the gate controllability over the channel. However, as the gate oxide thickness scales below 2 nm, the direct tunneling (DT) gate leakage increases

current is the weak inversion conduction current, which is dominated by the diffusion current flowing between the drain and source when |VGS| < |Vth|. It is considered as one of nonideal characteristics of MOSFET as a switching device and contributes major portions of the standby leakage power dissipation. 3) Direct source to drain tunneling: The ultimate physical scaling limit of MOSFETs is direct source-to-drain tunneling. If the barrier width (transistor channel length) between source and drain becomes small enough for electrons to tunnel through the barrier without any additional gate bias 4) Reverse-biased junction leakage current (reversebiased band-to-band tunneling current) BTBT: Reverse-biased junction leakage current (IREV) is the current flowing between the source/drain (S/D) and the substrate through the parasitic reverse-biased pn-junction diode in the offstate MOSFET. IREV mainly consists of the diffusion and drift of minority carriers near the depletion region edge and the generation of electron-hole pairs in the depletion region of the reversebiased pn-junction. The amount of IREV depends on the junction area and doping concentration. If both S/D and substrate regions are heavily doped, BTBT dominates the IREV since the electric field across the junction depletion region increases. The various leakage mechanisms in a MOSFET are illustrated in Fig. 1.

exponentially due to quantum mechanical tunneling. The DT

Figure.1. (a) Various leakage mechanisms in a MOSFET, (b) IOFF, min is the minimum achievable leakage current in a MOSFET. In low EG materials it is generally limited by IBTBT

5) Hot carrier effects (HCEs): The high electric fields in a device also cause reliability problems such as threshold voltage shifts and trans-conductance degradation and therefore the device becomes unstable and even can fail. 3. A. NANO-SCALE MOSFETS

(silcon on insulator)SOI-MOSFET Advantages The advantages of SOI technology come from its buried oxide (BOX) layer (a cross-section of a SOI device is shown in Fig. 2). With the reduction of the parasitic capacitances, mostly as a result of the reduced drain/source junction capacitances [3], SOI devices yield improved switching speed and reduced power consumption. The operating speed is also improved since the isolated channel from substrate bias prevents the increase in a threshold voltage of stacked SOI transistors. In addition, the perfect lateral and vertical isolation from substrate provides latch-up and inter-device leakage free CMOS technology, reduction in various interferences, and better soft error immunity. Moreover, SOI technology offers tighter transistor packing density and simplified

and advanced process techniques, fully depleted ultrathinbody SOI (FD UTB SOI) devices are considered as one of the best scaling options. Undoped or very lightly doped UTB devices minimize impurity scattering and reduce threshold voltage variation resulting from random dopant fluctuation. On the other hand there is a significant drawback in SOI technology. Since the BOX, which has approximately 100 times lower thermal conductivity than that of silicon, prevents thermal conduction path from SOI transistors to the substrate, SOI transistors are easily affected by the thermal heating generated in the channel, which is called Self-Heating Effects. Consequently, the self-heating degrades the mobility of carriers and causes the threshold voltage shift. These effects get worse with FD structures because they use thinner silicon films. B. (Double Gate) DG-FINFET Structure In the double gate transistor structures, there are two gate electrode surfaces controlling the channel region simultaneously or independently. Because of its structure, the DG-FET can have three different possible configuration of its two gate electrode thus giving three different designs with different level of complexities as far as fabrication is concerned [4].

Figure3.Three different topologies of the DGFET Figure.2. Cross-section of a SOI MOSFET

SOI transistors are classified into two types; partially depleted (PD) SOI, if the silicon film (typically 100 nm or more) on the BOX layer is thicker than the depletion region depth beneath the gate oxide, and fully depleted (FD) SOI, if the body (silicon film) thickness is thin enough (typically50 nm or less) or the doping concentration of the body is low enough to be fully depleted. FD SOI transistors have superior advantages over PD SOI transistors in terms of extremely low subthreshold swing (<65 mV/decade), no floating-body effects, and low threshold voltage variation with temperature (2-3 times less). However, since FD SOI transistors are even more sensitive to process variation such as the silicon film layer variation resulting in threshold voltage fluctuation, PD SOI devices were commercially introduced first. With careful device design

Type I DGFET is the most straightforward implementation, an extension of current bulk MOSFET technology. The second gate can be placed underneath the active device. While such device is simple to envision, the process flow is extremely complex, often requiring wafer bonding or selective epitaxial silicon growth. The biggest challenge comes in aligning the top and the bottom gate without introducing substantial parasitic resistive and capacitive elements. The process flow to fabricate this device is quite different from the existing BULK process, making it unattractive to be adopted by semiconductor industry for production. Rotation of the double-gate device structure and making use of the third dimension out of wafer plane could provide for an easier method of fabrication. One such proposed structure, the Vertical Replacement Gate FET, achieves the DG structure by rotating it by 90 degrees out of the wafer plane through an axis

parallel to gate line. It results in a vertical structure through which current flows normal to the wafer surface. This structure is advantageous for critical dimension control as the gate length is determined by a deposited film thickness, which is significantly more controllable than standard lithography techniques. However, this results in a device technology that can support only a single gate length, which places a severe constraint on digital and analog circuit designers alike, who often need larger gate lengths for ratioed logic or improved output resistance. If, however, the double-gate FET is rotated by 90 degrees through the axis parallel to the direction of current flow (Type III), some of the traditional fabrication problems associated with double gate FETs can be overcome. This device has been termed as FinFET device (Figure. 4).

Figure.5 Bulk MOSFET and FinFET device

Figure.4 Schematic of FinFET Advantages

The double-gate (DG) FinFET provides a fundamental advantage over conventional single-gate (SG) FETs. In short-channel FETs, the drain potential competes with that of the gate to influence the channel. When the drain 'wins' the transistor is said to suffer from 'punch-through' and becomes too leaky in the 'off' state to be useful for ultra large-scale integration (ULSI). With a conventional transistor, the channel potential is isolated from the drain by a combination of proximity of the gate electrode (thin gate dielectric) and the neutral body (shallow body depletion depth). As a result, good short-channel control requires strong coupling of the channel to the body; this coupling has two negative influences, namely increased subthreshold swing, and decreased drive current for a given VGS-VT. In the double gate architecture, a second gate plays the role of the neutral body and thus short channel control can be affected through increased influence of this second gate. Since this second gate is electrically connected to the first gate, increased coupling for short-channel control also results in increased coupling for subthreshold and superthreshold control of the channel[5][6] (figure.5).

One advantage of the FinFET, is that the channel can be undoped. That feature will become increasingly important as the channel length shrinks. The number of dopants in doped channels becomes exceedingly small as their length and width/height shrinks to only a few tens of nanometers. Consequently, fluctuations in this number during manufacture, along with small variations in the channel length across the chip, could wreak havoc on threshold voltages, degradingif not ruiningcircuit operation. In contrast, the absence of channel doping allows the gate to have much more influence over the device's threshold voltage. Another advantage is that the fin can be made extremely thin. This feature means that no region of the fin escapes the influence of the gate. Power consumption is lower because there is no leakage path for charge carriers to flow between the source and drain when the device is off. On the other hand, the gate misalignment has a serious effect on the performance of the device. If the gate is misaligned enough in either direction (towards the source, or towards the drain), there will exist a region on the opposite side of the back gate where the body of the device is not double-gated. Here, the advantage of the double- gate device is lost. If this un-gated region is on the drain side, the back gate is not preventing the drain fields from fringing into the channel and causing threshold voltage roll-off. This results in increased DIBL for this device[7]. If the un-gated region is on the source side, the back gate is not assisting the front gate in controlling the sourceto-channel barrier. This results in a change in the absolute threshold voltage of the device.

C. TRI-GATE FET The tri-gate FET is like DG-FET but has 3 gates (top gate and the two side gates) as in figure 6. Tri-gate FET is currently receiving great attention by the industry due to its high gate-channel controllability, impressive scalability over planar structures, high drive current and near-ideal subthreshold swing. Tri-Gate MOSFETs are ideally suited for low power and low standby power digital applications, and are promising candidates for future nanometer MOSFET applications [8].

switched off. This method of using variable bias to control a tunneling current is characteristic of a two terminal resonant tunneling device called the Resonant Tunneling Diode (RTD) [10]. Similar adjustment of the energy levels in the potential well relative to the source can be achieved by varying the voltage on a third (gate) terminal. This configuration is part of a Resonant Tunneling Transistor (RTT). The RTT is similar to a MOSFET, in that it can act as a switch or an amplifier.

Figure6.Tri-Gate Transistor



There are various kinds of nanometer-scale solid-state replacements for the bulk effect transistor that have been suggested. The essential structural feature they have in common is a small island composed of semiconductor or metal in which electrons may be confined. Island dimensions typically lie in the range of 5 to 100 nm. The island may consist of a small region different from the surrounding material or it may demarcated by minute, specifically patterned electrodes. The nanometer-scale island is thus surrounded by closely spaced potential energy barriers. Two important quantum mechanical effects are exhibited by electrons confined to such islands. The first one pertains to energy quantization, which restricts the electrons to occupy one of a finite number of one-electron energy levels (quantum states)[9]. The smaller the island, the more widely spaced in energy are these levels. Secondly, if the potential barriers are thin enough (~5 to 10 nm), electrons resident in energy levels lower than the height of the barriers have a finite probability of tunneling through the barrier to get on or off the island. A. Resonant Tunneling Devices We focus primarily on explaining the operation of resonant tunneling devices, because they employ quantum effects in their simplest form. Presently, these devices usually are fabricated from layers of two different III/V semiconductor alloys, such as the pair GaAs and AlAs. The simplest type of resonant tunneling device is the resonant tunneling diode (RTD). In Figure 7(a), a bias voltage across the island induces mobile electrons in the conduction band of the source region to attempt to move through the potential well in the island region to reach the drain region, which is at a lower potential. It is crucial that the energy of the quantum states in the potential well on the island can be adjusted relative to the energy of the bands in the source and drain region, so that tunneling can take place. As in Figure 7(b), when the bias potential is sufficient to lower the energy of an unoccupied quantum state inside the well to be within the source conduction band energy range, the quantum well is said to be in resonance or on, and electrons can tunnel on to the island. Usually, there are a large number of unoccupied energy levels present in the drain region, so that electrons can easily tunnel off the island, and current can flow as in Figure7(c). Otherwise, current through the device is blocked the device is out of resonance or

Figure.7 Operation of Solid-State Resonant Tunneling Diode

B. Single-ElectronTransistors (SETs) The device consists of two tunnel junctions characterized by (as shown in Figure.8) a junction capacitance C, a tunneling resistance R. The two junctions are separated by an island which is coupled to a gate bias, while a source-drain bias is applied across the tunnel junctions as shown. An SET can be visualized as having a double barrier potential. The double junction is a circuit consisting of two tunnel junctions in series, which form an island between them. The junctions are biased with a voltage source connected between the source and drain. For very small bias no current, as the electrons do not have enough energy to overcome the barrier. We initially assume that no bias voltage is applied to the gate terminal. Increasing the source to drain bias voltage steadily, at some point it becomes possible for an electron to tunnel through the first junction. This electron enters the island thus increasing the energy level of the island from Ne to (N +1) e. This in turn forces an extra electron to exit from the island through the second barrier, thus re- turning the island to its earlier energy state Ne. Since the source to drain bias voltage has not changed, another electron enters the island through the first junction resulting in a steady current through the double

junction. If we make the second tunnel junction barrier higher than the first barrier, then certain number of electrons will have to be accumulated on the island before any electron can tunnel through to the drain. This phenomenon of blocking an electron from immediately leaving the island is called coulomb blockade. The source to drain voltage increase necessary to overcome the coulomb blockade is called the coulomb gap voltage [11]. As we increase the drain-source voltage, due to the quantization of the electronic charge an increase in current occurs only at increments of the coulomb gap voltage as depicted by the conductance graph of Figure 9. Hence, the current waveform looks like a staircase called the coulomb staircase (as in Figure10).We have a device that switches between conducting and non-conducting stages by the addition of a single-electron at the gate terminal. Hence it can be used for building logic circuits similar to CMOS circuits.

researches have been actively carried out to find an alternative way to continue to follow Moores law. Among these efforts, various kinds of alternative memory and logic devices, so called beyond CMOS devices, have been proposed. These nanodevices take advantage of the quantum mechanical phenomena and ballistic transport characteristics under lower supply voltage and hence low power consumption. Moreover, due to their extremely small size, those devices are expected to be used for ultra density integrated electronic computers. While nanoelectronics presents the opportunity to incorporate billions of devices into a single system, it also increases defects and variations both during manufacturing and chip operations. Therefore, an additional constraint, reliability, has to be added to the conventional low-power, high speed and highdensity design consideration. Due to this additional constraint, it is necessary to develop a new knowledge and reliability paradigm for nanoelectronics in order to enable industries to predict, optimize and design upfront reliability and performance of nanoelectronics. The new paradigm should be in a multi dimensional space covering devices, interconnects, architecture, circuit design, CAD, and fabrication issues. REFERENCES
[1] International Technology Roadmap for Semiconductors (ITRS) 2009 Edition. Available from: [2] Yong-Bin Kim Challenges for Nanoscale MOSFETs and Emerging Trans. Electr. Electron. Mater. 10(1) 21 (2009): G.-D. Hong et al. [3] FINFET Electronics Seminar Topic | [4] vaidyanathan subramanian multiple gate fieldieffect transistor for future CMOS technology [5] Naveen Agrawal-Design, Simulation and Fabrication of Ultra Thin Fin for Double Gate MOSFETS [6] David Michael Fried The Design ,Fabrication and Characterization of Independent gate FINFETs,May2005 [7] Kuk-Hwan Kim, Jin-Woo Han , Yang-Kyu Choi, investigation of gate misalignment effects in FinFETs [8] Jean-Pierre Colinge Multiple-gate SOI MOSFETs J.-P. Colinge Solid-State Electronics 48 (2004) 897905 [9] Ellenbogen,DavidGoldhaberGordon,MichaelS.Montemerlo,J.Christophr Lover Overview of nano electronics devices [10] R.Compao,L.Molenkamp Technology Road Map for nanoelectronics [11] Tezaswi Raja,Vishwani D. Agrawal,Michael L. Bushnell A Tutorial on the Emerging Nanotechnology Devices

Figure 8: Schematic of an SET.

Figure 9: Plot of conductance of an SET as a function of source to drain voltage.

Figure 10: Plot of conductance of an SET as a function of source to drain voltage. Where (energy gap between two energy levels) U(repulsion energy electrons must overcome to get on the island)

5. Conclusion As dimensional scaling of CMOS transistors is reaching its fundamental limits, various