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A 0:35 m Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links
Carlos Zamarreo-Ramos, Teresa Serrano-Gotarredona, and Bernab Linares-Barranco, Fellow, IEEE
AbstractThis paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching mechanism. Using this technique, the link power consumption can be scaled down with the event rate without compromising the maximum system throughput. The proposed technique has been implemented on a typical push/pull low voltage differential signaling (LVDS) circuit, but it can easily be extended to other widely used current mode standards, such as current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL). A proof of concept prototype has been fabricated in 0 35 m CMOS incorporating the proposed driver/receiver pair along with a previously reported switchable serializer/deserializer scheme. At a 500 Mbps bit rate, the maximum event rate is 11 Mevent/s for 32-bit events. In this situation, current consumption is 7.5 mA and 9.6 mA for the driver and receiver, respectively, while differential voltage amplitude is 300 mV . However, if event rate is lower than 2030 Kevent/s, current consumption has a oor of 270 A for the driver and 570 A for the receiver. The measured ON/OFF switching times are in the order of 1 ns. The serial link could be operated at up to 710 Mbps bit rate, resulting in a maximum 32-bit event rate of 15 Mevent/s. This is the same peak event rate as that obtained with the same SerDes circuits and a non-switched driver/receiver pair. Index TermsAddress event representation (AER), asynchronous circuits, asynchronous communications, event-driven processing, low voltage differential signaling (LVDS), LVDS drivers, Manchester encoding, neuromorphic circuits and systems, serial AER, serial interchip communication.
Received October 07, 2011; revised December 13, 2011; accepted January 15, 2012. This work was supported in part by Andalusian Grant TIC-6091 (NANO-NEURO), Spanish grants from the Ministry of Economy and Competitivity (former Ministry of Science and Innovation) TEC2009-106039-C04-01 (VULCANO) (with support from the European Regional Development Fund), and PRI-PIMCHI-2011-0768 (PNEUMA) coordinated with the European CHIST-ERA program. C. Zamarreo-Ramos was supported by an FPU scholarship. This paper was recommended by Associate Editor S.-C. Liu. The authors are with IMSE-CNM-CSIC, Sevilla 41092, Spain (e-mail: terese@imse-cnm.csic.es; bernabe@imse-cnm.csic.es). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TBCAS.2012.2186136

I. INTRODUCTION

DDRESS EVENT REPRESENTATION (AER) is becoming a very popular protocol among the neuromorphic community for virtually connecting neurons built in different chips using limited hardware resources [1], [2]. When a neuron generates an output spike in the transmitter chip, an AER output block will assign a digital address to this event. The information is transmitted through a fast digital bus to the receiving chip. Analyzing the AER address, an input block is able to send a spike to any target neuron within the destination chip. This way, the AER protocol can establish virtual connections between neurons without needing physical wires between them. This communication infrastructure paves the way for efcient hardware implementations of large scale spiking neural networks. The elds of application of the AER protocol include vision (retina) sensors [3][7], auditory systems [8][11], winner take all networks [12], [13] and cortical brain structure emulation systems [14][17]. In recent years there has been a growing interest in building large-scale multi-module AER systems [12], [18][31]. These implementations follow different approaches to managing network trafc between blocks, but all of them face the problem of integrating a lot of asynchronous communication channels. Hardware implementation in large scale systems imposes stringent design constraints for the communication layer to improve system reliability and achieve affordable power consumption. Most reported AER based processing chips and sensors use bit-parallel ports for the inter-chip communication interface. This introduces a severe scalability problem when multi-chip AER systems need to be assembled. Parallel buses lead to a high pin count and power hungry AER units. An alternative solution to the bulky parallel AER link is to transmit event sub-words serially through a smaller parallel port [22], [23]. When consecutive events share parts from previous events, they are not re-transmitted, reducing link trafc and power. However, large scale systems demand even higher degrees of integration and several groups have proposed migrating from parallel or word serial solutions to fully bit-serial AER links. This approach would combine a high data rate with lower power consumption [25][27], [32]. All reported bit-serial AER links are implemented using commercial Serializer/Deserializer (SerDes) parts or FPGA Rocket I/O channels to reduce cost and development time.

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Fig. 1. Example of a 120-chip multi-module multi-link AER system PCB Concept. Each chip has 8 AER serial ports, each with a pair of LVDS microstrips and corresponding handshaking wires. Each chip contains an event processor and a programmable event router. Every time an event is received the router decides whether the event is destined to the local event processor, or needs to be transfered to another serial AER output port.

Traditional high speed serial links are not, however, sufciently power efcient to transmit sparse AER events. In embedded clock applications, data and clock information are both merged in a single channel. Using channel encoding schemes, such as 8 B/10 B codes, the user can ensure a high enough number of transitions in data ow to keep the receiver synchronized. A clock-data-recovery circuit (CDR) analyzes the input stream and extracts the clock from it employing a phase locked loop (PLL) or delay locked loop (DLL) circuit. However, a continuous data ow is required to keep the link synchronized. In the absence of user data, idle commas are transmitted and discarded by the receiver. In source synchronous solutions, clock and data are forwarded to the receiver through different signal paths. Two driver/receiver pairs are needed to support this communication, increasing system complexity and overall power consumption. Nevertheless, there is no need for a constant data ow between the transmitter and receiver sides. For example, Fig. 1 shows a possible PCB hosting 120 AER chips in a 2D grid, each with eight bit-serial low voltage differential signalling (LVDS) links, exploiting mesh network communications [33]. Typical LVDS links may present a current (including SerDes consumption between and Driver/Receiver I/O pads). Consequently, the current concould sumption of the links in the PCB in Fig. 1 range from 14.4 A to 144 A. Fortunately, AER trafc is sparse

can therefore be easily reduced by several and the average orders of magnitude by developing serial links with event rate dependent power consumption. An asynchronous and event-driven SerDes architecture was recently proposed [34] to overcome the limitations of embedded clock and source synchronous approaches. The clock is embedded in the data ow but the CDR circuit does not need any comma transmissions when there is no user data. Synchronization information is digitally stored at the receiver side and updated with every new event. Communication can be restarted immediately, avoiding the need for long preambles or loss of information. In this serial AER link, a Manchester encoding scheme introduces extra edges in the bit stream to guarantee a proper clock recovery. Hence, only one driver/receiver pair is needed to implement the communication. A pair of digital request/acknowledge signals are sent along with the high speed AER data for ow control purposes, using a 4-phase handshaking protocol. The asynchronous SerDes power consumption scales down with event rate [34]. This is not the case with the high speed LVDS [35] driver/receiver pair [36] used in this primary implementation. These circuits have a large static power consumption that remains even if there is no data being transmitted. As serial lines must operate at any known logic value, a mA range current ows through the termination resistor. Several authors have addressed the problem of reducing the LVDS driver power consumption [37][40]. The techniques proposed range from low voltage implementations of current mode drivers that reduce the number of stacked elements [37], to low input capacitance driver realizations to save power in the pre-driver stage [38] or even voltage mode circuits in BiCMOS [39], [40] or CMOS [41] technologies. However, all these solutions are focused on dynamic power reduction and still suffer from high static power dissipation. In this paper, we propose to increase the serial AER link power efciency by quickly turning off the LVDS driver/receiver bias currents that are responsible for static power consumption.1 This way, the driver/receiver pair will be switched OFF in the presence of pauses and turned back ON quickly when new events are ready to be transmitted. A fast start-up link is mandatory because recovery time directly impacts overall link latency and reduces the maximum achievable throughput. A reasonable limit for the additional latency introduced by the switching mechanisms described in this paper is set to 1 bit time. This way, the power saving mechanisms would not trade-off with the maximum link throughput. The proposal presented in this paper is for a regular push/pull current mode LVDS driver circuit and a conventional receiver. The current mode approach has been adopted rather than the voltage mode approach because it provides robust impedance matching and higher immunity to power supply noise. Voltage mode circuits can achieve similar (or even higher) precision in impedance matching, but to do so they need extra calibration
1This idea was advanced in an earlier proposal [42], presenting simulation results for the ST90 nm technology. However, such a design was never submitted for fabrication because the technology was discontinued. As a consequence, we decided to develop the driver and receiver for the low cost and widely used AMS 0:35 m technology, since all our AER chips are also designed for this technology.

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Fig. 2. (a) Desired waveform of the supply current drawn by the switchable driver or receiver when a 1/T event rate is being transmitted. (b) Differential mode voltage of the serial data for this current consumption pattern. T is serial bit transmission time, T is event transmission time (34 bits plus overheads), T is inter-event pause, T is start overhead, T is end overhead, and T is inverse of actual event rate.

Fig. 3. Figure of merit  versus event rate parametrized by the on/off current ratio.

circuitry. These extra circuits contribute to increasing the driver power consumption and introduce an area penalty. In principle, therefore, current mode drivers ensure better signal integrity and higher data rates for an identical channel than their voltage mode counterparts. On the other hand, current mode logic (CML) [43] or low-voltage positive emitter-coupled logic (LVPECL) [44] drivers are simpler to design as they do not require commonmode adjustment circuitry, although when turning them OFF and back ON quickly, it is necessary to keep their common mode for fast recovery, thus making the design more complex. As the technique proposed is based on efciently switching large current sources ON/OFF, the solution presented here for the push/pull LVDS driver can be directly extended to other current mode standards. The paper is structured as follows. The next Section quanties the power saving effects of switching off the driver and receiver circuits in pauses. Section III briey reviews the previously presented burst mode SerDes scheme [34], while Section IV discusses the changes introduced in the classic AER protocol to handle the link switching operation. Section V describes the circuit implementation and design techniques used for both driver and receiver blocks. Finally, Section VI shows experimental reCMOS. sults obtained from a prototype fabricated in II. SWITCHABLE HIGH SPEED SERIAL LINKS Fig. 2 shows the desired waveforms for the supply current and differential mode voltage of switchable high speed serial links. Instantaneous current consumption switches from a high current in the order of mA when circuits are transmitting data in pauses. Tranto a low current in the order of hundreds of sitions between both states must be very sharp to maintain a be the time high throughput and low latency in the link. Let required by the SerDes scheme to transmit a single event and the time that the link remains idle between two consecutive transmissions. The mean current consumption for an event ow with an average 1/T event rate is (1)

A conventional current mode driver is not switched OFF when a pause is detected. This leads to a constant current consumption . Let independent of the event rate and given by us dene a gure of merit for the power saving effect of the switchable link as (2) where is the time difference between two consecutive events ( for ). Case corresponds to a conventional current mode link without current switching. The lower the value for , the higher the power saving effect achieved. The ratio between the ON/OFF currents depends on the driver/receiver circuit implementation. The second term of (2) introduces the dependence of on event rate. Fig. 3 shows a family of curves that plot versus event rate for different ON/OFF current ratios. For very low event saturates to its minimum value, determined by the rates, relation between ON and OFF currents. For medium and high data rates, the gure of merit decreases linearly with data rate. ratio is the basic design variable for optimizing The serial link energy efciency and minimizing it will be the main goal of this work. III. SWITCHABLE AER SERIALIZER/DESERIALIZER CIRCUIT A power efcient instant start-up event-based SerDes circuit pair was recently proposed [34] which can instantly stop and resume serial bit data transmission. This circuit is able to interface with existing AER blocks and convert the classic parallel bus into a high speed serial channel and viceversa. Fig. 4(a) shows the block diagram of the previously reported bit-serial AER LVDS link. The sender reads the input 32-bit parallel AER data and implements the 4-phase handshaking protocol with reqIN and ackIN signals. The sender also activates reqSER when the input event is latched and ready to be transmitted. When ackSER acknowledges a previous request, the event is serialized into a pair of wires and two bits of preamble are added to the event address. The bit stream is encoded in a Manchester format with the time reference given by a master clock. The receiver decodes the transmitted address and communicates it to the next block

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Fig. 5. (a) Previously used AER protocol [34]. (b) Modication for the switchable version.

(for 100 Keps tion from 17 mA (for 10 Meps) down to2 and below), without introducing any speed penalty. IV. AER PROTOCOL MODIFICATION ON/OFF switchable LVDS driver and receiver I/O pad pairs need to handle extra signals to control the ON/OFF switching. In particular, the sender takes the decision to turn OFF the driver when there is no data to transmit. When a pause occurs, the differential output lines are made to evolve to the same commonmode voltage, as there is no current owing through the termination resistor. In principle, we could use the serial handshaking signals to tell the driver and receiver pads whether a bit-serial event is being transmitted or not. However, the previously used handshaking signals [34], only indicate the start of the bit-serial transmission and not its duration. A modication to the traditional AER protocol is therefore required to provide the timing information to detect pauses, switch OFF bias currents, force a constant output value, and freeze the deserializer. Fig. 5(a) presents the AER protocol waveforms used previously for the burst mode SerDes implementation [34]. In this case, the transmitter sets a low level in reqSER when new data is ready to transmit. If the receiver is ready to handle a new event, it returns the acknowledge ackSER, enabling the transmission. Then reqSER returns to a high level, the transmitter considers that handshaking transaction completed and the receiver sets ackSER to high level while the bit-serial data transmission continues until it nishes. The protocol modication proposed is shown in Fig. 5(b). Keeping ackSER at low level until the bit-serial data transmission has nished provides a proper timing reference for the driver/receiver to switch ON/OFF. This way, the driver and receiver are activated when reqSER and ackSER have a falling edge, respectively, and are disabled with the next rising edge at ackSER. The deserializer generates a pulse at reqOUT when the event has been completely decoded and deserialized. Signal ackSER is deactivated afterwards to switch OFF the link until the arrival of the next event. Fig. 4(b) shows the modications introduced to handle the AER protocol modication. Signal ackSER is generated by the new block ackSergen, which receives signal reqOUT and the original acknowledge generated by the Serial-RX handshake block ackSERold when the receiver can accept a new event. A falling edge at reqSER activates the transmitter and the serial
2As we will explain in Section VI, this residual current consumption is mainly due to a non-optimum bias circuit.

Fig. 4. Block diagram of the bit serial AER LVDS link. (a) Peviously reported implementation [34]. (b) Modication to handle the ON/OFF switching mechanism. Changes from one implementation to another are highlighted.

using a parallel AER interface implemented with reqOUT and ackOUT. The deserializer needs to extract the transmission master clock to decode the input data ow. Manchester coding always generates a transition in the middle of the bit period to embed the clock in the bit stream. A specialized clock and data recovery (CDR) circuit is used to extract the master clock from the data [45]. This extracted clock rclk is used to decode data from the Manchester stream and put it into a parallel format. As the data ow generated by the AER chips is asynchronous, there can be long pauses without data transmission. The deserializer therefore has a memory mechanism to keep the extracted clock frequency tuned during inactive periods. For a more detailed description of the serializer and deserializer circuits the reader is referred elsewhere [34]. For this particular implementation we showed that the eventrate dependent current consumption of the SerDes pair varied (for 100 Keps and from 22 mA (for 10 Meps) down to below). However, the physical LVDS driver and receiver pads used a non-switchable design [36], draining a total rate-independent current of about 16 to 17 mA. A further important rate dependent power saving can therefore be achieved by using a switchable LVDS driver/receiver I/O pad pair. In this paper we present just such an LVDS pair, which reduces current consump-

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Fig. 6. Circuit block ackSergen [see Fig. 4(b)] in the receiver that transforms ackSERold into ackSER, which is active during the event bit-serial transmission.

outputs evolve to a known logic value (zero in this case). After a propagation delay, request signal reqSER arrives at the receiver side, which is also turned ON if it has resources to receive new data. One constraint is that the high speed bit-serial signals must be stable at their zero value when the receiver is activated. The propagation delay of the reqSER path must therefore be longer than that of the high speed serial path. Signals reqSER and ackSER must be propagated along two standard digital pads (one in the transmitter chip and the other in the receiver chip). If the driver is designed to recover from pauses with sub-bit delays, communication can be established without asynchronous hazards. The receiver generates ackSER using the simple circuit shown in Fig. 6. The deserializer generates a pulse in ackSERold when it detects that reqSER is at low level and a new event can be processed. This pulse generates a reset for the falling edge triggered ip-op shown in Fig. 6, causing the activation of ackSER. This signal is sent back to the transmitter and stays activated until a falling edge at reqOUT occurs. At this point, the ip-op is triggered and captures its input, which is tied to the voltage supply. This makes ackSER return to high level and the link is turned OFF, waiting for the next event. V. CURRENT-MODE LINK CIRCUIT IMPLEMENTATION A. Physical LVDS I/O Driver Circuit A typical push pull current mode transmitter acts as a current source with switched polarity [36]. Output current ows through the load resistance, establishing the correct differential output voltage swing. MOS switches are used to change the output current polarity depending on the transmitted logic level. Output common mode is controlled by a feedback loop which senses it, compares it to a reference and acts on the current sources. The high precision voltage reference is generated by a bandgap circuit. The main power consumption contribution in a current mode driver comes from current sources. If a 350 mV differential am(two plitude is desired and the load resistor is typically resistors located in the driver and receiver), curparallel rent sources of 7 mA are needed. These current sources can be switched OFF during pauses to save power. However, two design considerations must be taken into account to achieve real burst mode operation. When the driver is switched OFF, the output common mode must be retained until the next transmission. If the common-mode is lost, it will take longer to recover. The ON/OFF switching mechanism must be fast enough not to slow down the event transmission rate. That is why

Fig. 7. Proposed switchable current mode driver.

very fast, low noise switchable current sources are required to implement an efcient switchable link. Fig. 7 shows the schematic of the proposed switchable current mode driver. The driver input signals are the single ended bit-serial stream dataSer and the serial AER protocol signals reqSER and ackSER. The ON/OFF Controller generates the differential version of dataSer, labeled INVOA and INVOB, for the NMOS switches. It also generates and drives the enable signal enTX which is active during event transmission to switch ON the driver. This signal is the result of a NAND operation between reqSER and ackSER. When the driver is enabled, bias voltages PBIAS and NBIAS are driven by the common mode feedback (CMFB) circuit. In this conguration, the driver works in the same way as the previously reported non-switchable version [36] and output common mode is controlled by the CMFB circuit. When the driver is disabled, voltages PBIAS and NBIAS are pulled up or down, switching OFF the current sources. are used to terminate the transResistors mission line impedance. A double termination scheme with resistors at both transmitter and receiver sides is used to improve impedance matching and reduce reections which may deteriorate signal integrity. The output common voltage is sensed by into two elements. When the driver is splitting the resistor active, the CMFB block closes the loop and sets the bandgap voltage VREF as output common mode. During pauses, voltage directly forces VREF, but not through the feedback buffer loop. As output currents are very low during pauses, the buffer response time can be designed in the order of ms. Hence, the buffer can be designed to have a very low static power consumption. The CMFB circuit is always driven by a constant voltage at its input. Information contained in PBIAS and NBIAS about the output common mode and the differential amplitude is therefore retained during pauses and immediately restored in the transmission mode. Fig. 8 shows the ON/OFF Controller schematics. This block generates the enTX signal [Fig. 8(a)] when reqSER or ackSER are active at low level indicating that serial handshaking is taking place. An intermediate level of logic disables the switching operation when conguration signal SW is set to ground. Signal REFRESH forces activation of enTX in the

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Fig. 8. ON/OFF Controller schematics for (a) driver activation signal generation. (b) Input rail-to-rail serial stream handling.

Fig. 10. Trade-off between switching time after pauses and current consumption when the driver is turned OFF in the PMOS current source. C is the design variable in both cases. Typical, fast and slow corners are represented.

are used to pull the gate voltage of the transistors up/down, drastically reducing transition times. When the driver is turned voltON, gate voltages are imposed by the CMFB circuit ( ages). When a pause starts, signals enTX and enTXnot switch and there is charge redistribution between the parasitic capacand the design capacitor . This causes a change in itor the gate voltage that can be computed using the charge conservation equations before and after the switching
Fig. 9. (a) CMFB circuit of Fig. 7. (b) Passive pull up/down circuits in Fig. 7.

(4) (5) By applying the charge conservation the voltage step is principle

absence of event transmission in case the common mode needs refresh due to parasitic leaks (see also explanations around Figs. 11 and 19). Moreover, the ON/OFF Controller also adapts the rail-to-rail input signal to a differential format compensating the lag between INVOA and INVOB with a dummy transmission gate, as shown in Fig. 8(b). Tapered buffers and make it possible to maintain a low input parasitic capacitance while providing enough driving capability to handle the LVDS output switches. Fig. 9(a) shows the schematic of the CMFB circuit used in this design. The input differential pair compares a ltered version of the sensed common mode voltage CMID against reference VREF. Any current imbalance generated by the comparator and with a gain is mirrored to the driver current sources . If the feedback loop is stable, the steady state will converge to a common mode equal to reference VREF. Gain is chosen high to keep the CMFB static current consumption much lower than in the high speed path. Passive components and introduce a low frequency compensation pole that ensures common mode control loop stability [36]. To achieve a differential amplitude at the driver load , the CMFB circuit bias current must be of (3) The passive pull up/down circuits used in the design and their basic operation are shown in Fig. 9(b) [37]. The dashed line represents the parasitic capacitor associated with component the PMOS and NMOS transistor gate nodes. Design capacitors

(6) Voltage step can be adjusted through to control at and preferably in the the OFF currents sub-threshold region to reduce static power. These OFF curas rents are added to the bias currents of auxiliary blocks static power consumption during pauses, but power efciency is not compromised if these OFF currents are one order of . However, if the voltage step between magnitude below ON and OFF situations is reduced, the ON/OFF turning mechanism is faster and does not suffer from current peaking. The and idle current trade-off between the turning ON speed consumption is shown in Fig. 10, versus for different technology corners, obtained through simulation. We for the PMOS current source because no chose can be observed for a larger , signicant variation in but speed is degraded as increases. The design capacitor for the NMOS counterpart, determined following the same design procedure, is 0.5 pF. During pauses, gate voltages NBIAS and PBIAS in Figs. 7 and 9(b) are left oating and suffer drift through leakage currents. and becoming This can result in the OFF currents at excessively large, increasing static power and making it difcult to keep the common mode voltage VREF at CMID for buffer (because of mismatch between OFF currents at and ). To avoid such situations the Drift Corrector block (see Fig. 7)

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Fig. 11. Drift Corrector circuit in Fig. 7 that detects drifts at the output common mode during pauses.

.A was chosen where in this design. However, the input common-mode range of this hysteresis comparator is limited, to keep the differential pair and feedback loop transistors in saturation. A preamplier can be added at the comparator input to increase the common-mode range and relax its specications, as shown in Fig. 12(a). Fig. 12(b) shows the preamplier circuit. Its folded-cascode conguration enables a large gain-bandwidth product independent of the input common mode. The PMOS input differential pair output is set to a low DC voltage via the folded cascode structure to increase the input common mode range. Moreover, the internal node of the cascode conguration provides a low impedance output node which pushes the internal pole to high frequencies. The output stage load resistors determine the gain, output common-mode and bandwidth of the pre-amplier (8) (9) The use of a wide input common mode range preamplier allows lower aspect ratio devices for the comparator input stage and preamplier load capacitance can be minimized. This reduces the resistors impact on the frequency response, pushing the output pole to higher frequencies. For this design, with and ,a resistor was chosen. The receiver power consumption is mainly due to the bias currents of the cascaded blocks in Fig. 12(a). These two circuits are not needed during the pauses if the comparator output is forced to have a constant value (zero in this design). Bias currents can therefore be disabled during pauses. A low level in the ackSER signal switches the receiver ON. The switches encircled with dashed lines in Fig. 12 are used to turn the bias currents OFF during pauses. These switches have been designed to enable very fast transitions of relatively high bias currents while maintaining a low ON resistance. A large current passes through these switches during regular operation and the voltage drop can affect the tail current source saturation. VI. EXPERIMENTAL RESULTS A proof of concept prototype of the switchable serial AER CMOS. All the compolink was fabricated in 3.3 V nents described in this paper were integrated as custom-made pads with ESD protections, ground and supply voltage decoupling capacitors and analog circuit biasing resources. The cur, while rent mode driver pad needed an area of 370x . Fig. 13 shows a mithe receiver pad area was 270x crophotograph of the test chip on which the main parts have been highlighted. The bandgap circuit was used to generate a stable, PVT independent common mode voltage and bias currents. A stand-alone voltage controlled oscillator (VCO) was used to generate the master transmission frequency in a programmable way. The test channel used in the experiments comdifferential miprised a pair of PCB traces forming a crostrip line of 5 cm length. Fig. 14 shows the test PCB set-up used in the experiments. Two 16-bit USB-AER boards [46] received events from a

Fig. 12. (a) Receiver architecture. (b) Preamplier. (c) Hysteresis comparator.

detailed in Fig. 11 is added. This is a window comparator comprising two asymmetric comparators and an XNOR gate. The circuit generates an activation pulse at signal REFRESH whenever the output common mode leaves the comparator . This pulse will cause another pulse in the window enTX signal to activate the driver. The pull up/down circuit will and , driving them to their refresh the gate voltages at OFF currents. The driver will remain activated until the output common mode enters the comparison window. B. Physical LVDS I/O Receiver Circuit The conventional LVDS receiver [36] uses a current to voltage conversion with a termination resistor. This voltage is processed by a continuous time preamplier and a rail to rail comparator to provide a proper output for the deserializer circuit, as shown in Fig. 12. The last stage is usually a hysteresis comparator to avoid output glitches due to input noise. The implemented hysteresis comparator, shown in Fig. 12(c), uses a positive feedback loop to achieve enough gain and speed to convert the low amplitude signal into a rail-to-rail signal. The hysteresis range can be controlled by the aspect ratios of the PMOS transistors as (7)

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Fig. 13. Microphotograph of fabricated test prototype.

Fig. 15. AER protocol management at (a) reqIN (dotted line) and ackIN (continuous line) signals. (b) reqSER (dotted line) and ackSER (continuous line) signals. (c) reqOUT (dotted line) and ackOUT (continuous line) signals. (d) Differential mode of the LVDS signal. Time scale is s.

Fig. 14. (a) Schematics of the test set-up for the 32 bit AER pattern management. (b) Board photograph.

PC connected to them through USB ports. These events were sent through a parallel AER connector to the test board. Each USB-AER board provided a 16-bit AER bus, but a 32-bit version was needed for the serial transmitter. For this reason, streams coming from two different boards had to be synchronized to form up a 32-bit AER bus. A complex programmable logic device (CPLD) implemented a C-element for req1 and req2 to generate reqIN. This way, both 16-bit parallel input streams were merged into a single 32-bit stream which was serially transmitted. At the receiver side, the output ow had to be split into two AER streams, each of which could be captured by a single 16-bit parallel USB-AER board. The CPLD performed this task in the same way as in the transmitter side, managing ack1 and ack2. Each output USB-AER board was able to transmit captured and timestamped events to a computer through its USB connection for further analysis. Fig. 15 presents the measured AER handshake protocol signals at (a) the transmitter parallel input (reqIN, ackIN), (b) the

serial interface (reqSER, ackSER) and (c) the receiver parallel output (reqOUT, ackOUT). When a new 32-bit event was ready to be transmitted, the CPLD received the request signals from the USB-AER boards and activated reqIN. This action indicated to the serial AER transmitter that it had to latch the event and respond with an acknowledge ackIN to the USB-AER sender boards. The delay between reqIN and ackIN was 15 ns for a 500 MHz transmission master clock inside the serializer circuit (Serial TX in Fig. 14(a)) [34]. The ackIN remained active during 68 ns, corresponding to the 34 clock cycles required for the serialization process [34]. While the channel was busy with an event, the transmitter stopped the sender side by keeping ackIN at low level. Serial AER signals reqSER and ackSER were used to provide the timing information to switch the high speed serial driver and receiver ON and OFF. Before starting with a new event serial transmission, reqSER was activated and the receiver acknowledged with ackSER if it can handle a new event, with a delay of 6.6 ns. The main difference between this implementation and the one described previously [34] was the duration of the ackSER activation. In this switchable implementation, ackSER was kept active until all event bit data had been transmitted: 82 ns for the 500 Mbps bit rate. When the event was properly recovered from the input serial stream, the output AER interface communicated it to the receiving USB-AER boards. The 24 ns delay between signals reqOUT and ackOUT was due to the USB-AER board logic and the extra latency introduced by the CPLD operation. Fig. 16 shows the measured differential mode of the serial signal at the receiver input. An Agilent DSO81304B Innium oscilloscope with 5 GHz bandwidth probes was used for this measurement. The bit rate was set to 500 Mbps and the event rate was congured to be 4.7 Mevent/s. The ON and OFF switching times were 1 ns (less than the bit time). Compared to the duration

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ZAMARREO-RAMOS et al.: SUB-NS WAKE-UP TIME ON-OFF SWITCHABLE LVDS DRIVER-RECEIVER CHIP I/O PAD PAIR 9

Fig. 18. Current-mode switchable driver and receiver current consumption versus event rate. Differential amplitude is 300 mV.

Fig. 16. Measured high speed serial signal at the receiver input for the currentmode driver with two different horizontal time scales. Differential amplitude is 300 mV.

Fig. 17. Eye diagram for the current-mode driver at receiver input. Differential amplitude is 300 mV .

of the whole event transmission, these times were negligible and did not compromise the serial link latency or maximum event rate. The differential amplitude obtained was 350 mV. Fig. 17 shows the eye diagram for the Manchester encoded stream measured at the receiver input. A 43 ps of rms jitter was measured, very similar to the values measured previously [34] where a non-switchable driver [36] was used. This suggests that the introduction of the switching mechanism does not limit the jitter of the whole link. The maximum event rate was obtained by shorting the reqOUT and ackOUT signals and measuring the input to output request delay. For the 500 MHz clock frequency, the maximum achievable event rate was 11 Mevent/s, corresponding to a 92 ns latency. The link operation tolerated a wide range of transmission frequencies, being tuned continuously using the on-chip VCO. For the maximum frequency operation, corresponding to a 710 MHz master clock, a 66 ns input to output request latency was measured. This produced a maximum event rate of 15 Mevent/s. This was also the maximum event rate we reported previously [34] using the non-switchable driver [36]. Consequently, using the presented switchable driver/receiver pair in-

troduced no delay penalty, but did introduce important rate-dependent power savings. Also, bit error rate (BER) was not degraded by the use of this new switching driver. Fig. 18 shows how the power consumption of the switchable link scaled down with event rate. The high speed circuitry could be programmed to switch the bias currents or not, thus allowing a fair comparison between both situations. If the switching mechanism was deactivated, a roughly constant driver current consumption of 7.5 mA was obtained for all the event rates. In the receiver side, current consumption ranged from 9.6 to 8.4 mA for the maximum and minimum event rate situations, respectively. When the switching mechanism was activated, the maximum receiver and driver power consumptions were almost the same because the circuits remained turned ON most of the time. However, current consumption decreased with event rate. The driver and receiver current consumption and , respectively. These curves saturated at values correspond to the quiescent current consumption of the I/O circuitry when the link was switched OFF. The receiver idle current was high due to the non-optimum biasing circuits for the preamplier and hysteresis comparator. However, this current can be dramatically reduced if an optimized low power biasing circuit is used for the receiver. Testing the circuit that detects drifts in the output common mode during pauses can be cumbersome if we let the leakage currents charge/discharge the driver internal nodes. This approach will require several hours of observation and a sophisticated test set up. To speed up the common mode drift effect, we introduced extra spurious currents in the differential output lines using the set up shown in Fig. 19(a). The oscilloscope differential probe introduced a common mode resistor between the differential lines and ground which drew a current proportional to the output common mode. This current was larger than the common mode retain buffer bias. In this scenario, buffer (see Fig. 7) failed to control the common mode and the resulting dynamics can be observed in Fig. 19(b) by the action of the drift correction circuit of Fig. 11. When the common mode correction circuit detected the drift from the nominal value, it red a refresh pulse and the driver was activated. As the CMFB circuit retained the information about the steady state of the control loop, the output common mode was immediately recovered. When the driver was turned OFF again, the common

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TABLE I PERFORMANCE COMPARISON WITH OTHER LVDS DRIVERS

corresponds to the current consumption when the link is continuously transmitting data and is for the minimum ac) tivity situation. The maximum physical bit rate (for for this work is 1.42 Gbps, which corresponds to twice the transmitted data bit rate of 0.71 Gbps because of the Manchester encoding used in the SerDes circuits.3 VII. CONCLUSIONS This paper describes the design and testing of a current mode switchable driver and receiver I/O circuit pair intended to be used in high speed serial AER links. Turning the I/O circuits ON/OFF during pauses allows power consumption to be scaled with the transmitted event rate. As AER stream activity tends to be sparse in time, this feature is mandatory for the building of reliable, low power, large scale neuromorphic systems in which hundreds of AER chips must communicate with each other. A proof of concept prototype was fabricated in standard CMOS along with SerDes circuits reported previously [34]. The driver realization achieves a current consumption saving factor of 30 compared to its non-switchable counterpart. The receiver current saving factor is 17, but this can be improved by reducing the static power consumption associated with biasing circuits. Due to the high speed mechanisms applied to switch the driver/receiver current sources, the link is able to settle back to its nominal values in 1 ns, thus saving power without trading off against the link maximum event rate. REFERENCES
Fig. 19. (a) Load model for the oscilloscope differential probe. (b) Output common mode and differential mode waveforms when the driver is loaded with probe. [1] M. Sivilotti, Wiring considerations in analog VLSI systems with application to eld-programmable networks computation and neural systems, Ph.D. dissertation, California Inst. Technol., Pasadena, 1991. [2] M. Mahowald, VLSI analogs of neuronal visual processing: A synthesis of form and function, computation and neural systems, Ph.D. dissertation, California Inst. Technol., Pasadena, 1992. [3] V. Chan, C. Jin, and A. van Schaik, An address-event vision sensor for multiple transient object detection, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 4, pp. 278288, Dec. 2007. [4] P. Lichtsteiner, C. Posch, and T. Delbrck, A 128 128 120 dB 30 mW asynchronous vision sensor that responds to relative intensity change, IEEE J. Solid-State Circuits, vol. 43, pp. 566576, Feb. 2008. [5] C. Posch, D. Matolin, and R. Wohlgenannt, A QVGA 143 dB dynamic range frame-free PWM image sensor with lossless pixel-level video compression and time-domain CDS, IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 259275, Jan. 2011.

mode drifted again. This effect allowed us to test the common mode refresh circuit without waiting hours for current source gate voltage charging/discharging due to leakage currents. As can be seen, the comparator window (see Fig. 11) had a value and the comparator response time of was 153 ns. Table I shows a comparison with state of the art LVDS drivers. This implementation is comparable in terms of data rate, layout area and differential mode amplitude with similar works, but it is the only one which scales power consumption with event rate.

3References [36][38] and [41] in Table I do not disclose the f of the technology used. This number has been estimated from other similar technologies.

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ZAMARREO-RAMOS et al.: SUB-NS WAKE-UP TIME ON-OFF SWITCHABLE LVDS DRIVER-RECEIVER CHIP I/O PAD PAIR 11

[6] J. A. Leero-Bardallo, T. Serrano-Gotarredona, and B. Linares-Barranco, A 3:6 s asynchronous frame-free event-driven dynamic-vision-sensor, IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 14431455, Jun. 2011. [7] D. G. Chen, D. Matolin, A. Bermak, and C. Posch, Pulse-modulation imagingreview and performance analysis, IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 1, pp. 6482, Feb. 2011. [8] R. Sarpeshkar, M. Baker, C. Salthouse, J. Sit, L. Turicchia, and S. Zhak, An analog bionic ear processor with zero-crossing detection, in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2005, pp. 7879. [9] B. Wen and K. Boahen, A 360-channel speech preprocessor that emulates the cochlear amplier, in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2006, pp. 556557. [10] V. Chan, S. Liu, and A. van Schaik, AER EAR: A matched silicon cochlea pair with address event representation interface, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp. 4849, Jan. 2007. [11] B. Wen and K. Boahen, A silicon cochlea with active coupling, IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 6, pp. 444455, Dec. 2009. [12] E. Chicca, A. M. Whatley, P. Lichtsteiner, V. Dante, T. Delbrck, P. D. Guidice, R. J. Douglas, and G. Indiveri, A multichip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 4849, Jan. 2007. [13] M ster, Y. Wang, R. Douglas, and S. Liu, Quantication of a spikebased winner-take-all VLSI network, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 10, pp. 31603169, Nov. 2008. [14] R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimnez, C. Serrano-Gotarredona, J. Prez-Carrasco, B. Linares-Barranco, A. Linares-Barranco, G. Jimnez-Moreno, and A. Civit-Ballcels, On real-time AER 2D convolutions hardware for neuromorphic spike based cortical processing, IEEE Trans. Neural Netw., vol. 19, no. 7, pp. 25482566, Dec. 2006. [15] R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimnez, and B. Linares-Barranco, A neuromorphic cortical-layer microchip for spike-based event processing vision systems, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 11961219, Jul. 2008. [16] L. Camuas-Mesa, A. Acosta-Jimnez, C. Zamarreo-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, A 32 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 Meps throughput, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 4, pp. 777790, Apr. 2011. [17] L. Camuas-Mesa, C. Zamarreo-Ramos, A. Linares-Barranco, A. Acosta-Jimnez, T. Serrano-Gotarredona, and B. Linares-Barranco, An event-driven multi-kernel convolution processor module for event-driven vision sensors, IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 504517, Feb. 2012. [18] R. Serrano-Gotarredona, M. ster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gmez-Rodrguez, L. Camuas-Mesa, R. Berner, M. Rivas-Prez, T. Delbrck, S.-C. Liu, R. Douglas, P. Higer, G. Jimnez-Moreno, A. Ballcels, T. Serrano-Gotarredona, A. Acosta-Jimnez, and B. Linares-Barranco, CAVIAR: A 45 k neuron, 5 M synapse, 12 G connect/s AER hardware sensory-processing-learning-actuating system for high speed visual object recognition and tracking, IEEE Trans. Neural Netw., vol. 20, no. 9, pp. 14171438, Sep. 2009. [19] R. Vogelstein, U. Mallik, J. Vogelstein, and G. Cauwenberghs, Dynamically recongurable silicon array of spiking neurons with conductance-based synapses, IEEE Trans. Neural Netw., vol. 18, no. 1, pp. 253265, Jan. 2007. [20] M. Kahn, D. Lester, L. Plana, A. Rast, X. Jin, E. Painkras, and S. Furber, SpiNNaker: Mapping neural networks onto a massively-parallel chip multi-processor, in Proc. IEEE Int. Joint. Conf. Neural Networks, Jun. 2008, pp. 28492856. [21] J. Fieres, J. Schemmel, and K. Meier, Realizing biological spiking network models in a congurable wafer-scale hardware system, in Proc. IEEE Int. Joint. Conf. Neural Networks, Jun. 2008, pp. 969976. [22] T. Y. W. Choi, P. Merolla, J. Arthur, K. Boahen, and B. E. Shi, Neuromorphic implementation of orientation hypercolumns, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 10491060, Jun. 2005. [23] K. Boahen, A burst-mode word-serial address-event link I,II,III, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 12691300, Jul. 2004. [24] P. Merolla, J. Arthur, B. E. Shi, and K. Boahen, Expandable networks for neuromorphic chips, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 301311, Feb. 2007.

[25] H. Berge and P. Higer, High-speed serial AER on FPGA, in Proc. IEEE Int. Symp. Circuits and Systems, May 2007, pp. 857860. [26] D. B. Fasnacht, A. M. Whatley, and G. Indiveri, A serial communication infrastructure for multi-chip address event systems, in Proc. IEEE Int. Symp. Circuits and Systems, May 2008, pp. 648651. [27] L. Mir-Amarante, A. Jimnez-Fernndez, A. Linares-Barranco, F. Gmez-Rodrguez, R. Paz, G. Jimnez, A. Civit, and R. Serrano-Gotarredona, LVDS serial AER link performance, in Proc. IEEE Int. Symp. Circuits and Systems, May 2007, pp. 15371540. [28] S. Mitra, S. Fusi, and G. Indiveri, Real-time classication of complex patterns using spike-based learning in neuromorphic VLSI, IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 1, pp. 3242, Feb. 2009. [29] R. Mill, S. Sheik, G. Indiveri, and S. L. Denham, A model of stimulus-specic adaptation in neuromorphic analog VLSI, IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 5, pp. 413419, Oct. 2011. [30] Z. Fu, T. Delbrck, P. Lichsteiner, and E. Culurciello, An address-event fall detector for assisted living applications, IEEE Trans. Biomed. Circuits Syst., vol. 2, no. 2, pp. 8896, Jun. 2008. [31] C. Zamarreo-Ramos, A. Linares-Barranco, T. Serrano-Gotarredona, and B. Linares-Barranco, Multi-casting mesh AER: A scalable assembly approach for recongurable neuromorphic structured AER systems. Application to ConvNets, IEEE Trans. Biomed. Circuits Syst., accepted for publication. [32] S. Hartmann, S. Schiefer, S. Scholze, J. Partzsch, C. Mayr, S. Henker, and R. Schffny, Highly integrated packet-based AER communication infrastructure with 3 Gevent/s throughput, in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, 2010, pp. 950953. [33] L. Benini and G. D. Micheli, Networks on chips: A new SoC paradigm, IEEE Comput., vol. 35, no. 1, pp. 7078, Jan. 2002. [34] C. Zamarreo-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, An instant-startup jitter-tolerant Manchester-encoding serializer/deserializar scheme for event-driven bit-serial LVDS inter-chip AER links, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 11, pp. 26472660, 2011. [35] LVDS Owners Manual, 4th ed., National Semiconductor, Santa Clara, CA, 2008. [36] A. Boni, A. Pierazzi, and D. Vecchi, LVDS I/O interface for Gp/sper-pin operation in 0:35 m CMOS, IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706711, Apr. 2001. [37] M. Chen, A. Pierazzi, J. Silva-Martnez, M. Nix, and M. Robinson, Low-voltage low-power LVDS drivers, IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 472479, Feb. 2005. [38] A. Tajalli and Y. Leblebici, A slew controlled LVDS output driver circuit in 0:18 m CMOS technology, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 538548, Feb. 2009. [39] K. Abugharbieh, S. Krishnan, J. Mohan, V. Devnath, and I. Duzevik, An ultralow-power 10-Gbits/s LVDS output driver, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 262269, Jan. 2010. [40] V. Bratov, J. Binkley, V. Katzman, and J. Choma, Architecture and implementation of low-power LVDS output buffer for high-speed applications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 10, pp. 262269, Oct. 2005. [41] H. Lu, H.-W. Wang, C. Su, and C.-N. Liu, Design of an all-digital LVDS driver, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 16351644, Aug. 2009. [42] C. Zamarreo-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, Low power LVDS transceiver for AER links with burst mode operation capability, in Proc. 24th Conf. Design of Circuits and Integrated Systems, 2009. [43] P. Heydari and R. Mohanavelul, Design of ultrahigh-speed low-voltage CMOS CML buffers and latches, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 10, pp. 10811093, Oct. 2004. [44] A. Boni, 1.2-Gb/s true PECL 100 K compatible I/O interface in 0.35-m CMOS, IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 979987, Jun. 2001. [45] P. Popescu, A. Solheim, and M. Wight, Experimental monolithic high speed transceiver for Manchester encoded data, in Proc. Bipolar/CMOS Circ. and Tech. Meeting, Oct. 1995, pp. 110113. [46] F. Gmez-Rodrguez, R. Paz-Vicente, A. Linares-Barranco, M. Rivas, L. Mir, S. Vicente, G. Jimnez, and A. Civit, AER tools for communications and debugging, in Proc. IEEE Int. Symp. Circuits and Systems, May 2006, pp. 32533256.

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Carlos Zamarreo-Ramos received the B.S. degree in telecommunications engineering in 2007, the M.Sc. degree in microelectronics in 2009, and the Ph.D. degree in 2011 from the University of Seville, Sevilla, Spain. From 2007 until December 2011, he was a Ph.D. student at the Instituto de Microelectrnica de Sevilla (IMSE-CNM-CSIC), Sevilla, Spain. In June/July 2010, he was with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, as a Visiting Scholar. His research interests include very large scale integration (VLSI) circuit design applied to bio-inspired circuits and systems, bio-inspired signal processing, high-speed serial links, modular assembly of recongurable address event representation (AER) processing systems, hardware implementations and simulation of spiking neural networks, implementations of event-driven AER vision processing systems, and power management. Since February 2012, he has been a Junior Analog Designer at Dialog Semiconductor GmbH, Germering, Germany. Teresa Serrano-Gotarredona received the B.S. degree in electronic physics and the Ph.D. degree in VLSI neural categorizers from the University of Sevilla, Sevilla, Spain, in 1992, and 1996, respectively, and the M.S. degree in electrical and computer engineering from The Johns Hopkins University, Baltimore, MD, in 1997. She was an Assistant Professor in the Electronics and Electromagnetism Department, University of Sevilla from September 1998 until September 2000. Since September 2000, she has been a Tenured Scientist at the National Microelectronics Center, (IMSE-CNM-CSIC), Sevilla, Spain, and in 2008 she was promoted to Tenured Researcher. Her research interests include analog circuit design of linear and nonlinear circuits, VLSI neural-based pattern recognition systems, VLSI implementations of neural computing and sensory systems, transistor parameters mismatch characterization, address-event-representation VLSI, RF circuit design, nanoscale memristor-type AER, and real-time vision processing chips. She is coauthor of the book Adaptive Resonance Theory Microchips (Norwell, MA: Kluwer, 1998). Dr. Serrano-Gotarredona was corecipient of the 1997 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award for the paper A Real-Time Clustering Microchip Neural Engine. She was also corecipient of the 2000 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: REGULAR PAPERS Darlington Award for the paper A General Translinear Principle for Subthreshold MOS Transistors. She is an ofcer of the IEEE CAS Sensory Systems Technical Committee. She is Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: REGULAR PAPERS since December 2011.

Bernab Linares-Barranco (M94F10) received the B.S. degree in electronic physics, the M.S. degree in microelectronics, and the Ph.D. degree in high-frequency OTA-C oscillator design from the University of Sevilla, Sevilla, Spain, in 1986, 1987, and 1990, respectively, and the Ph.D. degree in analog neural network design from TexasA&M, College Station, in 1991. Since September 1991, he has been a Tenured Scientist at the Sevilla Microelectronics Institute (IMSE), which is one of the institutes of the National Microelectronics Center (CNM) of the Spanish Research Council (CSIC) of Spain. On January 2003, he was promoted to Tenured Researcher and, in January 2004, to Full Professor of Research. Since March 2004, he has also been a part-time Professor with the University of Sevilla. From September 1996 to August 1997, he was on sabbatical stay at the Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, as a Postdoctoral Fellow. During Spring 2002, he was a Visiting Associate Professor at the Electrical Engineering Department, Texas A&M University. He is coauthor of the book Adaptive Resonance Theory Microchips (Norwell, MA: Kluwer, 1998). He was also the coordinator of the EU-funded CAVIAR project. He has been involved with circuit design for telecommunication circuits, VLSI emulators of biological neurons, VLSI neural-based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, transistor parameter mismatch characterization, address- event-representation VLSI, RF circuit design, real-time vision processing chips, and extending AER to the nanoscale. Dr. Linares-Barranco was a corecipient of the 1997 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award for the paper A Real-Time Clustering Microchip Neural Engine and the 2000 IEEE Circuits and Systems (CAS) Darlington Award for the paper A General Translinear Principle for Subthreshold MOS Transistors. He organized the 1994 Nips PostConference Workshop Neural Hardware Engineering. From July 1997 until July 1999, he was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART II, ANALOG AND DIGITAL SIGNAL PROCESSING, and from January 1998 to December 2009, he was an Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS. He is an Associate Editor of Frontiers in Neuromorphic Engineering since May 2010. He was the Chief Guest Editor of the 2003 IEEE TRANSACTIONS ON NEURAL NETWORKS Special Issue on Neural Hardware Implementations. From June 2009 until May 2011, he was the Chair of the Sensory Systems Technical Committee of the IEEE CAS Society. In March 2011 he became Chair of the IEEE CAS Society Spain Chapter. He is an IEEE Fellow.