Gbe Phy Datasheet

June 2010 Order Number: 319440- 016
Revision 2.3
I nt el 82578 GbE PHY
Dat asheet
Pr oduct Feat ur es
Gener al
10/ 100/ 1000 BASE-T I EEE 802. 3
specificat ion conformance
Support s up t o 4 KB j umbo frames ( full
duplex)
1
Support s carrier ext ension ( half duplex)
Energy det ect low power modes
Loopback modes for diagnost ics
Fully int egrat ed digit al adapt ive equalizers,
echo cancellers, and crosst alk cancellers
Advanced digit al baseline wander correct ion
Aut omat ic MDI / MDI X crossover at all
speeds of operat ion
Aut omat ic polarit y correct ion
I EEE 802. 3u aut o- negot iat ion conformance
MDC/ MDI O management int erface
Flexible filt ers t o reduce MAC power
Shared NVM access t hrough t he MAC
I nt el VPro, I nt el Viiv and Virt ualizat ion
support wit h appropriat e I nt el chipset ( s)
component s
Smart speed operat ion for aut omat ic speed
reduct ion on fault y cable plant s
PMA loopback capable ( no echo cancel)
1. Ref er t o t he l at est I nt el 82578 Speci f i cat i on Updat e f or mor e det ai l s.
Advanced cabl e di agnost i cs
TDR
Channel frequency response
Ex t ended conf i gur at i on l oad sequence
Pow er
Reduced power consumpt ion during normal
operat ion and power down modes
I nt egrat ed I nt el Aut o Connect Bat t ery
Saver
Single pin LAN Disable for easier BI OS
implement at ion
Dual i nt er connect bet w een t he Pl at f or m
Cont r ol l er Hub ( PCH) Medi a Access
Cont r ol l er ( MAC)
2
and Physi cal Layer
( PHY) :
PCI - based int erface for act ive st at e
operat ion ( S0 st at e)
SMBus for host and management t raffic ( Sx
st at e)
Technol ogy
48- pin package, 6 x 6 mm wit h a 0. 4 mm
lead pit ch and an Exposed Pad* for ground
Three configurable LED out put s
Fully int egrat ed linear regulat ion for
1. 2 Vdc
2. The MAC i s i ncor por at ed i nt o t he I nt el
5 Ser i es Ex pr ess Chi pset .

ii
Legal Li nes and Disclaimers
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TO SALE AND/ OR USE OF I NTEL PRODUCTS I NCLUDI NG LI ABI LI TY OR WARRANTI ES RELATI NG TO FI TNESS FOR A PARTI CULAR PURPOSE,
MERCHANTABI LI TY, OR I NFRI NGEMENT OF ANY PATENT, COPYRI GHT OR OTHER I NTELLECTUAL PROPERTY RI GHT. I nt el product s are not int ended for
use in medical, life saving, life sust aining, crit ical cont rol or safet y syst ems, or in nuclear facilit y applicat ions.
I nt el may make changes t o specificat ions and product descript ions at any t ime, wit hout not ice.
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or ot herwise, t o any such pat ent s, t rademarks, copyright s, or ot her int ellect ual propert y right s.
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Please review t he t erms at ht t p: / / www.int el.com/ net comms/ prerelease_t erms.ht m carefully before using any I nt el prerelease product , including any
evaluat ion, development or reference hardware and/ or soft ware product ( collect ively, Pre- Release Product ) . By using t he Pre- Release Product , you
indicat e your accept ance of t hese t erms, which const it ut e t he agreement ( t he Agreement ) bet ween you and I nt el Corporat ion ( I nt el ) . I n t he event
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fut ure definit ion and shall have no responsibilit y what soever for conflict s or incompat ibilit ies arising from fut ure changes t o t hem.
I nt el processor numbers are not a measure of performance. Processor numbers different iat e feat ures wit hin each processor family, not across different
processor families. See ht t p: / / www.int el.com/ product s/ processor_number for det ails.
This document cont ains informat ion on product s in t he design phase of development . The informat ion here is subj ect t o change wit hout not ice. Do not
finalize a design wit h t his informat ion.
The 82578 GbE PHY may cont ain design defect s or errors known as errat a which may cause t he product t o deviat e from published specificat ions. Current
charact erized errat a are available on request .
Hyper-Threading Technology requires a comput er syst em wit h an I nt el
Pent ium
4 processor support ing HT Technology and a HT Technology enabled

chipset , BI OS and operat ing syst em. Performance will vary depending on t he specific hardware and soft ware you use. See ht t p: / / www. int el.com/
product s/ ht / Hypert hreading_more.ht m for addit ional informat ion.
Cont act your local I nt el sales office or your dist ribut or t o obt ain t he lat est specificat ions and before placing your product order.
Copies of document s which have an ordering number and are referenced in t his document , or ot her I nt el lit erat ure, may be obt ained from:
I nt el Corporat ion
P. O. Box 5937
Denver, CO 80217- 9808
or call in Nort h America 1- 800- 548- 4725, Europe 44- 0- 1793- 431- 155, France 44- 0- 1793- 421- 777, Germany 44- 0- 1793- 421- 333, ot her Count ries 708-
296- 9333.
I nt el and I nt el logo are t rademarks or regist ered t rademarks of I nt el Corporat ion or it s subsidiaries in t he Unit ed St at es and ot her count ries.
* Ot her names and brands may be claimed as t he propert y of ot hers.
Copyright 2010, I nt el Corporat ion. All Right s Reserved.
iii
Dat asheet 82578 GbE PHY
Cont ent s
1. 0 I nt r oduct i on .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 1
1. 1 Scope .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 1
1. 2 Overview . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 1
1. 3 Main Flows . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 2
1. 4 References . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 3
1. 5 Product Codes. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 3
1. 6 Product Mat rix .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 4
2.0 I nt er connect s .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 5
2. 1 I nt roduct ion . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 5
2. 2 PCI e- Based .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 5
2. 2.1 PCI e I nt erface Signals.. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 5
2. 2.2 PCI e Operat ion and Channel Behavior . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 6
2. 3 SMBus . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 6
2. 3.1 Overview . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 6
2. 4 Transit ions bet ween SMBus and PCI e int erfaces . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 8
2. 4.1 Swit ching from SMBus t o PCI e . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 8
2. 4.2 Swit ching from PCI e t o SMBus . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . 8
2. 5 I nt el 5 Series Express Chipset / 82578 SMBus/ PCI e I nt erconnect s.. .. .. .. . .. .. .. .. .. .. .. .. . 9
3.0 Pi n I nt er f ace . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 11
3. 1 Pin Assignment . .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 11
3. 1.1 Signal Type Definit ions. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 11
3. 1.2 PCI e I nt erface Pins ( 8) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 12
3. 1.3 SMBus I nt erface Pins ( 2) . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 12
3. 1.4 Miscellaneous Pins ( 3) .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 12
3. 1.5 PHY Pins ( 14) . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 13
3. 1. 6 Test abilit y Pins ( 5) .. . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . .. . . . . . 14
3. 1.7 Power Pins ( 13) .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 14
3. 1.8 LVR Power and Cont rol Pins ( 3) .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 14
4.0 Pack age.. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 15
4. 1 Package Type and Mechanical .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 15
4. 2 Package Elect rical and Thermal Charact erist ics . . . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 16
4. 3 Power and Ground Requirement s. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 17
4. 4 Pinout s ( Top View, Pins Down) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 18
4. 5 Ball Mapping. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 19
5.0 I ni t i al i zat i on .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 21
5. 1 Power Up . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 21
5. 2 Reset Operat ion .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 23
5. 3 Timing Paramet ers . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 24
5. 3.1 Timing Requirement s . .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 24
5. 3.2 Timing Guarant ees .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 24
6.0 Pow er Management and Del i v er y .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 25
6. 1 Power Target s. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 25
6. 2 Power Delivery.. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 26
6. 2.1 2. 5 Vdc and 1. 8 Vdc Supply . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 26
6. 2.2 1. 2 Vdc Supply . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 26
6. 3 Power Management .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 26
6. 3.1 Global Power St at es. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 26
6. 4 Power Saving Feat ures.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 28
6. 4. 1 I nt el
Aut o Connect Bat t ery Saver ( ACBS) . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 28

6. 4.2 Aut omat ic Link Downshift .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 28
82578 GbE PHYDat asheet
iv
7.0 Dev i ce Funct i onal i t y . .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 33
7.1 Tx Flow .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 33
7.2 Rx Flow .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 33
7.3 Flow Cont rol .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 33
7.3.1 MAC Cont rol Frames and Recept ion of Flow Cont rol Packet s.. .. .. .. .. .. . .. .. .. .. .. .. . 34
7.3.2 Transmit t ing PAUSE Frames . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 35
7.4 Wake Up .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 35
7.4.1 Host Wake Up . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 36
7.4.2 Accessing The 82578s Wake Up Regist er Using MDI C. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 44
7.5 PHY Loopback . .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 45
8.0 Pr ogr ammer s Vi si bl e St at e . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 47
8.1 Terminology .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 47
8.2 MDI O Access. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 48
8.3 Addressing.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 48
8.4 Address Map . .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 49
8.5 PHY Regist ers ( Page 0) .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 51
8.5.1 Ext ended Debug Port Regist ers. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 65
8.6 Port Cont rol Regist ers ( Page 769) .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 68
8.7 St at ist ics Regist ers . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 69
8.8 PCI e Regist ers. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 71
8.9 General Regist ers .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 73
8.9.1 I nt errupt s.. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 75
8.10 Wake Up Regist ers. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 76
8.10.1 Accessing Wake Up Regist ers Using MDI C . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 76
8.10.2 Host Wake Up Cont rol St at us Regist er Descript ion.. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 77
9.0 Non- Vol at i l e Memor y ( NVM) . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 87
9.1 I nt roduct ion .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 87
9.2 NVM Programming Procedure Overview .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 87
9.3 LAN NVM Format and Cont ent s . .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 89
9.3.1 Hardware Accessed Words . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 90
9.3.2 Soft ware Accessed Words .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 99
9.3.3 Basic Configurat ion Soft ware Words .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 104
9.4 I nt el
5 Series Express Chipset / 82578 NVM Cont ent s.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 106

10.0 I nt el
5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace.. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 107

10. 1 Regist er Byt e Ordering .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 107
10. 2 Regist er Convent ions .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 108
10. 2.1 PCI Configurat ion and St at us Regist ers - CSR Space. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 109
11.0 El ect r i cal and Ti mi ng Speci f i cat i ons . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 161
11. 1 I nt roduct ion .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 161
11. 2 Operat ing Condit ions. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 161
11. 2.1 Absolut e Maximum Rat ings .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 161
11. 2.2 Recommended Operat ing Condit ions . .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 162
11. 2.3 ESD Specificat ions . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 162
11. 3 Power Delivery .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 162
11. 3.1 Volt age Regulat or Power Supply Specificat ions .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 163
11. 3.2 Power On/ Off Sequence.. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 165
v
11. 4 I / O DC/ AC Paramet ers .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 165
11. 4. 1 3. 3 Vdc DC/ I O .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 165
11. 4. 2 2. 5 Vdc/ I O . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 166
11. 4. 3 I nput Buffer Only .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 167
11. 4. 4 SMBus AC I / O. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 168
11. 4. 5 PCI e DC/ AC Specificat ions . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 168
11. 5 Discret e/ I nt egrat ed Magnet ics Specificat ions. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 171
11. 6 Oscillat or/ Cryst al Specificat ions. .. . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . 172
12.0 Schemat i c and Boar d Layout Check l i st s . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 175
13. 0 Ref er ence Schemat i cs .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 177
14.0 Model s .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 179
82578 GbE PHYDat asheet
vi
Rev i si on Hi st or y
Dat e Rev i si on Descr i pt i on
June 2010 2. 3
Updat e t it le page.
Updat ed sect ion 10. 3. 1. 10 ( bit 13 descript ion) .
Added new values t o sect ion 12. 4. 2 ( VI H) .
Removed old sect ion 8.
Updat ed sect ion 10. 3. 1. 11 ( bit 12 and 13 desct ipt ions) .
February 2010 2. 2
Updat ed figure 1.
Updat ed t able 2.
Updat ed sect ion 7. 4 and 10. 3. 1. 2 ( added I nt el 5 Series Express Chipset references) .
Added power sequencing not e t o sect ion 5. 3. 2.
Updat ed sect ion 6. 4. 2. 2 ( added Windows* 7 reference) .
Updat ed sect ions 7. 4. 1. 3. 1. 4 t hrough 7. 4. 1. 3. 1. 7 and 7. 4. 1. 3. 2. 1 t hrough 7. 4. 1. 3. 2. 2
( swapped Possible VLAN Tag and Possible Len/ LLC/ SNAP Header in t he t ables) .
Added a not e t o sect ion 10. 3. 1. 15 ( LED behaviour) .
November 2009 2. 1
Updat ed power consumpt ion t arget s in sect ion 6.
Updat ed t he NVM format and cont ent s t o mat ch current NVM image.
Added a PHY funct ionalit y sect ion.
Updat ed t he recommended operat ing condit ions in sect ion 12.
June 2009 2. 0 I nit ial Public Release.
May 2009 1. 75 Maj or revision ( all sect ions) .
April 2009 1. 0
Updat ed t it le page ( advanced cable diagnost ics) .
Added new Sect ion I nt el 5 Series Express Chipset / 82578 SMBus/ PCI e I nt erconnect s.
Added SMBus specificat ion reference t o sect ion 1. 5.
Updat ed pad size in sect ion 4. 1.
Changed int ernal pin name from LAN_PWR_GOODn t o LAN_DI SABLE_N ( all sect ions) .
Added new Sect ion Device Funct ionalit y.
Added new Sect ion MAC Programming I nt erface.
Added Appendix A, B, and C.
Updat ed Sect ion 11. 6.
January 2009 0. 98 Updat ed sect ion 7. 3. 2 - removed power on/ off sequence diagram.
December 2008 0. 97 Updat ed t ables 7 and 8 - added LAN disable est imat ed power numbers.
December 2008 0. 96 Updat ed t ables 7 and 8 ( lat est power numbers) .
Sept 2008 0. 95
Sect ion 2. 2. 2 ( Removed last paragraph and Table 2) .
Sect ion 2. 3 ( changed SMBCLK t o SMB_CLK and SMBDATA t o SMB_DATA) .
Sect ion 2. 3. 1 ( updat ed paragraph) .
Sect ion 2. 3. 1. 6 ( Removed) .
Removed old sect ions 2. 3. 1. 6. 1, 2. 3. 1. 6. 2, and 2. 3. 1. 7) .
Sect ion 2. 3. 2. 2. 1 ( updat ed t able) .
Sect ion 4. 1 ( added new mechanical drawing and pad size values) .
Sect ion 5. 3. 2 ( changed T
XTAL
paramet er t o 35 ms) .
Sect ion 6. 3. 1. 1 ( updat ed paragraph) .
Sect ion 6. 3. 1. 2 ( removed all mode 1 references and updat ed regist er references) .
Sect ion 6. 3. 1. 3 ( added K1 I dle St at e informat ion) .
Sect ion 6. 3. 2 ( changed KX t o K0) .
Sect ion 6. 3. 3 ( updat ed regist er references) .
Sect ion 6. 4 ( new sect ion) .
Sect ion 7. 2. 1 ( added not es following t able) .
July 2008 0. 9
Added new sect ion 8. 0 Non-Volat ile Memory ( NVM) .
Added sect ion 6. 4 Power Saving Feat ures.
Updat ed sect ion 6. 1 Power Target s.
Updat ed sect ion 3. 1. 7 Power Pins.
Updat ed sect ion 3. 1. 5. 2 Analog Pins.
May 2008 0. 81 Updat ed pin descript ion in Figure 3 and Sect ion 4. 5.
vii
May 2008 0. 8
Updat ed Tables 7 and 8 ( added new power numbers) .
Updat ed Sect ions 3. 1. 7 and 3. 1. 8 ( clarified power, LVR, and cont rol pins) .
Updat ed Sect ion 4. 1 ( Added Epad size specificat ions) .
Updat ed Figure 1 ( removed ferrit e beads from diagram) .
Updat ed Sect ions 1. 2 ( added not e) , 2. 2 ( added not e) , 2. 3 ( added not e) , and 7. 2. 2.
April 2008 0. 7 Added a discret e/ int egrat ed magnet ics specificat ions t able t o Sect ion 7. 0.
Mar 2008 0. 6 Maj or revision ( all sect ions) .
Jan 2008 0. 5 I nit ial release ( I nt el Confident ial) .
Dat e Rev i si on Descr i pt i on
82578 GbE PHYI nt r oduct i on
1
1. 0 I nt r oduct i on
1.1 Scope
This document describes t he ext ernal archit ect ure for t he 82578. I t ' s int ended t o be a
reference for soft ware developers of device drivers, board designers, t est engineers, or
anyone else who might need specific t echnical or programming informat ion about t he
82578.
1.2 Over vi ew
The 82578 is a single port Gigabit Et hernet Physical Layer Transceiver ( PHY) . I t
connect s t o t he I nt el
5 Series Express Chipset int egrat ed Media Access Cont roller

( MAC) t hrough a dedicat ed int erconnect . The 82578 support s operat ion at 1000/ 100/
10 Mb/ s dat a rat es. The PHY circuit ry provides a st andard I EEE 802. 3 Et hernet
int erface for 1000BASE-T, 100BASE-TX, and 10BASE-T applicat ions ( 802. 3, 802. 3u,
and 802. 3ab) .
The 82578 is packaged in a small foot print QFN package. Package size is 6 x 6 mm wit h
a 0. 4 mm lead pit ch and a height of 0. 85 mm, making it very at t ract ive for small form-
fact or plat forms.
The 82578 int erfaces wit h it s MAC t hrough t wo int erfaces: PCI e- based and SMBus. The
PCI e ( main) int erface is used for all link speeds when t he syst em is in an act ive st at e
( S0) while t he SMBus is used only when t he syst em is in a low power st at e ( Sx) . I n
SMBus mode, t he link speed is reduced t o 10 Mb/ s ( dependent on low power opt ions) .
The PCI e int erface incorporat es t wo aspect s: a PCI e SerDes ( elect rically) and a cust om
logic prot ocol.
Not e: The 82578 PCI e int erface is not PCI e compliant . I t operat es at half of t he PCI Express*
( PCI e* ) Specificat ion v1. 1 ( 2. 5 GT/ s) speed. I n t his dat asheet t he t erm PCI e- based is
int erchangeable wit h PCI e. There is no design layout differences bet ween normal PCI e
and t he 82578s PCI e- based int erface.
2
I nt r oduct i on82578 GbE PHY
Fi gur e 1. 82578 Bl ock Di agr am
1.3 Mai n Fl ow s
The 82578 main int erfaces are PCI e and SMBus on t he host side and t he MDI int erface
on t he link side. Transmit t raffic is received from t he MAC device t hrough eit her PCI e or
SMBus on t he host int erconnect and t hen t ransmit t ed on t he MDI link. Receive t raffic
arrives on t he MDI link and t ransferred t o t he MAC t hrough eit her t he PCI e or SMBus
int erconnect s.
The MAC and syst em soft ware cont rol t he 82578 funct ionalit y t hrough t wo
mechanisms:
The 82578 configurat ion regist ers are mapped int o t he MDI O space and can be
accessed by t he MAC t hrough t he PCI e or SMBus int erconnect s.
The MDI O t raffic is embedded in specific fields in SMBus packet s or carried by
special packet s over t he PCI e encoded int erconnect as defined by t he cust om
prot ocol.
Specific flows are described in ot her sect ions of t his document :
Power delivery opt ions are described in Sect ion 4.3.
Power management is described in Sect ion 6.3.
PHY
SMBus PCI e
Mul t i pl ex er
PLL
LEDs
SMBus PCI e
Cr y st al
Test abi l i t y
MDI
Gb E PHY
/ GMI I
MDI O
St at us & Cont r ol
Power
Suppl y
Power
Fi l t er
RX MAC
Host
Wak e Up
82578 GbE PHYI nt r oduct i on
3
1.4 Ref er ences
I nformat ion Technology - Telecommunicat ion & I nformat ion Exchange Bet ween
Syst ems - LAN/ MAN - Specific Requirement s - Part 3: Carrier Sense Mult iple Access
wit h Collision Det ect ion ( CSMA/ CD) Access Met hod and Physical Layer
Specificat ions, I EEE St andard No. : 802. 3- 2002
I nt el Et hernet Cont rollers Loopback Modes, I nt el Corporat ion
SMBus specificat ion revision 2. 0.
I nt el
5 Series Express Chipset Family Ext ernal Design Specificat ion ( I nt el
5
Series Express Chipset EDS) , I nt el Corporat ion
I nt el

5 Series Express Chipset Ext ernal Dat asheet Specificat ion, I nt el Corporat ion
I nt el
5 Series Express Chipset SPI Flash Programming Guide - Applicat ion Not e,
I nt el Corporat ion
I nt el
82578 Schemat ic and Layout Checklist s, I nt el Corporat ion

I nt el
82578 MDI Different ial Trace and Power Loss Calculat ors, I nt el Corporat ion
1.5 Pr oduct Codes
Table 1 list s t he product ordering codes for t he 82578 GbE cont roller. Refer t o t he
I nt el
82578 GbE PHY Specificat ion Updat e for device ordering informat ion.
Tabl e 1. Pr oduct Or der i ng Codes
Dev i ce Mar k et Segment Pr oduct Code
82578DM
Corporat e deskt op and
workst at ion
WG82578DM
82578DC Consumer deskt op WG82578DC
4
I nt r oduct i on82578 GbE PHY
1. 6 Pr oduct Mat r i x
Method of enabling/disabling features in SKUs
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*

Desktop Corporate
82578 for
Corporate
10EF X X X X X X X X X X X X X
Desktop Consumer
82578 for
Consumer
10F0 X X X X X X
Gigabit
Performance Extended
82578 GbE PHYI nt er connect s
5
2.0 I nt er connect s
2.1 I nt r oduct i on
The 82578 implement s t wo int erconnect s t o t he MAC:
PCI e - A high- speed SerDes int erface using PCI e elect rical signaling at half speed
while keeping t he cust om logical prot ocol for act ive st at e operat ion mode.
Syst em Management Bus ( SMBus) A very low speed connect ion for low power
st at e mode for manageabilit y communicat ion only. At t his low power st at e mode
t he Et hernet link speed is reduced t o 10 Mb/ s.
.
The 82578 aut omat ically swit ches t he inband t raffic bet ween PCI e and SMBus based
on t he syst em power st at e.
2.2 PCI e- Based
Not e: The 82578 PCI e int erface is not PCI e compliant . I t operat es at half of t he PCI Express*
( PCI e* ) Specificat ion v1. 1 ( 2. 5 GT/ s) speed. I n t his dat asheet t he t erm PCI e- based is
int erchangeable wit h PCI e. There is no design layout differences bet ween normal PCI e
and t he 82578s PCI e- based int erface. St andard PCI e validat ion t ools cannot be used t o
validat e t his int erface.
2. 2. 1 PCI e I nt er f ace Si gnal s
The signals used t o connect bet ween t he MAC and t he PHY in t his mode are:
Serial different ial pair running at 1. 25 Gb/ s for Rx
Serial different ial pair running at 1. 25 Gb/ s for Tx
100 MHz different ial clock input t o t he PHY running at 100 MHz
Power and clock good indicat ion t o t he PHY PE_RST_N pin
Clock cont rol t hrough CLK_REQ_N pin
Tabl e 2. 82578 I nt er connect Modes
Sy st em
PHY
SMBus PCI e
S0 and PHY Power Down Not used I dle
S0 and I dle or Link Disc Not used I dle
S0 and act ive Not used Act ive
Sx Act ive Power down
Sx and DMoff Act ive Power down
6
I nt er connect s82578 GbE PHY
2.2.2 PCI e Oper at i on and Channel Behavi or
The 82578 only runs at 1250 Mb/ s speed, which is 1/ 2 of t he PCI e Specificat ion v1. 1,
2.5 Gb/ s PCI e frequency. Each of t he PCI e root port s in t he I nt el
5 Series Express
Chipset - int egrat ed MAC have t he abilit y t o operat e wit h t he 82578. The port
configurat ion is pre- loaded from t he NVM. The select ed port adj ust s t he t ransmit t er t o
run at t he 1.25 GHz rat e and does not need t o be PCI e compliant .
Packet s t ransmit t ed and received over t he PCI e int erface are full Et hernet packet s and
not PCI e t ransact ion/ link/ physical layer packet s.
Aft er t he PCI e power- up sequence complet es, each t ransmit t er st art s t ransmit t ing idle
symbols and t he receiver acquires synchronizat ion as specified in 802. 3z.
2. 3 SMBus
Not e: The 82578 SMBus must only be connect ed t o SMLink0 in t he I nt el
5 Series Express
Chipset . No ot her device ( like an ext ernal BMC) can be connect ed t o SMLink0 when t he
82578 is connect ed t o t he I nt el
5 Series Express Chipset SMLink0.

2.3.1 Ov er v i ew
SMBus is used as an int erface t o pass t raffic bet ween t he 82578 and t he I nt el
5 Series
Express Chipset when t he syst em is in a low power st at e ( Sx st at e) . The int erface is
also used t o enable t he I nt el
5 Series Express Chipset t o configure t he 82578 as well

as passing inband informat ion bet ween t hem.
The SMBus uses t wo primary signals: SMB_CLK and SMB_DATA t o communicat e. Bot h
of t hese signals float high wit h board- level pull- ups.
The SMBus specificat ion has defined various t ypes of message prot ocols composed of
individual byt es. The message prot ocols support ed by t he 82578 are described in t he
relevant sect ions.
For more det ails about SMBus, see t he SMBus specificat ion.
2.3.1.1 SMBus Channel Behav i or
The SMBus specificat ion defines t he maximum frequency of t he SMBus as 100 KHz.
2.3.1.2 SMBus Addr essi ng
The 82578s address is assigned using SMBus ARP prot ocol. The default SMBus address
is 0xC8.
7
2. 3.1. 3 Bus Ti meout s
The 82578 can det ect ( as a mast er or a slave) an SMB_CLK t imeout on t he main
SMBus. I f t he SMBus clock line is held low for 25 ms, t he 82578 abort s t he t ransact ion.
As a slave, t he 82578 det ect s t he t imeout and goes int o an idle st at e. I n idle, t he slave
releases t he SMB_CLK and SMB_DATA lines. Any dat a t hat was received before t he
t imeout might have been processed depending on t he t ransact ion.
As a mast er, t he 82578 det ect s a t imeout and issues a STOP on t he SMBus at t he next
convenient opport unit y and t hen brings t he SMBus back t o idle ( releases SMB_CLK and
SMB_DATA) . Any mast er t ransact ion t hat t he 82578 det ect s a t imeout on is abort ed.
2. 3.1. 4 Bus Hangs
Alt hough uncommon, SMBus bus hangs can happen in a syst em. The reason for t he
hang is t ypically an unexpect ed, asynchronous reset or noise coupled ont o t he SMBus.
Slaves can cont ribut e t o SMBus hangs by not implement ing t he SMBus t imeout s as
specified in SMBus 2. 0 specificat ion. Mast ers or host mast ers can cont ribut e t o SMBus
hangs by not det ect ing t he failures and by not at t empt ing t o correct t he bus hangs.
Because of t he pot ent ial bus hang scenario, t he 82578 has t he capabilit y of det ect ing a
hung bus. I f SMB_CLK or SMB_DATA are st uck low for more t han 35 ms, t he 82578
forces t he bus t o idle ( bot h SMB_CLK and SMB_DATA set ) if it is t he cause of t he bus
hang.
2. 3.1. 5 Pack et Er r or Code ( PEC) Suppor t
PEC is defined in t he SMBus 2.0 specificat ion. I t is an ext ra byt e at t he end of t he
SMBus t ransact ion, which is a CRC- 8 calculat ed on all of t he preceding byt es ( not
including ACKs, NACKs, STARTs, or STOPs) in t he SMBus t ransact ion. The polynomial
for t his CRC- 8 is:
x8 + x2 + x + 1
The PEC calculat ion is reset when any of t he following occurs:
A STOP condit ion is det ect ed on t he host SMBus
An SMBus hang is det ect ed on t he host SMBus
The SMB_CLK is det ect ed high for ~ 50 s
8
2.3.1.6 SMBus ARP Funct i onal i t y
The 82578 doesnt support ARP prot ocol.
2.4 Tr ansi t i ons bet w een SMBus and PCI e i nt er f aces
2.4.1 Sw i t chi ng f r om SMBus t o PCI e
Communicat ion bet ween t he MAC and t he 82578 is done t hrough t he SMBus each t ime
t he syst em is in a low power st at e ( Sx) ; PE_RST_N signal is low. The MAC/ PHY
int erface is needed t o enable host wake up from t he 82578.
Possible st at es for act ivit y over t he SMBus:
1. Aft er power on ( G3 t o S5) .
2. On syst em st andby ( Sx) .
While in t his st at e, t he SMBus is used t o t ransfer t raffic, configurat ion, cont rol and
st at us bet ween t he MAC and t he 82578.
The swit ching from t he SMBus t o PCI e is done when t he PE_RST_N signal is high.
Any t ransmit / receive packet t hat is not complet ed when PE_RST_N is assert ed is
discarded.
Any inband message t hat was sent over t he SMBus and was not acknowledged is
re- t ransmit t ed over PCI e.
2.4.2 Sw i t chi ng f r om PCI e t o SMBus
The communicat ion bet ween t he MAC and t he 82578 is done t hrough PCI e each t ime
t he syst em is in act ive power st at e ( S0) ; PE_RST_N signal is high. Swit ching t he
communicat ion t o SMBus is only needed t o enable host wake up in low power st at es
and is cont rolled by t he I nt el 5 Series Express Chipset .
The swit ching from PCI e t o SMBus is done when t he PE_RST_N signal is low.
Any t ransmit / receive packet t hat is not complet ed when PE_RST_N goes t o 0b is
discarded.
Any inband message t hat was sent over PCI e and was not acknowledged is re-
t ransmit t ed over SMBus.
9
2.5 I nt el 5 Ser i es Ex pr ess Chi pset / 82578 SMBus/ PCI e
I nt er connect s
The 82578 can be connect ed t o any x1 PCI e port in I nt el
5 Series Express Chipset .

The PCI e port t hat connect s t o t he 82578 is select ed by PCHSTRP9, bit s [ 11: 8] in t he
SPI Flash descript or region. For more informat ion on t his set t ing, please refer t o t he
I nt el

5 Series Express Chipset Ext ernal Dat asheet Specificat ion. The I nt el
5 Series
Express Chipset - t o- 82578 PCI e port connect ion in t he reference schemat ic must mat ch
t he previously ment ioned I nt el
5 Series Express Chipset SPI st rap set t ing. Choosing

anot her port can result in unexpect ed syst em behavior.
The SMBus/ PCI e int erface can be configured in as shown Figure 2.
Not es:
1. Any free PCI e port s ( port s 1- 8) can be used t o connect t o t he 82578 PCI e I nt erface.
2. Any CLKOUT_PCI E[ 7: 0] and PCI ECLKRQ[ 7: 0] can be used t o connect t o PE_CLK for t he 82578.
3. PETp/ n, PERp/ n, PE_CLKp/ n should be rout ed as different ial pair as per t he PCI e specificat ion.
Fi gur e 2. I nt el 5 Ser i es Ex pr ess Chi pset / 82578 I nt er connect s
Intel 5 Series
PETp[8:1]
PETn[8:1]
PERp[8:1]
PERn[8:1]
Intel PHY
PERp
PERn
PETp
PETn
100nF
100nF
100nF
100nF
+V3.3A
PCIe
2.2k
5%
SMBus
CLKOUT_PCIE[7:0]P
SML0DATA
SML0CLK
SMBDATA
SMBCLK
CLKOUT_PCIE[7:0]N
PCIECLKRQ[7:0]#
PE_CLKP
PE_CLKN
CLK_REQ_N
0 ohm
EMPTY
LAN_DISABLE_N
LAN_PHY_PWR_CTRL/
GPIO12
10k
+V3.3M_LAN
10k
EMPTY
2.2k
5%
10k
+V3.3A
10
Not e: This page int ent ionally left blank.
82578 GbE PHYPi n I nt er f ace
11
3. 0 Pi n I nt er f ace
3.1 Pi n Assi gnment
The 82578 is packaged in a 48- pin package, 6 x 6 mm wit h a 0.4 mm lead pit ch. There
are 48 pins on t he periphery and a die pad ( Exposed Pad* ) for ground.
Not e: Refer t o t he reference schemat ics for pin connect ion det ails. Cont act your I nt el
represent at ive for access.
3.1.1 Si gnal Ty pe Def i ni t i ons
Si gnal Ty pe Def i ni t i on
I n I nput is a st andard input - only signal.
I A st andard input - only signal.
Out ( O) Tot em pole out put is a st andard act ive driver.
T/ s Tri- st at e is a bi- direct ional, t ri- st at e input / out put pin.
S/ t / s
Sust ained t ri- st at e is an act ive low t ri- st at e signal owned and driven by one and only one
agent at a t ime. The agent t hat drives an s/ t / s pin low must drive it high for at least one
clock before let t ing it float . A new agent cannot st art driving an s/ t / s signal any sooner t han
one clock aft er t he previous owner t ri- st at es it .
O/ d Open drain enables mult iple devices t o share as a wire- OR.
Analog Analog input / out put signal.
A- in Analog input signal.
A- out Analog out put signal.
B I nput bias
12
Pi n I nt er f ace82578 GbE PHY
3. 1. 2 PCI e I nt er f ace Pi ns ( 8)
3.1.3 SMBus I nt er f ace Pi ns ( 2)
3. 1. 4 Mi scel l aneous Pi ns ( 3)
Pi n Name Pi n # Ty pe Op Mode Name and Funct i on
PE_RST_N 36 I I nput PCI e reset .
PETp
PETn
38
39
A- out Out put PCI e Tx.
PERp
PERn
41
42
A- in I nput PCI e Rx.
PE_CLKP
PE_CLKN
44
45
A- in I nput PCI e clock.
CLK_REQ_N 48 O/ d Out put
Clock request . Connect t o VCC3P3 t hrough a 10 K pullup
resist or.
Pi n Name Pi n # Type Op Mode Name and Funct i on
SMB_CLK 28 O/ d BI - dir
SMBus clock. Pull t his signal up t o 3. 3 Vdc ( auxiliary supply
1
)
t hrough a 2. 2 K resist or ( while in Sx mode) .
SMB_DATA 31 O/ d BI - dir
SMBus dat a. Pull t his signal up t o 3. 3 Vdc ( auxiliary supply) t hrough
a 2. 2 K resist or ( while in Sx mode) .
1. AUX power means t he power rail is available in all power st at es including G3 t o S5 t ransit ions and Sx st at es
wit h Wake on LAN ( WoL) enabled.
RSVD1_VCC3P3 1 T/ s Connect t o VCC3P3 t hrough a 5%, 3. 01 K resist or.
RSVD2_VCC3P3 2 T/ s Connect t o VCC3P3 t hrough a 5%, 3. 01 K resist or.
LAN_DI SABLE_N 3 I Not e: When t his pin is set t o 0b, t he 82578 is disabled.
82578 GbE PHYPi n I nt er f ace
13
3.1.5 PHY Pi ns ( 14)
3.1.5.1 LEDs ( 3)
This t able list s t he funct ionalit y of t he LED out put pins. Refer t o t he I nt el
5 Series
Family Plat form Design Guide ( PDG) for LED connect ion det ails.
3. 1.5. 2 Anal og Pi ns ( 11)
LED0 26 O Out put
This signal is used for t he programmable LED
( LI NK_LI NK/ ACTI VI TY) .
LED1 27 O Out put
( LI NK_1000) .
LED2 25 O Out put
( LI NK_100) .
Pi n Name Pi n# Ty pe Op Mode Name and Funct i on
MDI _PLUS[ 0]
MDI _MI NUS[ 0]
13
14
Analog Bi- dir
Media Dependent I nt erface[ 0]
1000BASE- T: I n MDI configurat ion, MDI [ 0] + / - corresponds t o
BI _DA+ / - and in MDI -X configurat ion MDI [ 0] + / - corresponds t o
BI _DB+ / - .
100BASE- TX: I n MDI configurat ion, MDI [ 0] + / - is used for t he
t ransmit pair and in MDI -X configurat ion MDI [ 0] + / - is used for
t he receive pair.
10BASE- T: I n MDI configurat ion, MDI [ 0] + / - is used for t he
t ransmit pair and in MDI -X configurat ion MDI [ 0] + / - is used for
t he receive pair.
MDI _PLUS[ 1]
MDI _MI NUS[ 1]
17
18
Analog Bi- dir
Media Dependent I nt erface[ 1]
1000BASE- T: I n MDI configurat ion, MDI [ 1] + / - corresponds t o
BI _DB+ / - and in MDI -X configurat ion MDI [ 1] + / - corresponds t o
BI _DA+ / - .
100BASE- TX: I n MDI configurat ion, MDI [ 1] + / - is used for t he
receive pair and in MDI -X configurat ion MDI [ 1] + / - is used for t he
t ransmit pair.
10BASE- T: I n MDI configurat ion, MDI [ 1] + / - is used for t he
receive pair and in MDI -X configurat ion MDI [ 1] + / - is used for t he
t ransmit pair.
MDI _PLUS[ 2]
MDI _MI NUS[ 2]
MDI _PLUS[ 3]
MDI _MI NUS[ 3]
20
21
23
24
Analog Bi- dir
Media Dependent I nt erface[ 3: 2]
1000BASE- T: I n MDI configurat ion, MDI [ 3: 2] + / - corresponds t o
BI _DA+ / - and in MDI -X configurat ion MDI [ 3: 2] + / - corresponds t o
BI _DB+ / - .
100BASE- TX: Unused.
10BASE- T: Unused.
XTAL_OUT 9 O Out put cryst al.
XTAL_I N 10 I I nput cryst al.
RBI AS 12 Analog Connect t o ground t hrough a 2. 37 K + / - 1%.
14
Pi n I nt er f ace82578 GbE PHY
3. 1. 6 Test abi l i t y Pi ns ( 5)
Not e: The 82578 uses t he JTAG int erface t o support XOR files for manufact uring t est . BSDL is
not support ed.
3.1.7 Pow er Pi ns ( 13)
3.1.8 LVR Pow er and Cont r ol Pi ns ( 3)
JTAG_TCK 35 I n I nput JTAG clock input .
JTAG_TDI 32
I n
PU
I nput JTAG TDI input .
JTAG_TDO 34 T/ s Out put JTAG TDO out put .
JTAG_TMS 33
I n
PU
I nput JTAG TMS input .
TEST_EN 30 I n I nput
Should be connect ed t o ground t hrough a 1 K resist or, when
connect ed t o logic 1b and t est mode is enabled.
Pi n Name Pi n # Ty pe Name and Funct i on
AVDD1P2
8, 11, 16, 22,
40, 43
Power 1. 2 Vdc supply.
AVDD1P2 8 Power 1. 2 Vdc sense feedback.
AVDD2P5 15, 19 Power 2. 5 Vdc supply.
DVDD1P2 37, 46, 47 Power 1. 2 Vdc supply; connect ed t o DVDD using 0 0805 resist ors.
DVDD2P5 29 Power 2. 5 Vdc supply t o I / O.
VDD3P3_I N 5 Power 3. 3 Vdc supply.
VDD2P5_OUT 4 Power 2. 5 Vdc out .
Pi n Name Pi n # Ty pe Name and Funct i on
CTRL1P2 7 Analog Connect t o t he base of t he PNP.
VCT 6 Analog
Regulat or out put ; connect t o 1. 8 Vdc supply and a cent er t ap, 1 F
capacit or.
82578 GbE PHYPack age
15
4. 0 Pack age
4.1 Pack age Ty pe and Mechani cal
The 82578 is a 6 mm x 6 mm, 48- pin QFN Halogen Free, Pb Free package wit h a pad
size of 3.80 mm x 3. 80 mm.
Fi gur e 3. Pack age Di mensi ons
0.156 3.65 3.80 3.95 0.144 0.150
Controlling Dimension - Millimeter
Reference Document - JEDEC MO-220
Tolerance Requirement for D1/E1: +/- 0.1 mm
Notes:
16
Pack age82578 GbE PHY
4. 2 Pack age El ect r i cal and Ther mal Char act er i st i cs
The t hermal resist ance from j unct ion t o case, qJC, is 15. 1 C/ Wat t .
The t hermal resist ance from j unct ion t o ambient , qJA, is as follows: 4- layer PCB, 85
degrees ambient .
No heat sink is required.
Ai r Fl ow ( m/ s) Max i mum T
J
qJA ( C/ Wat t )
0 119 34
1 118 33
2 116 31
17
4.3 Pow er and Gr ound Requi r ement s
The 82578 requires t hree power supplies plus one int ernal power rail t hat is brought
out for decoupling. Figure 4 shows a t ypical power delivery configurat ion t hat can be
implement ed.
Not e: Power delivery can be cust omized based on a specific OEM plat form configurat ion.
Fi gur e 4. 82578 Pow er Del i ver y Di agr am
82578
CTRL1p2
R1
R2
R3
C1
C2
C4
1.2v
Q1
BCP69
C6 C5
43
22
R4
C3
C7
C8 C9
6
2.5v
4
7
2.5v
15, 19
2.5v
29
3.3VDD
5
8,11,16,40
37,46,47
1.2v
2.37 Kohm 1%
12
Center Tap
Magnetic
1uf
XTAL1
10
9
27pF
27pF
C1, C2,C5 X5R 10 uF 6.3V
C8, C9 X5R 4.7uF 6.3V
C6, C3, C4 100 nF
R1 (4.99 Kohm)
R3 (0 ohm 0805) Do Not Populate
R4 (0 ohm)
C7 (0.01 uF) Do Not Populate
R2 and R5 (0 ohm 0805)

1.2V
1.2V
1.2V
1.2V
1uf
+3.3V LAN
+3.3V LAN
Do Not Populate
Do Not Populate
R5
49
VCT
18
4.4 Pi nout s ( Top Vi ew , Pi ns Dow n)
Fi gur e 5. 82578 Pi nout s
38 39 40 41 42 43 44 45 46 47 48
82578
48 Pin QFN
6 mm x 6 mm
0.4 mm pin pitch
with Exposed Pad*
2
P
1
D
D
V
D
N
_
Q
E
R
_
K
L
C
2
P
1
D
D
V
D
2
P
1
D
D
V
D
N
K
L
C
_
E
P
P
K
L
C
_
E
P
2
P
1
D
D
V
A
n
R
E
P
p
R
E
P
2
P
1
D
D
V
A
n
T
E
P
p
T
E
P
]
0
[
S
U
L
P
_
I
D
M
]
3
[
S
U
N
I
M
_
I
D
M
]
3
[
S
U
L
P
_
I
D
M
2
P
1
D
D
V
A
]
2
[
S
U
N
I
M
_
I
D
M
]
2
[
S
U
L
P
_
I
D
M
5
P
2
D
D
V
A
]
1
[
S
U
N
I
M
_
I
D
M
]
1
[
S
U
L
P
_
I
D
M
2
P
1
D
D
V
A
5
P
2
D
D
V
A
]
0
[
S
U
N
I
M
_
I
D
M
PE_RST_N
LED2
LED0
LED1
SMB_CLK
DVDD2P5
TEST_EN
SMB_DATA
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TCK
RSVD_VCC3P3
RBIAS
AVDD1P2
XTAL_IN
XTAL_OUT
AVDD1P2
CTRL_1P2
VCT
VDD3P3_IN
VDD2P5_OUT
LAN_DISABLE_N
36
35
34
33
32
31
30
29
28
25
26
27
1
2
3
4
5
6
7
8
9
10
11
12
37
13 14 15 16 17 18 19 20 21 22 23 24
RSVD_VCC3P3
Pin 1
Pin 49 - VSS_EPAD
19
4.5 Bal l Mappi ng
Pi n Name Si de Pi n Number Pi n Name Si de Pi n Number
RSVD_VCC3P3 Left 1 MDI _PLUS[ 0] Bot t om 13
RSVD_VCC3P3 Left 2 MDI _MI NUS[ 0] Bot t om 14
LAN_DI SABLE_N Left 3 AVDD2P5 Bot t om 15
VDD2P5_OUT Left 4 AVDD1P2 Bot t om 16
VDD3P3_I N Left 5 MDI _PLUS[ 1] Bot t om 17
VCT Left 6 MDI _MI NUS[ 1] Bot t om 18
CTRL1P2 Left 7 AVDD2P5 Bot t om 19
AVDD1P2 Left 8 MDI _PLUS[ 2] Bot t om 20
XTAL_OUT Left 9 MDI _MI NUS[ 2] Bot t om 21
XTAL_I N Left 10 AVDD1P2 Bot t om 22
AVDD1P2 Left 11 MDI _PLUS[ 3] Bot t om 23
RBI AS Left 12 MDI _MI NUS[ 3] Bot t om 24
LED2 Right 25 DVDD1P2 Top 37
LED0 Right 26 PETp Top 38
LED1 Right 27 PETn Top 39
SMB_CLK Right 28 AVDD1P2 Top 40
DVDD2P5 Right 29 PERp Top 41
TEST_EN Right 30 PERn Top 42
SMB_DATA Right 31 AVDD1P2 Top 43
JTAG_TDI Right 32 PE_CLKP Top 44
JTAG_TMS Right 33 PE_CLKN Top 45
JTAG_TDO Right 34 DVDD1P2 Top 46
JTAG_TCK Right 35 DVDD1P2 Top 47
PE_RST_N Right 36 CLK_REQ_N Top 48
VSS_EPAD EPAD 49
20
82578 GbE PHYI ni t i al i zat i on
21
5. 0 I ni t i al i zat i on
5.1 Pow er Up
Fi gur e 6. Pow er Up Sequence
Power up
Internal power on circuit has
detected valid power on input
pins (3.3/2.5/1.2 Vdc)
Strapping are sampled
Internal power on reset is
de-asserted
Internal Xosc stabilizes
Start PCIe training
Send link status message
PHY starts link auto-negotiation
PHY establishes link
MDIO registers are
initialized by the MAC
Start PCIe training
Is PE_RST#
low
Yes No Wait for Intel 5
Series Express Chipset
SMBus address valid
22
I ni t i al i zat i on82578 GbE PHY
Tabl e 3. Fi gur e Not es
Not e
1 Plat form power ramps up ( 3. 3 V dc/ 2. 5/ 1. 2 Vdc)
2 XTAL is st able aft er T
XTAL
sec.
3 I nt ernal Power On Reset t riggers T
POR
aft er XTAL is st able. St rapping opt ions are lat ched.
4 PCI e t raining if PE reset is de- assert ed.
5 Wait for I nt el
5 Series Express Chipset SMBus address valid.

6 Send Link St at us message.
7 MAC configures t he 82578.
8 PHY goes t hrough aut o- negot iat ion t o acquire link.
82578 GbE PHYI ni t i al i zat i on
23
5.2 Reset Oper at i on
The reset sources for t he 82578 are as follows:
I nt er nal Pow er On Reset ( POR) The 82578 has an int ernal mechanism for
sensing t he power pins. Unt il power is up and st able, t he 82578 generat es an
int ernal act ive low reset . This reset act s as a mast er reset for t he 82578. While t he
int ernal reset is 0b, all regist ers in t he 82578 are reset t o t heir default values.
St rapping values are lat ched aft er I nt ernal POR is de- assert ed.
PHY Sof t Reset A PHY reset caused by writ ing t o bit 15 in MDI O regist er 0.
Set t ing t he bit reset s t he PHY, but does not reset non- PHY part s. Soft reset is used
mainly t o program t he PHY t o a different work point wit hout affect ing funct ionalit y
of t he rest of t he device. Once t he PHY complet es it s int ernal reset , a reset
complet e indicat ion is sent t o t he MAC over t he int erconnect . The MAC t hen
configures t he PHY.
Not e: The MAC configures t he PHY regist ers. Ot her t he 82578 regist ers do not need t o be
configured.
PCI e Reset - Aft er assert ing a PCI e reset , t he 82578 st ops t he PCI e int erface and
if in t he middle of t ransmit t ing a packet it will be dropped. De- assert ing PCI e reset
reset s t he int ernal FI FO unless wakeup is act ivat ed and causes a swit ch from
SMBus t o PCI e.
I n- Band Reset - An inband message causing complet e reset of t he 82578 except
t he wake up filt ers cont ent .
The effect of t he various reset opt ions on t hese and ot her regist ers is list ed in Table 4.
Table 4 list s t he impact of each t he 82578 reset .
Tabl e 4. 82578 Reset s
Ef f ect s/
Sour ces
PCI e
I nt er f ace
Non- PHY
Regi st er s
and St at e
PHY
Regi st er s
and St at e
Reset
Compl et e
I ndi cat i on
St r appi ng
Opt i ons
Fuse
Regi st er s
Mov e Out
of Pow er
Dow n
Mode
Wak e Up
Regi st er
I nt ernal
POR
1

PHY Soft
Reset
2

PCI e Reset
I n- Band
Reset

1. Assert ing a 3. 3 Vdc power on reset should move t he PHY out of power down mode.
2. PHY regist ers ( page 0 in MDI O space and any aliases t o page 0) are reset during a PHY soft reset . The rest of
t he 82578s MDI O space is not reset .
24
I ni t i al i zat i on82578 GbE PHY
5.3 Ti mi ng Par amet er s
5. 3. 1 Ti mi ng Requi r ement s
The 82578 requires t he following st art - up and power- st at e t ransit ions.
5. 3.2 Ti mi ng Guar ant ees
The 82578 guarant ees t he following st art - up and power st at e t ransit ion relat ed t iming
paramet ers.
Not e: For plat form power sequencing requirement s for t he I nt el 5 Series Express Chipset
MAC, refer t o t he I nt el 5 Series Express Chipset EDS.
Tabl e 5. Ti mi ng Requi r ement s
Par amet er Descr i pt i on Mi n. Max . Not es
T
r2init
Complet ing a PHY
configurat ion following a
reset complet e indicat ion.
0. 5 s
Tabl e 6. Ti mi ng Guar ant ees
Par amet er Descr i pt i on Mi n Max Not es
T
PHY_Reset
Reset de- assert ion t o PHY
reset complet e
10 ms
PHY configurat ion should be delayed
unt il PHY complet es it s reset .
Tc2an
Cable connect at st art of
aut o- negot iat ion
1. 2 s 1. 3 s Per 802. 3 specificat ion.
82578 GbE PHYPow er Management and Del i v er y
25
6. 0 Pow er Management and Del i v er y
This sect ion describes how power management is implement ed in t he 82578.
6.1 Pow er Tar get s
Table 7 list s t he t arget s for device power for t he 82578. Not e t hat power is reduced
according t o link speed and link act ivit y.
Not e: Device power is t he power dissipat ed by t he 82578.
Tabl e 7. 82578 Pow er Consumpt i on Tar get s Ex t er nal 1. 8 Vdc
1
1. Measured power could be higher or lower based on measurement set up and PHY power delivery configurat ion.
Sy st em St at e Li nk St at e
3. 3 Vdc
Cur r ent
[ mA]
1. 8 Vdc
Cur r ent
[ mA]
1. 2 Vdc
Cur r ent
[ mA]
Dev i ce
Pow er
[ mW]
Sol ut i on
Pow er
( mW)
BCP69
Sol ut i on
S0 Maximum
1000Mb act ive @
90 C [ Ta]
22 193 284 761 1647
S0 Typical
1000 Mb/ s act ive 22 193 282 758 1640
100 Mb/ s act ive 14 43 121 259 587
10 Mb/ s act ive 15 114 72 341 663
1000 Mb/ s idle 22 194 237 706 1495
100 Mb/ s idle 13 42 71 204 416
10 Mb/ s idle 11 1 25 68 122
Cable disconnect 9 0 10 42 63
LAN disable 9 0 14 47 76
Sx
Wake on
LAN ( WoL)
enabled
100 Mb/ s - WoL 13 42 68 200 406
10 Mb/ s - WoL 11 1 23 66 116
WoL
disabled
Disabled in BI OS
2
2. Assumes t he syst em is in t he Moff st at e and SLP_LAN# is used t o gat e PHY power.
0 0 0 0 0
Disabled in driver 9 0 14 47 76
26
Pow er Management and Del i v er y 82578 GbE PHY
The following sect ions describe requirement s in specific power st at es.
6. 2 Pow er Del i v er y
The 82578 operat es from a 3.3 Vdc ext ernal power rail ( see Figure 7) .
6. 2. 1 2. 5 Vdc and 1. 8 Vdc Suppl y
The 2. 5 Vdc and 1. 8 Vdc are is supplied by int ernal LVRs as shown in t he schemat ics
t hat follow.
6.2.2 1.2 Vdc Suppl y
The 1. 2 Vdc rail can be supplied in one of t wo ways ( see Figure 4) :
An ext ernal power supply not dependent on support from t he 82578. For example,
t he plat form designer might choose t o rout e a plat form- available 1.2 Vdc supply t o
t he 82578. I nt el
5 Series Express Chipset

A discret e LVR solut ion, where t he base current of PNP power t ransist or is driven by
t he 82578, while t he power t ransist or is placed ext ernally.
6.3 Pow er Management
6.3.1 Gl obal Pow er St at es
The 82578 t ransit ions bet ween power st at es based on a st at us packet received over
t he int erconnect and based on t he Et hernet link st at e. The following power st at es are
defined:
Pow er Up Defined as t he period from t he t ime power is applied t o t he 82578 and
unt il t he 82578 powers up it s PHY. The 82578 needs t o consume less t han 40 mA
during t his period.
Act i v e 10/ 100/ 1000 Mb/ s Et hernet link is est ablished wit h a link part ner at
any of 10/ 100/ 1000 Mb/ s speed. The 82578 is eit her t ransmit t ing/ receiving dat a or
is capable of doing so wit hout delay ( for example, no clock gat ing t hat requires
lengt hy wake) .
I dl e 10/ 100/ 1000 Mb/ s - Et hernet link is est ablished wit h a link part ner at any
of 10/ 100/ 1000 Mb/ s speed. The 82578 is not act ively t ransmit t ing or receiving
dat a and might ent er a lower power st at e ( for example, t he cust om int erface can
be in elect rical idle) .
Cabl e Di sconnect The PHY ident ified t hat a cable is not connect ed. The 82578
signals t he MAC t hat t he link is down. The PHY might ent er energy det ect mode or
t he MAC might init iat e a move int o act ive power down mode ( sD3) .
Pow er Dow n ( LAN Di sabl e) Ent ry int o power down is init iat ed by t he MAC by
set t ing t he LAN_DI SABLE_N pin t o zero. The 82578 loses all funct ionalit y in t his
mode ot her t han t he abilit y t o power up again.

27
6. 3.1. 1 Pow er Up
Defined as t he period from t he t ime power is applied t o t he 82578 and unt il t he 82578
powers up it s PHY. t he 82578 should consume less t han ~ 40 mA during t his period.
Following t he 82578 PHY ent ering reset , t he power- up sequence is considered done
and t he requirement is removed.
6. 3.1. 2 Cabl e Di sconnect St at e
The 82578 ent ers a cable disconnect st at e if it det ect s a cable disconnect condit ion on
t he Et hernet link. Power is reduced during cable disconnect mode by several means:
The PHY ent ers energy det ect mode.
The PCI e link ent ers power down.
An exit from cable disconnect happens when t he 82578 det ect s energy on t he MDI link,
and st art s t he following exit sequence:
The 82578 signals t he MAC t hat link energy was det ect ed by clearing t he Cable
Disconnect bit in t he PCI e or SMBus int erface.
The PHY wait s unt il t he aut o- negot iat ion break link t imer expires ( T
c2an
t ime) and
t hen st art s t o advert ise dat a on t he line.
6. 3.1. 3 Pow er Dow n St at e
The 82578 ent ers a power- down st at e when t he LAN_DI SABLE_N pin is set t o zero.
Exit ing t his mode requires set t ing t he LAN_DI SABLE_N pin t o a logic one.
Figure 7 shows t he power- down sequence.
Fi gur e 7. Pow er - Dow n Sequence
Not e: I f t he LAN_DI SABLE_N pin cannot be used, a power- down inband can be used. When
used, t he power savings are lower since all logic cannot be t urned off in t his mode.
1
PCI e/ SMBus
PHY
Act ive
Act ive
Dev i ce
conf .
St ar t
AN
2
4
3
Pow er
Dow n
Power Down
5 6
LAN_DI SABLE_N
28
6.4 Pow er Savi ng Feat ur es
This sect ion provides informat ion about t he low power configurat ions for t he 82578.
6. 4.1 I nt el
Aut o Connect Bat t er y Sav er ( ACBS)

I nt el
Aut o Connect Bat t ery Saver for t he 82578 is a hardware- only feat ure t hat
aut omat ically reduces t he PHY t o a lower power st at e when t he power cable is
disconnect ed. When t he power cable is reconnect ed, it renegot iat es t he line speed
following I EEE specificat ions for aut o negot iat ion. By default , aut o negot iat ion st art s at
1 Gb/ s, t hen 100 Mb/ s full duplex/ half duplex, t hen 10 Mb/ s full duplex/ half duplex.
Not e: ACBS is only support ed during aut o negot iat ion. I f link is forced, t he 82578 does not
ent er ACBS mode.
82578 ACBS works in bot h S0 and Sx st at es. Since 82578 ACBS has no driver cont rol,
t he feat ure is always enabled, allowing power savings by default .
Not e: The cryst al clock drivers are int ermit t ent ly disabled when t he net work cable is
unplugged and t he 82578 is in ACBS mode.
6.4.2 Aut omat i c Li nk Dow nshi f t
Aut omat ic link downshift is a collect ion of power saving feat ures t hat enable a link
downshift from 1000 Mb/ s t o a lower speed t o save power under different condit ions
like t he AC cable plugged in, monit or idle, or ent ering Sx st at es.
Tabl e 8. Fi gur e 7 Not es
Not e Descr i pt i on
1
MAC sends an inband power- down message t hrough SMBus or PCI e or LAN_DI SABLE_N pin set t o
zero.
2
Once t he 82578 det ect s t he power- down message or LAN_DI SABLE_N t ransit ions t o a logic zero, t he
PHY ent ers a power- down st at e.
3 The PCI e link ( if enabled) ent ers elect rical idle st at e.
4 PCI e/ SMBus exit s a reset st at e and performs link init ializat ion.
5 MAC configures t he 82578 t hrough t he MDI O int erface.
6 PHY goes t hrough aut o- negot iat ion t o acquire link.
29
6. 4.2. 1 Li nk Speed Bat t er y Sav er
Link speed bat t ery saver is a power saving feat ure t hat negot iat es t o t he lowest speed
possible when t he 82578 operat es in bat t ery mode t o save power. When in AC mode,
where performance is more import ant t han power, it negot iat es t o t he highest speed
possible. The Windows NDI S drivers ( Windows XP and lat er) monit or t he AC- t o- bat t ery
t ransit ion on t he syst em t o make t he PHY negot iat e t o t he lowest connect ion speed
support ed by t he link part ner ( usually 10 Mb/ s) when t he power cable is unplugged
( swit ches from AC t o bat t ery power) . When t he AC cable is plugged in, t he speed
negot iat es back t o t he fast est LAN speed. This feat ure can be enabled/ disabled direct ly
from DMiX or t hrough t he advanced set t ings of t he Window' s driver.
When t ransferring packet s at 1000/ 100 Mb/ s speed, if t here is an AC- t o- bat t ery mode
t ransit ion, t he speed renegot iat es t o t he lower speed. Any packet t hat was in process is
re- t ransmit t ed by t he prot ocol layer. I f t he link part ner is hard- set t o only advert ise a
cert ain speed, t hen t he driver negot iat es t o t he advert ised speed. Not e t hat since t he
feat ure is driver based, it is available in S0 st at e only.
Link speed bat t ery saver handles duplex mismat ches/ errors on link seamlessly by re-
init iat ing aut o negot iat ion while changing speed. Link speed bat t ery saver also support s
spanning t ree prot ocol.
Not e: Packet s are re- t ransmit t ed for any prot ocol ot her t han TCP as well.
6. 4. 2. 2 Sy st em I dl e Pow er Sav er ( SI PS)
SI PS is a soft ware- based power saving feat ure t hat is enabled only wit h Microsoft *
Windows* Vist a* and Windows 7* . This feat ure is only support ed in t he S0 st at e and
can be enabled/ disabled using t he advanced t ab of t he Windows driver or t hrough
DMiX. The power savings from t his feat ure is dependent on t he link speed of t he
82578. Refer t o Sect ion 6. 1 for t he power dissipat ed in each link st at e.
SI PS is designed t o save power in t he 82578 by negot iat ing t o t he lowest possible link
speed when bot h t he net work is idle and t he monit or is t urned off due t o inact ivit y. The
SI PS feat ure is act ivat ed based on bot h of t he following condit ions:
The Windows* Vist a* / Windows 7* NDI S driver receives not ificat ion from t he
operat ing syst em when t he monit or is t urned off due t o non- act ivit y.
The LAN driver monit ors t he current net work act ivit y and det ermines t hat t he
net work is idle.
Then, wit h bot h t he monit or off and t he net work idle, t he LAN negot iat es t o t he lowest
possible link speed support ed by bot h t he PHY and t he link part ner ( t ypically 10 Mb/ s) .
I f t he link part ner is hard- set t o only advert ise a cert ain speed, t hen t he LAN negot iat es
t o t he advert ised speed. This link speed is maint ained unt il t he LAN driver receives
not ificat ion from t he operat ing syst em t hat t he monit or is t urned on, t hus exit ing SI PS
and renegot iat ing t o t he highest possible link speed support ed by bot h t he PHY and
t he link part ner. I f SI PS is exit ed when t ransferring packet s, any packet t hat was being
t ransferred is re- t ransmit t ed by t he prot ocol layer aft er renegot iat ion t o t he higher link
speed.
30
6.4.2.3 Low Pow er Li nk Up ( LPLU)
LPLU is a firmware/ hardware- based feat ure t hat enables t he designer t o make t he PHY
negot iat e t o t he lowest connect ion speed first and t hen t o t he next higher speed and so
on. This power saving set t ing can be used when power is more import ant t han
performance.
When speed negot iat ion st art s, t he PHY t ries t o negot iat e for a 10 Mb/ s link,
independent of speed advert isement . I f link est ablishment fails, t he PHY t ries t o
negot iat e wit h different speeds. I t enables all speeds up t o t he lowest speed support ed
by t he part ner. For example, if t he 82578 advert ises 10 Mb/ s only and t he link part ner
support s 1000/ 100 Mb/ s only, a 100 Mb/ s link is est ablished.
LPLU is cont rolled t hrough t he LPLU bit in t he PHY Power Management regist er. The
MAC set s and clears t he bit according t o hardware/ soft ware set t ings. The 82578 aut o
negot iat es wit h t he updat ed LPLU set t ing on t he following aut o- negot iat ion operat ion.
The 82578 does not aut omat ically aut o- negot iat e aft er a change in t he LPLU value.
LPLU is not dependent on whet her t he syst em is in Vac or Vdc mode. I n S0 st at e, link
speed bat t ery saver overrides t he LPLU funct ionalit y.
LPLU is enabled for non- D0a st at es by GbE NVM image word 0x17 ( bit 10)
0b = LPLU is disabled.
1b = LPLU is enabled in all non- D0a st at es.
LPLU power consumpt ion depends on what speed it negot iat es at . Sect ion 6. 1 includes
all of t he power numbers for t he 82578 in t he various speeds.
31
6. 4.2. 4 LAN Di sabl e Recommendat i ons
LAN_DI SABLE_N needs t o be connect ed t o t he GPI O12/ LAN_PHY_PWR_CTRL out put of
t he I nt el
5 Series Express Chipset . GPI O12 also needs t o be configured using I nt el
5
Series Express Chipset soft st raps as LAN_PHY_PWR_CTRL ( bit [ 20] of PCHSTRP0
regist er - LAN_PHY_PWR_CTRL/ GPI O12. Refer t o t he I nt el

Family Ext ernal Design Specificat ion ( I nt el

5 Series Express Chipset EDS) .
32
82578 GbE PHYDev i ce Funct i onal i t y
33
7. 0 Dev i ce Funct i onal i t y
7.1 Tx Fl ow
When packet s are ready for t ransmission in t he MAC it t ransfers t hem t o t he 82578
t hrough t he PCI e or t he SMBus ( depending on syst em st at e) . The 82578 st art s
t ransmit t ing t he arrived packet over t he wire aft er it gat hers eight byt es of dat a if t he
PCI e int erface is act ive or aft er all packet dat a is received if it was t ransferred over t he
SMBus; however, t his behavior has no dependency on link speed. The 82578 design is
based on t he assumpt ion t hat t he MAC has t he full packet ready for t ransmission.
7.2 Rx Fl ow
The 82578 maint ains a FI FO on t he receive side in order not t o lose packet s when PCI e
is act ive. I n t his case, t he 82578 init iat es recovery of t he PCI e when a recept ion has
st art ed. I f t he link is at 1 Gb/ s, t he t ransmission of t he packet over t he PCI e bus st art s
immediat ely aft er recovery. if t he link speed is lower, t he 82578 st art s t he t ransmission
aft er t he ent ire packet is received.
7.3 Fl ow Cont r ol
Flow cont rol as defined in 802. 3x, as well as t he specific operat ion of asymmet rical flow
cont rol defined by 802. 3z, is support ed in t he MAC. Some of t he flow cont rol
funct ionalit y has moved t o t he 82578. The following regist ers are duplicat ed t o t he
82578 for t he implement at ion of flow cont rol:
Flow Cont rol Address is: 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01; where 0x01 is t he
first byt e on t he wire, 0x80 is t he second, et c.
Flow Cont rol Type ( FCT) : a 16- bit field t o indicat e t he flow cont rol t ype.
Flow Cont rol Transmit Timer Value ( FCTTV) : a 16- bit t imer value t o include in a
t ransmit t ed PAUSE frame.
Flow Cont rol Refresh Threshold Value ( FCRTV) : a 16- bit PAUSE refresh t hreshold
value.
Flow cont rol is implement ed as a means of reducing t he possibilit y of receive buffer
overflows, which result in t he dropping of received packet s, and allows for local
cont rolling of net work congest ion levels. This can be accomplished by sending an
indicat ion t o a t ransmit t ing st at ion of a nearly full receive buffer condit ion at a receiving
st at ion. The implement at ion of asymmet ric flow cont rol allows for one link part ner t o
send flow cont rol packet s while being allowed t o ignore t heir recept ion. For example,
not required t o respond t o PAUSE frames.
34
Dev i ce Funct i onal i t y 82578 GbE PHY
7. 3. 1 MAC Cont r ol Fr ames and Recept i on of Fl ow Cont r ol Pack et s
Three comparisons are used t o det ermine t he validit y of a flow cont rol frame:
1. A mat ch on t he six- byt e mult icast address for MAC cont rol frames or t o t he st at ion
address of t he device ( Receive Address Regist er 0) .
2. A mat ch on t he t ype field
3. A comparison of t he MAC Cont rol Opcode field
The 802. 3x st andard defines t he MAC cont rol frame mult icast address as 01- 80- C2- 00-
00- 01. The flow cont rol packet s Type field is checked t o det ermine if it is a valid flow
cont rol packet : XON or XOFF. 802. 3x reserves t his as 0x8808. The final check for a
valid PAUSE frame is t he MAC Cont rol Opcode field. At t his t ime only t he PAUSE cont rol
frame opcode is defined and has a value of 0x0001. Frame- based flow cont rol
different iat es XOFF from XON based on t he value of t he PAUSE Timer field. Non- zero
values const it ut e XOFF frames while a value of zero const it ut es an XON frame. Values
in t he Timer field are in unit s of slot t ime. A slot t ime is hardwired t o 64 byt e t imes.
Not e: An XON frame signals cancelling t he pause from being init iat ed by an XOFF frame
( pause for zero slot t imes) .
Fi gur e 8. 802.3x MAC Cont r ol Fr ame For mat
Where S is t he st art - of- packet delimit er and T is t he first part of t he end- of- packet
delimit er for 802. 3z encapsulat ion. The receiver is enabled t o receive flow cont rol
frames if flow cont rol is enabled via t he RFCE bit in t he Device Cont rol ( CTRL) regist er.
Not e: Flow cont rol capabilit y must be negot iat ed bet ween link part ners via t he aut o-
negot iat ion process. The aut o- negot iat ion process might modify t he value of t hese bit s
based on t he resolved capabilit y bet ween t he local device and t he link part ner.
35
Once t he 82578 has validat ed t he recept ion of an XOFF, or PAUSE frame, it does t he
following:
I nit ializes t he pause t imer based on t he packet s Pause Timer field
Disables packet t ransmission or schedules t he disabling of t ransmission aft er t he
current packet complet es.
Sends an inband st at us command wit h t he TX OFF bit set .
Forward t he XOFF or PAUSE frame t o t he MAC.
Resuming t ransmission might occur under t he following condit ions:
Expirat ion of t he PAUSE t imer.
Recept ion of an XON frame ( a frame wit h it s PAUSE t imer set t o zero) .
1
Once t he 82578 has validat ed t he recept ion of an XON frame, it does t he following:
Enables packet t ransmission.
Sends an inband st at us command wit h t he Tx OFF bit cleared.
Forwards t he XON frame t o t he MAC.
7.3.2 Tr ansmi t t i ng PAUSE Fr ames
Transmit t ing PAUSE frames is done as a result of an I n- Band Cont rol command from
t he MAC. The MAC init iat es an inband message if it is enabled by soft ware by writ ing a
1b t o t he TFCE bit in t he Device Cont rol regist er.
Not e: Similar t o receiving flow cont rol packet s previously ment ioned, XOFF packet s can be
t ransmit t ed only if t his configurat ion has been negot iat ed bet ween t he link part ners via
t he aut o- negot iat ion process. I n ot her words, t he set t ing of t his bit indicat es t he
desired configurat ion.
When t he inband message from t he MAC is received, t he 82578 sends a PAUSE frame
wit h it s Pause Timer field equal t o FCTTV. Once t he receive buffer fullness reaches t he
low wat er mark, t he MAC sends an inband message indicat ing t o send an XON
message ( a PAUSE frame wit h a t imer value of zero) .
Not e: Transmit t ing flow cont rol frames should only be enabled in full- duplex mode per t he
I EEE 802. 3 st andard. Soft ware should make sure t hat t he t ransmission of flow cont rol
packet s is disabled when t he 82578 is operat ing in half- duplex mode.
7.4 Wak e Up
The 82578 support s host wake up.
This mechanism uses inband messages t o wake t he I nt el

from a sleep st at e. The host can enable host wake up from t he 82578 by set t ing t he
Host _WU_Act ive bit . When t his bit is set , aft er t he host t ransit ions t o a low power
st at e, t he SMBus int erface is st ill act ive and t he wake up indicat ion from t he 82578 t o
t he I nt el
5 Series Express Chipset would come in as an inband message over t he

SMBus.
1. The XON frame is also forwarded t o t he MAC.
36
Set t ing t he 82578s wake up:
1. Clear t he Host _WU_Act ive bit ( bit 4) in t he Port General Configurat ion regist er
( page 769, regist er 17) t o enable wake up mode.
2. Set bit 2 ( MACPD_enable) of t he Port Cont rol regist er ( page 769, regist er 17) t o
enable t he 82578 wake up capabilit y and soft ware accesses t o page 800.
3. Set t he Slave Access Enable bit ( bit 2) in t he Receive Cont rol regist er ( page 800,
regist er 0) t o enable access t o t he Flex Filt er regist er, if set t ing t hose bit s is needed
in t he next st age. The regist ers affect ed are:
a. Flexible Filt er Value Table LSB FFVT_L ( filt ers 01)
b. Flexible Filt er Value Table MSBs FFVT_H ( filt ers 23)
c. Flexible Filt er Value Table - FFVT_45 ( filt ers 45)
d. Flexible TCO Filt er Value/ Mask Table LSBs FTFT_L
e. Flexible TCO Filt er Value/ Mask Table MSBs FTFT_H
4. Configure t he 82578s wake up regist ers per ACPI / APM wake up needs.
5. Clear t he Slave Access Enable bit ( bit 2) in t he Receive Cont rol regist er ( page 800,
regist er 0) t o enable t he flex filt ers.
6. Set t he Host _WU_Act ive bit ( bit 4) in t he Port General Configurat ion regist er ( page
769, regist er 17) t o act ivat e t he 82578s wake up funct ionalit y.
Not e: Once wake up is enabled, t he 82578 st ops responding t o SMBus commands.
Host wake up:
1. When a WoL packet / event is det ect ed, t he 82578 sends an inband message t o t he
I nt el 5 Series Express Chipset indicat ing a host wake up.
2. The I nt el
5 Series Express Chipset wakes t he host .

3. The host should issue an PHY reset to t he 82578 before clearing the Host _WU_Act ive bit .
4. Host reads t he Wake Up St at us ( WUS) regist er; wake up st at us from t he 82578) .
The 82578 keeps and forwards t he wake up packet . When a wake up packet is
ident ified, t he wake up inband message is sent and t he host should clear t he
Host _WU_Act ive bit ( bit 4) in t he Port General Configurat ion regist er ( page 769,
regist er 17) . As a result , t he 82578 resumes t ransmit t ing t he packet . Each t ime t his bit
is set and if a wake up inband message has already sent , any new packet s received
does not overwrit e t he packet in t he FI FO. The 82578 re- t ransmit s t he wake up inband
message aft er 50 ms if no change in t he Host _WU_Act ive bit occurred.
7. 4.1 Host Wak e Up
The 82578 support s t wo t ypes of wake up mechanisms:
Advanced Power Management ( APM) wake up
ACPI Power Management wake up
37
7. 4.1. 1 Adv anced Pow er Management Wak e Up
Advanced Power Management Wakeup or APM Wakeup was previously known as Wake
on LAN ( WoL) . The basic premise is t o receive a broadcast or unicast packet wit h an
explicit dat a pat t ern, and t hen t o assert a signal t o wake up t he syst em or issue an in-
band PM_PME message ( if configured t o) .
At power up, if t he 82578s wake up funct ionalit y is enabled, t he APM Enable bit s from
t he NVM are writ t en t o t he 82578 by t he I nt el
5 Series Express Chipset t o t he APM

Enable ( APME) bit s of t he Wakeup Cont rol ( WUC) regist er. These bit s cont rol t he
enabling of APM wake up.
When APM wake up is enabled, t he 82578 checks all incoming packet s for Magic
Packet s. See Sect ion 7. 4.1.3. 1. 4 for a definit ion of Magic Packet s.
To enable APM wake up, programmers should writ e a 1b t o bit 10 in regist er 26 on page
0 PHY address 01, and t hen t he st at ion address t o regist ers 27, 28, 29 at page 0 PHY
address 01. The order is mandat ory since regist ers RAL0[ 31: 0] and RAH0[ 15: 0] are
updat ed wit h a corresponding value from regist ers 27, 28, 29, if t he APM WoL Enable
bit is set in regist er 26. The Address Valid bit ( bit 31 in RAH0) is aut omat ically set wit h
a writ e t o regist er 29, if t he APM WoL Enable bit is set in regist er 26. The APM Enable
bit ( bit 0 in t he WUC) is aut omat ically set wit h a writ e t o regist er 29, if t he APM WoL
Enable bit is set in regist er 26.
Once t he 82578 receives a mat ching magic packet , it :
Set s t he Magic Packet Received bit in t he WUS regist er.
I nit iat es t he I nt el
5 Series Express Chipset wake up event t hrough an inband

message.
APM wake up is support ed in all power st at es and only disabled if a subsequent NVM
read result s in t he APM Wake Up bit being cleared or soft ware explicit ly writ es a 0b t o
t he APM Wake Up ( APM) bit of t he WUC regist er.
7.4.1. 1.1 Li nk St at us Change
When t he LSCWO bit ( bit 5 in t he WUC regist er) is set , wake up is generat ed if all of t he
following condit ions are met :
APM wake up is enabled ( APME bit is set in t he WUC regist er)
The LSCWE bit ( bit 4) is set in t he WUC regist er
Link st at us change is det ect ed
When t he 82578 det ect s a link st at us change it :
Set s t he Link St at us Changed ( LNKC) bit ( bit 0) in t he WUS regist er.
I nit iat es t he I nt el
5 Series Express Chipset wake up event .

When t he LSCWO bit is set , wake up is never generat ed on link st at us change if eit her
APM wake up is disabled or t he LSCWE bit is cleared. I n t his case, t he LNKC bit ( bit 0)
in t he Wake up Filt er Cont rol ( WUFC) regist er is read as zero, independent of t he value
writ t en t o it .
38
7.4.1.2 ACPI Pow er Management Wak e Up
The 82578 support s ACPI Power Management based wake ups and can generat e
syst em wake up event s from t hree sources:
Recept ion of a Magic Packet
Recept ion of a ACPI wake up packet
Det ect ion of a link change of st at e
Act ivat ing ACPI Power Management wake up requires t he following st eps:
Programming of t he WUFC regist er t o indicat e t he packet s it needs t o wake up and
supplies t he necessary dat a t o t he I Pv4 Address Table ( I P4AT) and t he Flexible
Filt er Mask Table ( FFMT) , Flexible Filt er Lengt h Table ( FFLT) , and t he Flexible Filt er
Value Table ( FFVT) . I t can also set t he Link St at us Change Wake up Enable ( LNKC)
bit ( bit 0) in t he WUFC regist er t o cause wake up when t he link changes st at e.
Set t ing bit 2 ( MACPD_enable) of t he Port Cont rol regist er ( page 769, regist er 17) t o
put t he 82578 in wake up mode.
Once wake up is enabled, t he 82578 monit ors incoming packet s by first filt ering t hem
according t o it s st andard address filt ering met hod and t hen by filt ering t hem wit h all
enabled wake up filt ers. I f a packet passes bot h t he st andard address filt ering and at
least one of t he enabled wake up filt ers, t he 82578:
I nit iat es a t he I nt el
5 Series Express Chipset wake up event .

Set s one or more of t he Received bit s in t he WUS regist er. Not e t hat more t han one
bit is set if a packet mat ches more t han one filt er.
I f enabled, a link st at e change wake up causes similar result s.
7.4.1.3 Wak e Up Pack et s
The 82578 support s various wake up packet s using t wo t ypes of filt ers:
Pre- defined filt ers
Flexible filt ers
Each of t hese filt ers are enabled if t he corresponding bit in t he WUFC regist er is set t o
1b. I f t he wake up packet passes one of t he manageabilit y filt ers enabled in t he
Management Cont rol ( MANC) regist er, t hen syst em wake up also depends on t he
NoTCO bit ( 11) in t he WUFC regist er being inact ive.
7.4.1.3.1 Pr e- Def i ned Fi l t er s
The following packet s are support ed by t he 82578s predefined filt ers:
Direct ed Packet ( including exact , mult icast indexed, and broadcast )
Magic packet
I Pv4 request packet
Direct ed I Pv4 packet
Direct ed I Pv6 packet
Flexible UDP/ TCP and I P filt ers packet s
Each of t hese filt ers are enabled if t he corresponding bit in t he WUFC regist er is set t o
1b.
39
The explanat ion of each filt er includes a t able showing which byt es at which offset s are
compared t o det ermine if t he packet passes t he filt er. Not e t hat bot h VLAN frames and
LLC/ Snap can increase t he given offset s if t hey are present .
7.4.1. 3.1.1 Di r ect ed Ex act Pack et
The 82578 generat es a wake up event aft er receiving any packet whose dest inat ion
address mat ches one of t he seven valid programmed receive addresses if t he Direct ed
Exact Wake Up Enable bit ( bit 2) is set in t he WUFC regist er.
7.4.1. 3.1.2 Di r ect ed Mul t i cast Pack et
For mult icast packet s, t he upper bit s of t he incoming packet s dest inat ion address
indexes a bit vect or and t he Mult icast Table Array indicat es whet her t o accept t he
packet . I f t he Direct ed Mult icast Wake Up Enable bit ( bit 3) is set in t he WUFC regist er
and t he indexed bit in t he vect or is one, t he 82578 generat es a wake up event . The
exact bit s used in t he comparison are programmed by soft ware in t he Mult icast Offset
field ( bit s 4: 3) of t he RCTL regist er.
7.4.1. 3.1.3 Br oadcast
I f t he Broadcast Wake Up Enable bit ( bit 4) in t he WUFC regist er is set , t he 82578
generat es a wake up event when it receives a broadcast packet .
Of f set # of By t es Fi el d Val ue Act i on Comment
0 6 Dest inat ion Address Compare
Mat ch any pre- programmed address as
defined in t he receive address
0 6 Dest inat ion Address Compare See previous paragraph.
0 6 Dest inat ion Address FF* 6 Compare
40
7.4.1.3.1.4 Magi c Pack et
Magic packet s are defined as follows:
Magi c Pack et Technol ogy Det ai l s - Once t he 82578 has been put int o Magic
Packet mode, it scans all incoming frames addressed t o t he node for a specific
dat a sequence, which indicat es t o t he MAC t hat t his is a Magic Packet frame. A
Magic Packet frame must also meet t he basic requirement s for t he LAN
t echnology chosen, such as Source address, Dest inat ion Address ( which might
be t he receiving st at ions I EEE address or a Mult icast address t hat includes t he
Broadcast address) and CRC. The specific dat a sequence consist s of 16
duplicat ions of t he I EEE address of t his node wit h no breaks or int errupt ions.
This sequence can be locat ed anywhere wit hin t he packet , but must be
preceded by a synchronizat ion st ream. The synchronizat ion st ream enables t he
scanning st at e machine t o be much simpler. The synchronizat ion st ream is
defined as 6 byt es of 0xFF. The device also accept s a Broadcast frame, as long
as t he 16 duplicat ions of t he I EEE address mat ch t he address of t he syst em
t hat needs t o wake up.
The 82578 expect s t he dest inat ion address t o eit her:
1. Be t he broadcast address ( FF.FF. FF.FF. FF. FF)
2. Mat ch t he value in Receive Address ( RAH0/ RAL0) regist er 0. This is init ially loaded
from t he NVM but can be changed by t he soft ware device driver.
3. Mat ch any ot her address filt ering enabled by t he soft ware device driver.
I f t he packet dest inat ion address met one of t he t hree crit eria previously list ed, t he
82578 searches for 16 repet it ions of t he same dest inat ion address in t he packet ' s dat a
field. Those 16 repet it ions must be preceded by ( in t he dat a field) at least 6 byt es of
0xFF, which act as a synchronizat ion st ream. I f t he dest inat ion address is NOT t he
broadcast address ( FF. FF. FF.FF. FF.FF) , t he 82578 assumes t hat t he first non- 0xFF byt e
following at least 6 0xFF byt es is t he first byt e of t he possible mat ching dest inat ion
address. I f t he 96 byt es following t he last 0xFF are 16 repet it ions of t he dest inat ion
address, t he 82578 accept s t he packet as a valid wake up Magic Packet . Not e t hat t his
definit ion precludes t he first byt e of t he dest inat ion address from being 0xFF.
A Magic Packet s dest inat ion address must mat ch t he address filt ering enabled in t he
configurat ion regist ers wit h t he except ion t hat broadcast packet s are considered t o
mat ch even if t he Broadcast Accept bit ( bit 5) of t he RCTL regist er is 0b. I f APM wake
up is enabled in t he NVM, t he 82578 st art s up wit h t he RAH0/ RAL0 regist er 0 loaded
from t he NVM. This enables t he 82578 t o accept packet s wit h t he mat ching I EEE
address before t he soft ware device driver comes up.
MAC Header processed by main
address filt er
6 6 Source Address Skip
12 4 Possible VLAN Tag Skip
12 8
Possible Len/ LLC/ SNAP
Header
Skip
12 4 Type Skip
Any 6 Synchronizing St ream FF* 6+ Compare
any+ 6 96 16 copies of Node Address A* 16 Compare Compared t o RAH0/ RAL0 regist er
41
7.4.1. 3.1.5 I Pv4 Request Pack et
Three I Pv4 addresses are support ed, which are programmed in t he I Pv4 Address Table
( I P4AT) . A successfully mat ched packet must cont ain a broadcast MAC address, a
pr ot ocol t ype of 0x0806, and one of t he four programmed I Pv4 addresses.
address filt er
12 8
Header
Skip
12 2 Type 0x0806 Compare
14 2 Hardware Type 0x0001 Compare
16 2 Prot ocol Type 0x0800 Compare
18 1 Hardware Size 0x06 Compare
19 1 Prot ocol Address Lengt h 0x04 Compare
20 2 Operat ion 0x0001 Compare
22 6 Sender Hardware Address - I gnore
28 4 Sender I P Address - I gnore
32 6 Target Hardware Address - I gnore
38 4 Target I P Address I P4AT Compare
Might mat ch any of four values in
I P4AT
42
7. 4.1. 3.1. 6 Di r ect ed I Pv 4 Pack et
The 82578 support s receiving Direct ed I Pv4 packet s for wake up if t he I PV4 bit ( bit 6)
is set in t he WUFC regist er. Three I Pv4 addresses are support ed, which are
programmed in t he I Pv4 Address Table ( I P4AT) . A successfully mat ched packet must
cont ain t he st at ions MAC address, a Prot ocol Type of 0x0800, and one of t he four
programmed I pv4 addresses. The 82578 also handles Direct ed I Pv4 packet s t hat have
VLAN t agging on bot h Et hernet I I and Et hernet SNAP t ypes.
7. 4.1. 3.1. 7 Di r ect ed I Pv 6 Pack et
The 82578 support s receiving Direct ed I Pv6 packet s for wake up if t he I PV6 bit ( bit 7)
is set in t he WUFC regist er. One I Pv6 address is support ed, which is programmed in t he
I Pv6 Address Table ( I P6AT) . A successfully mat ched packet must cont ain t he st at ions
MAC address, a prot ocol t ype of 0x0800, and t he programmed I Pv6 address. The
82578 also handles Direct ed I Pv6 packet s t hat have VLAN t agging on bot h Et hernet I I
and Et hernet SNAP t ypes.
address filt er
12 8
Header
Skip
12 2 Type 0x0800 Compare I P
14 1 Version/ HDR lengt h 0x4X Compare Check I Pv4
15 1 Type of Service - I gnore
16 2 Packet Lengt h - I gnore
18 2 I dent ificat ion - I gnore
20 2 Fragment I nfo - I gnore
22 1 Time t o live - I gnore
23 1 Prot ocol - I gnore
24 2 Header Checksum - I gnore
26 4 Source I P Address - I gnore
30 4 Dest inat ion I P Address I P4AT Compare
Might mat ch any of four values in
I P4AT
address filt er
12 8
Header
Skip
12 2 Type 0x0800 Compare I P
14 1 Version/ Priorit y 0x6X Compare Check I Pv6
15 3 Flow Label - I gnore
18 2 Payload Lengt h - I gnore
20 1 Next Header - I gnore
43
7.4.1. 3.2 Fl ex i bl e Fi l t er
The 82578 support s a t ot al of six flexible filt ers. Each filt er can be configured t o
recognize any arbit rary pat t ern wit hin t he first 128 byt es of t he packet . To configure
t he flexible filt er, soft ware programs t he mask values int o t he Flexible Filt er Mask Table
( FFMT) and t he required values int o t he Flexible Filt er Value Table ( FFVT) , and t he
minimum packet lengt h int o t he Flexible Filt er Lengt h Table ( FFLT) . These cont ain
separat e values for each filt er. Soft ware must also enable t he filt er in t he WUFC
regist er, and enable t he overall wake up funct ionalit y must be enabled by set t ing
PME_En in t he Power Management Cont rol St at us Regist er ( PMCSR) or t he WUC
regist er.
Once enabled, t he flexible filt ers scan incoming packet s for a mat ch. I f t he filt er
encount ers any byt e in t he packet where t he mask bit is one and t he byt e doesnt
mat ch t he byt e programmed in t he Flexible Filt er Value Table ( FFVT) t hen t he filt er fails
t hat packet . I f t he filt er reaches t he required lengt h wit hout failing t he packet , it passes
t he packet and generat es a wake up event . I t ignores any mask bit s set t o one beyond
t he required lengt h.
Not e: The following packet s are list ed for reference purposes only. The flexible filt er could be
used t o filt er t hese packet s.
7.4.1. 3.2.1 I PX Di agnost i c Responder Request Pack et
An I PX Diagnost ic Responder Request packet must cont ain a valid MAC address, a
pr ot ocol t ype of 0x8137, and an I PX diagnost ic socket of 0x0456. I t might include LLC/
SNAP Headers and VLAN Tags. Since filt ering t his packet relies on t he flexible filt ers,
which use offset s specified by t he operat ing syst em direct ly, t he operat ing syst em must
account for t he ext ra offset LLC/ SNAP Headers and VLAN t ags.
7.4.1. 3.2.2 Di r ect ed I PX Pack et
A valid Direct ed I PX packet cont ain t he st at ions MAC address, a prot ocol t ype of
0x8137, and an I PX node address t hat equals t o t he st at ions MAC address. I t might
include LLC/ SNAP Headers and VLAN Tags. Since filt ering t his packet relies on t he
flexible filt ers, which use offset s specified by t he operat ing syst em direct ly, t he
operat ing syst em must account for t he ext ra offset LLC/ SNAP Headers and VLAN t ags.
21 1 Hop Limit - I gnore
22 16 Source I P Address - I gnore
38 16 Dest inat ion I P Address I P6AT Compare Mat ch value in I P6AT
Of f set
# of
By t es
Fi el d Val ue Act i on Comment
12 8 Possible Len/ LLC/ SNAP Header Skip
12 2 Type 0x8137 Compare I PX
14 16 Some I PX I nformat ion - I gnore
30 2 I PX Diagnost ic Socket 0x0456 Compare
44
7.4.1.3.2.3 I Pv 6 Nei ghbor Sol i ci t at i on Message Fi l t er
I n I Pv6, a Neighbor Solicit at ion Message packet ( t ype 135) is used for address
resolut ion. A flexible filt er can be used t o check for a Neighborhood Solicit at ion
Message packet ( t ype 135) .
Not e: The fields checked for det ect ion of a Neighbor Solicit at ion Message packet ( t ype 135)
are t ype, code and addresses.
7.4.2 Accessi ng The 82578 s Wak e Up Regi st er Usi ng MDI C
When soft ware needs t o configure t he wake up st at e ( eit her read or writ e t o t hese
regist ers) t he MDI O page should be set t o 800 ( for host accesses) unt il t he page is not
changed t o a different value wake up regist er access is enabled. Refer t o Sect ion 8. 10. 1
for more det ails.
Aft er t he page is set t o t he wake up page, t he Address field is no longer t ranslat ed as
reg_addr ( regist er address) but as an inst ruct ion. I f t he given address is in [ 0. . 15]
range meaning PHY regist ers, t he funct ionalit y remains unchanged.
There are t wo valid inst ruct ions:
Of f set
# of
By t es
Fi el d Val ue Act i on Comment
MAC Header
processed by main
address filt er
12 8 Possible Len/ LLC/ SNAP Header Skip
12 2 Type 0x8137 Compare I PX
14 10 Some I PX I nformat ion - I gnore
24 6 I PX Node Address
Receive
Address 0
Compare
Must mat ch Receive
Address 0
I nst r uct i on Addr ess Descr i pt i on
Address set 0x11 Wake up space address is set for eit her reading or writ ing.
Dat a cycle 0x12 Wake up space accesses read or writ e cycle.
45
7.5 PHY Loopback
PHY loopback is support ed in t he 82578. Soft ware or firmware should set t he 82578 t o
t he loopback mode ( via t he MDI C regist er) writ ing t o t he PHY Loopback Cont rol regist er
( address 19) . The MAC must be in forced link and in full duplex mode for PHY loopback
t o operat e. The following bit s must be configured t o enable PHY loopback:
CTRL.FRCDPLX = 1b: / / force duplex mode by t he MAC
CTRL. FD = 1b: / / Set full- duplex mode
46
82578 GbE PHYPr ogr ammer s Vi si bl e St at e
47
8. 0 Pr ogr ammer s Vi si bl e St at e
8.1 Ter mi nol ogy
This document names regist ers as follows.
By regist er number
Regist ers 0- 15 are independent of t he page and can be designat ed by t heir
regist er number.
When a regist er number is used for regist ers 16- 21, or 23- 28, it refers t o t he
regist er in page 0.
Regist er 31 in PHY address 01, is t he page regist er it self and doesnt belong t o
any page. I t is always writ t en as regist er 31.
By page and regist er number
This can be writ t en out as page x, regist er y, but is oft en abbreviat ed x. y
By name
Most funct ional regist ers also have a name.
Shor t hand Descr i pt i on
R/ W
Read/ Writ e. A regist er wit h t his at t ribut e can be read and writ t en. I f writ t en since reset , t he
value read reflect s t he value writ t en.
R/ W S
Read/ Writ e St at us. A regist er wit h t his at t ribut e can be read and writ t en. This bit represent s
st at us of some sort , so t he value read might not reflect t he value writ t en.
RO Read Only. I f a regist er is read only, writ es t o t his regist er have no effect .
WO Writ e Only. Reading t his regist er might not ret urn a meaningful value.
R/ WC
Read/ Writ e Clear. A regist er bit wit h t his at t ribut e can be read and writ t en. However, a writ e of
1b clears ( set s t o 0b) t he corresponding bit and a writ e of 0b has no effect .
R/ W SC
Read/ Writ e Self Clearing. When writ t en t o 1b t he bit causes an act ion t o be init iat ed. Once t he
act ion is complet e t he bit ret urn t o 0b.
RO/ LH
Read Only, Lat ch High. The bit records an event or t he occurrence of a condit ion t o be recorded.
When t he event occurs t he bit is set t o 1b. Aft er t he bit is read, it ret urns t o 0b unless t he event
is st ill occurring.
RO/ LL
Read Only, Lat ch Low. The bit records an event . When t he event occurs t he bit is set t o 0b. Aft er
t he bit is read, it reflect s t he current st at us.
RO/ SC
Read Only, Self Clear. Writ es t o t his regist er have no effect . Reading t he regist er clears ( set t o
0b) t he corresponding bit s.
RW0
I gnore Read, Writ e Zero. The bit is a reserved bit . Any values read should be ignored. When
writ ing t o t his bit always writ e as 0b.
RWP
I gnore Read, Writ e Preserving. This bit is a reserved bit . Any values read should be ignored.
However, t hey must be saved. When writ ing t he regist er t he value read out must be writ t en
back. ( There are current ly no bit s t hat have t his definit ion. )
Updat e
Value writ t en t o t he regist er field does not t ake effect unt il a soft ware reset is execut ed. The
value can st ill be read aft er it is writ t en.
Ret ain Value writ t en t o a regist er field does t ake effect wit hout a soft ware reset .

48
Pr ogr ammer s Vi si bl e St at e82578 GbE PHY
Regist er bit s are designat ed by a dot followed by a number aft er t he regist er address.
Thus, bit 4. 16. 2 is page 4, regist er 16 and bit 2. Mult i- bit fields follow t he MSB, colon,
LSB convent ion and so bit s 4. 16. 5: 4 is page 4, regist er 16, bit s 5: 4. All fields in a
regist er have a name.
Regist er bit s wit h default values marked wit h an ast erisk * are loaded by t he MAC
during t he 82578 power up and following reset . Ot her fields in t he same 16- bit regist er
must be loaded wit h t heir default values.
8.2 MDI O Access
Aft er PHY reset , a delay of 10 ms is required before any regist er access using MDI O.
8.3 Addr essi ng
Addressing is based on t he I EEE 802. 3 MI I Management I nt erface specificat ion defined
in clause 22 of 802. 3, part icularly sect ion 22. 2. 4.
The 82578 regist ers are spread over t wo PHY addresses 01, 02, where general
regist ers are locat ed under PHY address 01 and t he PHY specific regist ers are at PHY
address 02. The I EEE specificat ion allows five bit s for t he regist er access. Regist ers 0 t o
15 are defined by t he specificat ion, while regist ers 16 t o 31 are left available t o t he
vendor. The PHY implement s many regist ers for diagnost ic purposes. I n addit ion, t he
82578 cont ains regist ers cont rolling t he cust om int erface as well as ot her t he 82578
funct ions. The t ot al number of regist ers implement ed far exceeds t he 16 regist ers
available t o t he vendor. When t his occurs, a common t echnique is t o use paging. The
82578 regist ers in PHY address 01, are divided int o pages. Each page has 32 regist ers.
Regist ers 0- 15 are ident ical in all t he pages and are t he I EEE defined regist ers. Regist er
31 is t he page regist er in all pages of PHY address 01. All ot her regist ers are page
specific.
I n order t o read or writ e a regist er, soft ware should define t he appropriat e PHY
address. For PHY address 01, in order t o access regist ers ot her t han 0- 15, soft ware
should first set t he page regist er t o map t o t he appropriat e page. Soft ware can t hen
read or writ e any regist er in t hat page. Set t ing t he page is done by writ ing page_num x
32 t o Regist er 31. This is because only t he 11 MSBs of regist er 31 are used for defining
t he page. During writ e t o t he page regist er, t he five LSBs are ignored.
I n pages 800 and 801, t he regist er address space is more t han 32. See sect ion 8. 9 for
a descript ion of regist ers addressing in t hese pages.
Accessing more t han 32 regist ers in PHY address 02, is done wit hout using pages.
I nst ead, t wo regist ers from regist er address 16 t o 31 are used as Address Offset port
and Dat a port for ext ended set of regist ers. See sect ion 8. 5 for det ails about t hese
regist ers.
49
8.4 Addr ess Map
Tabl e 9. Addr ess Map
PHY
Addr ess
Page Regi st er Name Tabl e #
02 Any 0 Cont rol Regist er Table 10
02 Any 1 St at us Regist er Table 11
02 Any 2 PHY I dent ifier [ 18: 3] Table 12
02 Any 3 PHY I dent ifier [ 19: 24] Table 13
02 Any 4 Aut o- Negot iat ion Advert isement Table 14
02 Any 5 Link Part ner Abilit y ( Base Page) Base Table 15
02 Any 6 Aut o- Negot iat ion Expansion Table 16
02 Any 7 Next Page Transmit Table 17
02 Any 8 Link Part ner Next Page Table 18
02 Any 9 1000BASE-T Cont rol Table 19
02 Any 10 1000BASE-T St at us Table 20
02 Any 15 Ext ended St at us Table 21
02 0 16 Funct ion Cont rol Table 22
02 0 17 PHY- Specific St at us Table 23
02 0 18 I nt errupt Enable Table 24
02 0 19 I nt errupt St at us Table 25
02 0 20 Ext ended PHY- Specific Cont rol Table 26
02 0 21 Receive Error Count er Table 27
02 0 22 Cable Defect Test er Cont rol Table 28
02 0 24 LED Cont rol Table 29
02 0 25 Manual LED Override Table 30
02 0 28 Cable Defect Test er St at us Table 31
02 0 29 Debug Port Address Offset Table 32
02 0 30 Debug Port Dat a Table 33
Page 769 Por t Cont r ol Regi st er s
01 769 17 Port General Configurat ion Table 41
01 769 21 Power Management Cont rol Table 42
01 769 25 Rat e Adapt at ion Cont rol Table 44
01 769 27 Flow Cont rol Transmit Timer Value Table 45
Page 778 St at i st i cs Regi st er s
01 778 16 - 17 Single Collision Count Table 46
01 778 18 - 19 Excessive Collisions Count Table 47
01 778 20 - 21 Mult iple Collisions Count Table 48
01 778 23 - 24 Lat e Collision Count Table 49
01 778 25 - 26 Collision Count Table 50
01 778 27 - 28 Defer Count Table 51
01 778 29 - 30 Transmit wit h No CRS - TNCRS Table 52
PCI e Regi st er s

50
01 770 16 PCI e FI FOs Cont rol/ St at us Table 53
01 770 17 PCI e Power Management Cont rol Table 54
01 770 18 I n- Band Cont rol Table 55
01 770 20 PCI e Diagnost ics Table 56
01 770 21 Timeout s Table 57
01 770 23 PCI e K- St at e Minimum Durat ion Timeout Table 58
Gener al Regi st er s
01 776 19 82578 Capabilit y Regist er Table 59
01 0 25 OEM Bit s Table 60
01 0 26 SMBus Address Table 61
01 0 27- 28 Shadow Regist er for RAL0[ 31: 0] . Table 62
01 0 29 Shadow Regist er for RAH0[ 15: 0] . Table 63
01 0 30 LED Configurat ion Table 64
Page 800 - Wak e Up Regi st er s
01 800 0 Receive Cont rol Regist er Table 65
01 800 1 Wake Up Cont rol Regist er Table 66
01 800 2 Wake Up Filt er Cont rol Regist er Table 67
01 800 3 Wake Up St at us Regist er Table 68
01 800 16 Receive Address Low 0 Table 69
01 800 18 Receive Address High 0 Table 70
01 800 44 - 45 Shared Receive Address Low 0 Table 71
01 800 46 - 47 Shared Receive Address High 0 Table 72
01 800 58 - 59 Shared Receive Address High 3 Table 73
01 800 64 I P Address Valid I PAV Table 74
01 800 82 - 83 I Pv4 Address Table I P4AT 0 Table 75
01 800 88 - 89 I Pv6 Address Table I P6AT 0 Table 76
01 800 128 - 191 Mult icast Table Array MTA[ 31: 0] Table 77
01 800 256 + 2* n ( n = 0 - 127) Flexible Filt er Value Table LSB FFVT_01 Table 78
01 800 257 + 2* n ( n = 0 - 127) Flexible Filt er Value Table MSB FFVT_23 Table 79
01 800 512 + 2* n ( n = 0 - 127) Flexible Filt er Value Table FFVT_45 Table 80
01 800 768 + n ( n = 0 - 127) Flexible Filt er Mask Table FFMT Table 81
01 800 896 + n ( n = 0 - 3) Flexible Filt er Lengt h Table FFLT03 Table 82
01 800 904 + n ( n= 01) Flexible Filt er Lengt h Table FFLT45 Table 83
Tabl e 9. Addr ess Map
51
8.5 PHY Regi st er s ( Page 0)
Tabl e 10. Cont r ol Regi st er PHY Addr ess 02, Page Any, Regi st er 0
Bi t s Fi el d Mode HW Rst SW Rst Descr i pt i on
15 Reset R/ W, SC 0b SC
Writ ing a 1b t o t his bit causes immediat e PHY reset .
Once t he operat ion complet es, t his bit clears t o 0b
aut omat ically
1b = PHY reset .
0b = Normal operat ion.
14 Loopback R/ W 0b 0b
When loopback is act ive, t he t ransmit t er dat a on
TXD loops back t o RXD int ernally. The link breaks
when loopback is enabled.
1b = Enable loopback.
0b = Disable loopback.
13
Speed Select
( LSB)
R/ W 0b Ret ain
Bit 6, 13
11b = Reserved.
10b = 1000 Mb/ s.
01b = 100 Mb/ s.
00b = 10 Mb/ s.
12
Aut o-
Negot iat ion
Enable
R/ W 0b Ret ain
1b = Enable aut o- negot iat ion process.
0b = Disable aut o- negot iat ion process.
11 Power Down R/ W 0b 0b
1b = Power down.
10 Reserved RO 0b 0b Reserved
9
Rest art Aut o-
Negot iat ion
R/ W, SC 0b SC
Aut o- negot iat ion aut omat ically rest art s aft er a
hardware or soft ware reset regardless of whet her or
not t his bit is set .
1b = Rest art aut o- negot iat ion process.
8 Duplex Mode R/ W 0b Ret ain
1b = Full- duplex.
0b = Half- duplex.
7 Collision Test RO 0b 0b
Set t ing t his bit t o 1b causes t he COL pin t o assert
each t ime t he TX_EN pin is assert ed. This bit t akes
effect only while in 10 Mb/ s loopback mode.
6
Speed
Select ion
( MSB)
R/ W 0b Updat e See descript ion in bit 13.
5: 0 Reserved RO
Always
0x0
Always
0x0
Reserved, always set t o 0x0.
Tabl e 11. St at us Regi st er PHY Addr ess 02, Page Any , Regi st er 1
15 100BASE-T4 RO 0b 0b
100BASE-T4. This prot ocol is not available.
0b = PHY not able t o perform 100BASE-T4.
14
100BASE-X Full-
Duplex
RO 1b 1b 1b = PHY able t o perform full- duplex 100BASE-X.
13
100BASE-X Half-
Duplex
RO 1b 1b 1b = PHY able t o perform half- duplex 100BASE-X.
12
10 Mbps Full-
Duplex
RO 1b 1b 1b = PHY able t o perform full- duplex 10BASE-T.
11
10 Mbps Half-
Duplex
RO 1b 1b 1b = PHY able t o perform half- duplex 10BASE-T.

52
Tabl e 12. PHY I dent i f i er [ 18: 3] PHY Addr ess 02, Page Any , Regi st er 2
Tabl e 13. PHY I dent i f i er [ 19: 24] PHY Addr ess 02, Page Any , Regi st er 3
10
100BASE-T2
Full- Duplex
RO 0b 0b Not able t o perform 100 Base-T2.
9
100BASE-T2
Half- Duplex
RO 0b 0b Not able t o perform 100 Base-T2.
8 Ext ended St at us RO 1b 1b
Ext ended st at us informat ion in t he regist er Ext ended
St at us.
7 Reserved RO 0b 0b Must always be set t o 0b.
6
MF Preamble
Suppression
RO 1b 1b
1b = PHY accept s management frames wit h preamble
suppressed.
5
Aut o-
Negot iat ion
Complet e
RO 0b 0b
1b = Aut o- negot iat ion process complet e.
0b = Aut o- negot iat ion process not complet e.
4 Remot e Fault RO,LH 0b 0b
1b = Remot e fault condit ion det ect ed.
0b = Remot e fault condit ion not det ect ed.
3
Aut o- Negot iat ion
Abilit y
RO 1b 1b 1b = PHY able t o perform aut o- negot iat ion.
2 Link St at us RO,LL 0b 0b
I ndicat es whet her t he link was lost since t he last
read. For t he current link st at us, read
LI NK_REAL_TI ME ( bit [ 10] ) of t he regist er PHY-
Specific St at us. Lat ching low funct ion.
1b = Link is up.
0b = Link is down.
1 Jabber Det ect RO,LH 0b 0b
1b = Jabber condit ion det ect ed 0 = Jabber condit ion
not det ect ed.
0
Ext ended
Capabilit y
RO 1b 1b 1b = Ext ended regist er capabilit ies.
Bi t s Fi el d Ty pe Def aul t Descr i pt i on
15: 0
Unique
I dent ifier Bit s
18: 3
RO 0x004D Organizat ionally Unique I dent ifier ( OUI ) , bit s [ 18: 3] .
Bi t s Fi el d Ty pe Def aul t Descr i pt i on
15: 10
PHY I dent ifier
Bit s 24: 19
RO 110100b OUI , bit s [ 24: 19] .
9: 4 Model Number RO 000100b
The value is part of t he PHY ident ifier and represent s t he
Device Model Number.
3: 0
Revision
Number
RO 0x2
The value is part of t he PHY ident ifier and represent s t he
Device Revision Number.
Tabl e 11. St at us Regi st er PHY Addr ess 02, Page Any, Regi st er 1
53
Tabl e 14. Aut o- Negot i at i on Adver t i sement PHY Addr ess 02, Page Any , Regi st er 4
15 Next Page R/ W 0b Updat e
I f 1000BASE-T is advert ised t hen t he required next
pages are aut omat ically t ransmit t ed. This bit should be
set t o 0b if no addit ional next pages are needed.
1b = Advert ise.
0b = Not advert ised.
14 Ack RO
Always
0b
Always
0b
Must be 0b.
13 Remot e Fault R/ W 0b Updat e Writ e a 1b t o set remot e fault .
12 Reserved R/ W 0b Updat e Reserved
11
Asymmet ric
Pause
R/ W
See
Descr.
Updat e Writ e a 1b t o set asymmet ric pause.
10 Pause R/ W
See
Descr.
Updat e Writ e a 1b t o set pause.
9 100BASE-T4 R/ W 0b Ret ain Not able t o perform 100 Base-T4.
8
100BASE-TX
Full- Duplex
R/ W 1b Updat e Writ e a 1b t o advert ise.
7
100BASE-TX
Half- Duplex
6
10BASE-TX
Full- Duplex
5
10BASE-TX
Half- Duplex
4: 0 Select or Field R/ W 0x01 Ret ain Select or Field mode 00001b = 802. 3.
Tabl e 15. Li nk Par t ner Abi l i t y ( Base Page) Base PHY Addr ess 02, Page Any, Regi st er 5
15 Next Page RO 0b 0b
Received Code Word Bit 15
1b = Link part ner capable of next page.
0b = Link part ner not capable of next page.
14 Acknowledge RO 0b 0b
Acknowledge Received Code Word Bit 14
1b = Link part ner received link code word.
0b = Link part ner does not have Next Page abilit y.
13 Remot e Fault RO 0b 0b
Remot e Fault Received Code Word Bit 13
1b = Link part ner det ect ed remot e fault .
0b = Link part ner has not det ect ed remot e fault .
12
Technology
Abilit y Field
RO 0b 0b Received Code Word Bit 12
11
Asymmet ric
Pause
RO 0b 0b
1b = Link part ner request s asymmet ric pause.
0b = Link part ner does not request asymmet ric pause.
10
Pause
Capable
RO 0b 0b
1b = Link part ner is capable of pause operat ion.
0b = Link part ner is not capable of pause operat ion.
9
100BASE-T4
Capabilit y
RO 0b 0b
1b = Link part ner is 100BASE-T4 capable.
0b = Link part ner is not 100BASE-T4 capable.

54
8
100BASE-TX
Full- Duplex
Capabilit y
RO 0b 0b
1b = Link part ner is 100BASE-TX full- duplex capable.
0b = Link part ner is not 100BASE-TX full- duplex capable.
7
100BASE-TX
Half- Duplex
Capabilit y
RO 0b 0b
1b = Link part ner is 100BASE-TX half- duplex capable.
0b = Link part ner is not 100BASE-TX half- duplex capable.
6
10BASE-T
Full- Duplex
Capabilit y
RO 0b 0b
1b = Link part ner is 10BASE-T full- duplex capable.
0b = Link part ner is not 10BASE-T full- duplex capable.
5
10BASE-T
Half- Duplex
Capabilit y
RO 0b 0b
1b = Link part ner is 10BASE-T half- duplex capable.
0b = Link part ner is not 10BASE-T half- duplex capable.
4: 0 Select or Field RO 0x00 0x00 Select or Field Received Code Word Bit 4: 0
Tabl e 15. Li nk Par t ner Abi l i t y ( Base Page) Base PHY Addr ess 02, Page Any, Regi st er 5
Tabl e 16. Aut o- Negot i at i on Ex pansi on PHY Addr ess 02, Page Any , Regi st er 6
15: 5 Reserved RO 0x000 0x000 Reserved, must be set t o 0x000.
4
Parallel
Det ect ion Fault
RO, LH 0b 0b
Soft ware reset s t his bit t o 0b; clears it aft er a read.
1b = A fault has been det ect ed.
0b = A fault has not been det ect ed.
3
Link Part ner
Next page Able
RO 0b 0b
Soft ware reset s t his bit t o 0b; clears it aft er a read.
1b = Link part ner is next page able.
0b = Link part ner is not next page able.
2
Local Next Page
Able
RO 1b 1b
The soft ware reset value is det ermined by bit [ 15] of t he
Aut o- Negot iat ion Advert isement regist er and by bit s
[ 9: 8] of t he 1000 Base-T Cont rol regist er.
1b = Local device is next page able.
0b = Local device is not next page able.
1 Page Received RO, LH 0b 0b
On soft ware reset , t his bit value is reserved; LH; cleared
aft er a read.
1b = A new page has been received.
0b = A new page has not been received.
0
Link Part ner
Aut o-
Negot iat ion
Able
RO 0b 0b
Soft ware reset s t his bit t o 0b.
1b = Link part ner is aut o- negot iat ion able.
0b = Link part ner is not aut o- negot iat ion able.
Tabl e 17. Nex t Page Tr ansmi t PHY Addr ess 02, Page Any , Regi st er 7
15 Next Page R/ W 0b 0b Transmit code word bit 15.
14 Reserved RO 0b 0b Transmit code word bit 14.
13
Message Page
Mode
R/ W 1b 1b Transmit code word bit 13.
55
12 Acknowledge2 R/ W 0b 0b Transmit code word bit Bit 12.
11 Toggle RO 0b 0b Transmit code word bit 11.
10: 0
Message/
Unformat t ed
Field
R/ W 0x001 0x001 Transmit code word bit 10: 0.
Tabl e 17. Nex t Page Tr ansmi t PHY Addr ess 02, Page Any , Regi st er 7
Tabl e 18. Li nk Par t ner Nex t Page PHY Addr ess 02, Page Any , Regi st er 8
15 Next Page RO 0b 0b Received code word bit 15.
14 Acknowledge RO 0b 0b Received code word bit 14.
13 Message Page RO 0b 0b Received code word bit 13.
12 Acknowledge2 RO 0b 0b Received code word bit 12.
11 Toggle RO 0b 0b Received code word bit 11.
10: 0 Message Unformat t ed Field RO 0x000 0x000 Received code word bit 10: 0.
Tabl e 19. 1000BASE- T Cont r ol PHY Addr ess 02, Page Any , Regi st er 9
15: 13 Test Mode R/ W 000b Ret ain
The TX_TCLK is provided by t he RX_CLK pin for j it t er
t est ing in t est modes 2 and 3. Hardware reset or
soft ware reset ( see RESET ( bit [ 15] ) of t he regist er
Cont rol) should be issued t o ensure normal operat ion
aft er exit ing t he t est mode.
000b = Normal mode.
001b = Test Mode 1 - Transmit waveform t est .
010b = Test Mode 2 - Transmit j it t er t est ( mast er
mode) .
011b = Test Mode 3 - Transmit j it t er t est ( salve
mode) .
100b = Test Mode 4 - Transmit dist ort ion t est .
101b, 110b, 111b = Reserved.
12
Mast er/ Slave
Manual
Configurat ion
Enable
R/ W 0b Updat e
Mast er/ Slave Configurat ion Cont rol
1b = Manual mast er/ slave configurat ion.
0b = Aut omat ic mast er/ slave configurat ion.
11
Mast er/ Slave
Configurat ion
Value
R/ W
See
Descr.
Updat e
I gnored if bit [ 12] equals 0b.
1b = Manual configure as mast er.
0b = Manual configure as salve.
10 Port Type R/ W
See
Descr.
Updat e
I gnored if bit [ 12] equals 1b.
1b = Prefer mult i- port device ( mast er) .
0b = Prefer single port device ( slave) .
9
1000BASE-T
Full- Duplex
8
1000BASE-T
Half- Duplex
R/ W
See
Descr.
Updat e Writ e a 1b t o advert ise.
7: 0 Reserved R/ W 0x00 Ret ain Set t hese bit s t o 0x00.

56
Tabl e 20. 1000BASE- T St at us PHY Addr ess 02, Page Any , Regi st er 10
15
Mast er/ Slave
Configurat ion
Fault
RO, LH 0b 0b
This regist er bit get s cleared on a read.
1b = Mast er/ slave configurat ion fault det ect ed.
0b = No mast er/ slave configurat ion fault det ect ed.
14
Mast er/ Slave
Configurat ion
Resolut ion
RO 0b 0b
This regist er bit is not valid unt il t he PAGE_RECEI VED
( bit [ 1] ) of regist er Aut o- Negot iat ion Expansion is set t o
1b.
1b = Local PHY configurat ion resolved t o t he mast er.
0b = Local PHY configurat ion resolved t o t he slave.
13
Local Receiver
St at us
RO 0b 0b
1b = Local receiver is correct .
0b = Local receiver is incorrect .
12
Remot e
Receiver St at us
RO 0b 0b
1b = Remot e receiver is correct .
0b = Remot e receiver is incorrect .
11
Link Part ner
1000BASE-T
Full- Duplex
Capabilit y
RO 0b 0b
This regist er bit is not valid unt il PAGE_RECEI VED ( bit
[ 1] ) of regist er Aut o- Negot iat ion Expansion is set t o 1b.
1b = Link part ner is capable of 1000BASE-T full- duplex.
0b = Link part ner is not capable of 1000BASE-T full
duplex.
10
Link Part ner
1000BASE-T
Half- Duplex
Capabilit y
RO 0b 0b
This regist er bit is not valid unt il PAGE_RECEI VED ( bit
[ 1] ) of regist er Aut o- Negot iat ion Expansion is set t o 1b.
1b = Link part ner is capable of 1000BASE-T half- duplex
0b = Link part ner is not capable of 1000BASE-T half
duplex
9: 8 Reserved RO 00b 00b Reserved
7: 0
I dle Error
Count
RO, SC 0x00 0x00
Report s t he idle error count since t he last t ime t his
regist er was read. The count er st ops at 11111111 and
does not roll over. These bit s are cleared on a read.
Tabl e 21. Ex t ended St at us PHY Addr ess 02, Page Any , Regi st er 15
15
1000BASE-X
Full- Duplex
RO Always 0b Always 0b PHY not able t o perform 1000BASE-X full duplex.
14
1000BASE-X
Half- Duplex
RO Always 0b Always 0b PHY not able t o perform 1000BASE-X half duplex.
13
1000BASE-T
Full- Duplex
RO Always 1b Always 1b PHY able t o perform 1000BASE-T full duplex.
12
1000BASE-T
Half- Duplex
RO Always 0b Always 0b PHY not able t o perform 1000BASE-T half duplex.
11: 0 Reserved RO 0x000 0x000 Reserved
57
Tabl e 22. Funct i on Cont r ol 1 PHY Addr ess 02, Page 0, Regi st er 16
15: 12 Reserved R/ W 0x0 Updat e Reserved
11
Assert _
CRS_On_
Transmit
R/ W 0b Updat e
This bit has no effect in full- duplex.
0b = Never assert on t ransmit .
1b = Assert on t ransmit .
10 Reserved R/ W 0b Ret ain Reserved
9: 8
Energy
Det ect
R/ W
See
Descr.
Updat e
00b = Off.
10b = Sense only on receive ( energy det ect ) .
11b = Sense and periodically t ransmit NLP.
7 Reserved R/ W 0x0 Ret ain Reserved
6: 5
MDI
Crossover
Mode
R/ W 0x3 Updat e
Changes t o t hese bit s are disrupt ive t o normal operat ion.
As a result , any changes t o t hese regist ers must be
followed by a soft ware reset t o t ake effect .
00b = Manual MDI configurat ion.
01b = Manual MDI X configurat ion.
10b = Reserved.
11b = Enable aut omat ic crossover for all modes.
4: 3 Reserved R/ W 0x0 Ret ain Reserved
2 SQE_TEST R/ W 0b Ret ain
SQE t est is aut omat ically disabled in full- duplex mode
regardless of t he st at e of t his bit .
0b = SQE t est disabled.
1b = SQE t est enabled.
1
Polarit y
Reversal
Disable
R/ W 0b Ret ain
I f polarit y is disabled, t hen polarit y is forced t o be normal
in 10BASE-T.
1b = Polarit y reversal disabled.
0b = Polarit y reversal enabled.
0
Disable
Jabber
R/ W 0b Ret ain
1b = Disable j abber funct ion.
0b = Enable j abber funct ion.
Tabl e 23. PHY- Speci f i c St at us 1 PHY Addr ess 02, Page 0, Regi st er 17
15: 14 Speed RO 0x2 Ret ain
Valid only aft er resolved bit [ 11] of t his regist er =
11b. The resolved bit is set when aut o- negot iat ion
complet ed or aut o- negot iat ion is disabled.
11b = Reserved.
10b = 1000 Mb/ s.
01b = 100 Mb/ s.
00b = 10 Mb/ s.
13 Duplex RO 0b Ret ain
Valid only aft er resolved bit [ 11] of t his regist er = 1b.
The resolved bit is set when aut o- negot iat ion
complet ed or aut o- negot iat ion is disabled.
1 = Full- duplex.
0 = Half- duplex.
1b = Page received.
0 b= Page not received.
11
Speed and
Duplex
Resolved
RO 0b 0b
When aut o- negot iat ion is disabled, t his bit = 1b for
force speed.
1b = Resolved.
0b = Not resolved.

58
10
Copper Link
( real t ime)
RO 0b 0b
1b = Link up.
0b = Link down.
9: 7 Reserved RO 000b 000b Reserved, always set t o 000b.
6
MDI Crossover
St at us
RO 1b Ret ain
complet ed or aut o- negot iat ion is disabled. This bit is
0b or 1b depending on what is writ t en t o bit s [ 6: 5] of
regist er Funct ion Cont rol in manual configurat ion
mode. Funct ion Cont rol bit s [ 6: 5] are updat ed wit h a
soft ware reset .
1b = MDI -X.
0b = MDI .
5
Smart speed_
Downgrade
RO 0b 0b
1b = Smart speed downgrade occurs.
0b = Smart speed downgrade does not occur.
4
Energy Det ect
St at us
RO 0b 0b
1b= Sleep.
0b = Act ive.
3
Transmit _
Pause_Enabled
RO 0b 0b
complet ed or disabled. A reflect ion of t he MAC pause
resolut ion.
0b = Transmit pause disabled.
1b = Transmit pause enabled.
2
Receive_
Pause_Enabled
RO 0b 0b
A reflect ion of t he MAC pause resolut ion. This st at us
bit is valid only aft er resolved bit [ 11] of t his regist er
= 1b. The resolved bit is set when aut o- negot iat ion
complet ed or is disabled.
0b = Receive pause disabled.
1b = Receive pause enabled.
1
Polarit y ( real
t ime)
RO 0b 0b
1b = Reversed.
0b = Normal.
0
Jabber ( real
t ime)
RO 0b 0b
1b = Jabber.
0b = No j abber.
Tabl e 23. PHY- Speci f i c St at us 1 PHY Addr ess 02, Page 0, Regi st er 17
Tabl e 24. I nt er r upt Enabl e PHY Addr ess 02, Page 0, Regi st er 18
15
Aut o- Negot iat ion Error I nt errupt
Enable
R/ W 0b Ret ain
1b = I nt errupt enable.
0b = I nt errupt disable.
14 Speed Changed I nt errupt Enable R/ W 0b Ret ain
13 Duplex Changed I nt errupt Enable R/ W 0b Ret ain
12 Page Received I nt errupt Enable R/ W 0b Ret ain
11
Aut o- Negot iat ion Complet ed
I nt errupt Enable
R/ W 0b Ret ain
10
Link St at us Changed I nt errupt
Enable
R/ W 0b Ret ain
9 Symbol Error I nt errupt Enable R/ W 0b Ret ain
59
8 False Carrier I nt errupt Enable R/ W 0b Ret ain
7
FI FO Over/ Underflow I nt errupt
Enable
R/ W 0b Ret ain
I 1b = I nt errupt enable.
6
MDI Crossover Changed I nt errupt
Enable
R/ W 0b Ret ain
5 Smart speed I nt errupt Enable R/ W 0b Ret ain
4 Energy Det ect I nt errupt Enable R/ W 0b Ret ain
3: 2 Reserved R/ W 00b 00b Reserved, always set t o 00b.
1 Polarit y Changed I nt errupt Enable R/ W 0b Ret ain
0 Jabber I nt errupt Enable R/ W 0b Ret ain
Tabl e 24. I nt er r upt Enabl e PHY Addr ess 02, Page 0, Regi st er 18
Tabl e 25. I nt er r upt St at us PHY Addr ess 02, Page 0, Regi st er 19
15 Aut o- Negot iat ion Error RO,LH 0b 0b
An error occurs if t he mast er/ slave does
not resolve, parallel det ect fault , no
common HCD, or link does not come up
aft er negot iat ion complet ed.
0b = No aut o- negot iat ion error
1b = Aut o- negot iat ion error.
14 Speed Changed RO,LH 0b 0b
1b = Speed changed.
0b = Speed not changed.
13 Duplex Changed RO,LH 0b 0b
1b = Duplex changed.
0b = Duplex not changed.
1b = Page received.
0b = Page not received.
11 Aut o- Negot iat ion Complet ed RO,LH 0b 0b
1b = Aut o- negot iat ion complet ed.
0b = Aut o- negot iat ion not complet ed.
10 Link St at us Changed RO,LH 0b 0b
1b = Link st at us changed.
0b = Link st at us not changed.
9 Symbol Error RO,LH 0b 0b
1b = Symbol error.
0b = No symbol error.
8 False Carrier RO,LH 0b 0b
1b = False carrier.
0b = No false carrier.
7 FI FO_Over/ _Underflow RO 0b 0b
0b = No FI FO error
1b = Over/ underflow error.
6 MDI Crossover Changed RO,LH 0b 0b
1b = Crossover changed.
0b = Crossover not changed.
5 Smart speed_I nt errupt RO,LH 0b 0b
0b = No smart speed int errupt det ect ed.
1b = Smart speed int errupt det ect ed.
4 Energy Det ect Changed RO,LH 0b 0b
1b = Energy det ect st at e changed.
0b = No energy det ect st at e change
det ect ed.

60
3: 2 Reserved RO 0b 0b
1 Polarit y Changed RO,LH 0b 0b
1b = Polarit y changed.
0b = Polarit y not changed.
0 Jabber RO,LH 0b 0b
1b = Jabber.
0b = No j abber.
Tabl e 25. I nt er r upt St at us PHY Addr ess 02, Page 0, Regi st er 19
Tabl e 26. Ex t ended PHY- Speci f i c Cont r ol PHY Addr ess 02, Page 0, Regi st er 20
15: 11 Reserved R/ W 0x000 Ret ain Reserved, must be set t o 0x000.
10 aneg_now_qual R/ W 0b Ret ain
Set t ing t his bit t o 1b causes t he PHY t o rest art
aut o- negot iat ion.
This bit is self clearing.
9 Rev_aneg_qual R/ W 0b 0b
Makes t he PHY aut o- negot iat e in reversed mode.
This bit t akes it s value from t he input pin rev_aneg
by t he following:
Hardware reset ( fall of rst _dsp_i) .
PHY soft ware reset .
Rise of aneg_now.
8 Giga_dis_qual R/ W 0b 0b
Makes t he PHY disable GbE mode.
This bit t akes it s value from t he input pin giga_dis
by t he following:
Hardware reset ( fall of rst _dsp_i) .
PHY soft ware reset .
Rise of aneg_now.
7 Cfg_dis_qual R/ W 0b 0b
I f t his bit is set t o 1b, t hen t he aut o- negot iat ion
arbit rat ion FSM bypasses t he
LI NK_STATUS_CHECK st at e when t he 10BASE-T/
100BASE-T ready signal is assert ed.
The default value is 0b.
6 Mr_I t dis R/ W 0b 0b
I f t his bit is set t o 1b, t hen t he NLP receive link
int egrit y t est FSM st ays at t he NLP_TEST_PASS
st at e.
5 Smart speed_En R/ W 1b 1b
The default value is 1b if t his bit is set t o 1b and
t he cable inhibit s complet ion of t he t raining phase,
t hen aft er a few failed at t empt s, t he 82578
aut omat ically adj ust s t he highest abilit y t o t he
next lower speed: from 1000 Mb/ s t o 100 Mb/ s t o
10 Mb/ s.
61
4: 2
Smart speed_Ret ry_
Limit
R/ W 011b 011b
The default value is t hree; if set t o t hree, t hen t he
device at t empt s five t imes before adj ust ing; t he
number of at t empt s can be changed t hrough
set t ing t hese bit s.
000b = 2 ret ries.
001b = 3 ret ries.
010b = 4 ret ries.
011b = 5 ret ries ( default ) 100 = 6 ret ries.
101b = 7 ret ries.
110b = 8 ret ries.
111b = 9 ret ries.
1
Bypass_
Smart speed_Timer
R/ W 0b 0b
0b = The st able link condit ion is det ermined 2. 5
seconds aft er t he link is est ablished ( default ) .
1b = The st able link condit ion is det ermined as
soon as t he link is est ablished.
0 Reserved R/ W 0b 0b Reserved. Must be set t o 0b.
Tabl e 26. Ex t ended PHY- Speci f i c Cont r ol PHY Addr ess 02, Page 0, Regi st er 20
Tabl e 27. Recei ve Er r or Count er PHY Addr ess 02, Page 0, Regi st er 21
15: 0 Receive Error Count RO 0x00 00x00
Count er reaches it s maximum at 0xFFFF and does
not roll over ( when rx_dv is valid, count rx_er
numbers) . I n t his version, only for 100BASE-T and
1000BASE-T) .
Tabl e 28. Cabl e Def ect Test er Cont r ol PHY Addr ess 02, Page 0, Regi st er 22
9: 8 MDI _PAI _Select R/ W 00b 00b
Cable Defect Test er ( CDT) cont rol regist ers use t he
cable defect t est er cont rol regist ers t o select which
MDI pair is shown in t he Cable Defect Test er St at us
regist er.
00b = MDI [ 0] pair.
0 Enable_Test R/ W 0b 0b
When set , hardware aut omat ically disables t his bit
when CDT complet es.
0b = Disable CDT t est .
1b = Enable CDT t est .

62
Tabl e 29. LED Cont r ol PHY Addr ess 02, Page 0, Regi st er 24
15 Disable LED R/ W 0b Ret ain
0b = Enable.
1b = Disable.
14: 12 LED On Time R/ W 100b Ret ain
001b = 10 ms.
010b = 21 ms.
011b = 42 ms.
100b = 84 ms.
101b = 168 ms.
110b t o 111b = 42 ms.
11 Force I nt errupt RO 0b 0b Always 0b.
10: 8 LED On Time R/ W 001b Ret ain
000b = 21 ms.
001b = 42 ms.
010b = 84 ms.
011b = 168 ms.
100b = 330 ms.
101b t o 111b = 168 ms.
7: 5 Reserved RO 000b 000b Reserved
4: 3 LED_LI NK Cont rol R/ W 00b Ret ain
00b = Direct LED mode.
11b = Mast er/ slave LED mode.
01b, 10b = Combined LED modes.
2 LED_DUPLEX R/ W 0b Ret ain
0b = Duplex.
1b = Duplex/ collision.
1 LED_RX Cont rol R/ W 0b Ret ain
1b = Receive act ivit y/ link.
0b = Receive act ivit y.
0 Enable_Test R/ W 0b 0b
When set , hardware aut omat ically disables t his bit
when CDT complet es.
0b = Disable CDT t est .
1b = Enable CDT t est .
63
Tabl e 30. Manual LED Over r i de PHY Addr ess 02, Page 0, Regi st er 25
11: 10 LED_DUPLEX R/ W 00b Ret ain
LED off means LED pin out put equals high.
LED on means LED pin out put equals low.
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.
9: 8 LED_LI NK10 R/ W 00b Ret ain
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.
3: 2 LED_RX R/ W 00b Ret ain
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.
1: 0 LED_TX R/ W 00b Ret ain
00b = Normal.
01b = Blink.
10b = LED off.
11b = LED on.

64
Tabl e 31. Cabl e Def ect Test er St at us PHY Addr ess 02, Page 0, Regi st er 28
9: 8 St at us RO 00b 00b
The cont ent of t his regist er applies t o t he cable pair
select ed in t he Cable Defect Test er Cont rol regist er.
00b = Valid t est , normal cable ( no short or open in
cable) .
01b = Valid t est , short in cable ( impedance < 33 ) .
10b = Valid t est , open in cable ( impedance > 333 ) .
11b = Test failed.
7: 0 Delt a_Time RO 0x00 0x00 Delt a t ime t o indicat e dist ance
Tabl e 32. Debug Por t Addr ess Of f set PHY Addr ess 02, Page 0, Regi st er 29
5: 0 Address_Offset R/ W 0x00 0x00 Address index t o access t he debug regist ers.
Tabl e 33. Debug Por t Dat a PHY Addr ess 02, Page 0, Regi st er 30
15: 0 Dat a R/ W 0x024E
Dat a cont ent s of t he debug regist ers as addressed by
t he Debug Port Address Offset regist er.
65
8.5.1 Ex t ended Debug Por t Regi st er s
The following t he 82578 regist ers are referenced by t he Debug Port Address Offset and
t he Debug Port Dat a regist ers.
Tabl e 34. Syst em Mode Cont r ol 0, Addr ess Of f set = 0x 00
Tabl e 35. Syst em Mode Cont r ol 3, Addr ess Of f set = 0x 03
Tabl e 36. Hi ber nat i on Mode Cont r ol Regi st er , Addr ess Of f set = 0x 0B
15: 6 Reserved R/ W 0x009 Reserved
5: 4
TxDAC Class
Select
R/ W 00b Ret ain
Class AB, Class A Select Bit
1xb = 1000BT/ 100BT/ 10BT in class A mode.
01b = 1000BT/ 100BT/ 10BT in class AB.
00b = 1000BT in class AB mode, while 100BT/ 10BT
in class A mode.
15 Reserved R/ W 0b 0 Reserved
14 Tx_romi_sw R/ W 0b Ret ain
1b = A frame t ransmit t ed wit hin a rising of
link_st at us ( regist er17. 10) is never t ransmit t ed.
0b = Frames are t ransmit t ed when link is up.
13 Phy_pll_on R/ W 1b Ret ain
PLL Cont rol Bit
Makes an AND connect ion wit h t he input pin
phy_pll_on t o cont rol PLL.
1b = PLL is always on, except in iddq mode.
0b = PLL is cont rolled by t he hibernat e module.
12: 11 Reserved R/ W 11b Ret ain Reserved
10
LED t est
cont rol
R/ W 0b Ret ain
1b = Aft er power on reset , t he LED does not light .
0b = Aft er power on reset , t he LED does light for 2.5
seconds.
9: 0 Reserved R/ W 0x3FF Ret ain Reserved
15 Ps_hib_en R/ W 1b Ret ain
Power Hibernat e Cont rol Bit
1b = Hibernat e enable.
0b = Hibernat e disable.
14 Wake_mode R/ W 0b Ret ain
1b = PHY wake up by energy det ect or wake
up pin.
0b = PHY wake up only by energy det ect .
13 Reserved R/ W 1b Ret ain Reserved
12 Hib_pulse_sw R/ W 1b Ret ain
1b = When hibernat e, PHY sends NLP pulse
and det ect s signal from cable.
0b = When hibernat e, PHY doesn t send NLP
pulse and only det ect s signal from cable.
11 Gat e_25m_en_sw R/ W 1b Ret ain
1b = When hibernat e, shut off 25m clock of
aut o- negot iat ion.
0b = 25m clock t o aut o- negot iat ion is not
cont rolled by hibernat e.

66
Tabl e 37. 100BASE- TX Test Mode Regi st er , Addr ess Of f set = 0x 10
Tabl e 38. 1000BASE- T Test Mode Regi st er , Addr ess Of f set = 0x 11
Tabl e 39. 10BASE- T Test Mode Regi st er , Addr ess Of f set = 0x 12
Tabl e 40. Pow er Savi ng Cont r ol , Addr ess Of f set = 0x 29
15 TM100_ENA R/ W 0b Ret ain Enable dig100 loopback t est mode.
14: 8 Reserved R/ W 0x00 0b Reserved
7 Jit t er_t est R/ W 0b Ret ain 100BT j it t er t est .
6 Os_t est R/ W 0b Ret ain 100BT overshoot t est .
5 Dcd_t est R/ W 0b Ret ain 100BT DCD t est .
4 PMD_LPBK_2 R/ W 0b 0b
PMA loopback, t est MLT- 3 encoder and MLT- 3
decoder.
3 PMD_LPBK_1 R/ W 0b 0b PMD loopback, t est scrambler and descrambler.
2 PMA_LPBK_2 R/ W 0b 0b PMA loopback, t est carrier det ect and link monit or.
1 PMA_LPBK_1 R/ W 0b 0b PMA loopback, t est FEF generat or and FEF det ect or.
0 PCS_LPBK R/ W 0b 0b PCS loopback, t est pcs_t x and pcs_rx.
15: 1 Reserved R/ W 0x2AA9 Ret ain Reserved
0 Ext _lpbk_1000 R/ W 0b 0b
1b = Enable 1000BASE-T ext ernal loopback wit h
channel 0 < - > channel 1, channel 2 < - > channel
3.
5 Test _mode[ 2] R/ W 0b 0b
bit 2 of 3- bit t est _mode[ 2: 0] . See bit 1: 0 of
t his regist er.
4: 3 Reserved R/ W 00b 0b Reserved
2
Loopback mode
select
R/ W 0b 0b
1b = lpbk2deep in Loopback mode.
0b = lpbk1shallow in Loopback mode
( connect t o dig10. t est _mode_i[ 0] ) .
1: 0 Test _mode[ 1: 0] R/ W 00b 0b
Combined wit h bit 5:
001b = Packet wit h all ones, 10 MHz sine
wave.
010b = Pseudo random.
011b = Normal link pulse only.
100b = 5 MHz sin wave.
Ot hers: Normal mode.
15 Top_ps_en RO 1b Ret ain
1b = Top level power saving enable.
0b = Top level power saving disable.
14: 12 Dac_amp_1000 R/ W 0x3 Ret ain
Cont rol amplitude of t ransmit signal in 1000BT
mode.
Cont rol amplitude of t ransmit signal in 100BT
mode.
67
Cont rol amplit ude of t ransmit signal in 100BT
mode.
5: 1 Reserved R/ W 0x0 0 Reserved
0 ecnc_ps_en R/ W 1b Ret ain
1b = ecnc power saving enable.
0b = ecnc power saving disable.

68
8. 6 Por t Cont r ol Regi st er s ( Page 769)
Tabl e 41. Por t Gener al Conf i gur at i on PHY Addr ess 01, Page 769, Regi st er 17
Name Def aul t Bi t s Descr i pt i on Type
Tx Gat e Wait I FS 01110b 15: 11
Det ermines t he size ( in nibbles) of non-
deferring window from CRS de- assert ion.
R/ W
BP ext ension Wait 100b 10: 8
Addit ional wait ing byt e t imes aft er TX Gat e
Wait I PG expires unt il t he Back Pressure I n-
band bit is cleared.
R/ W
Reserved 0b 7 Reserved R/ W
Act ive_PD_enable 0b 6
Act ive Power Down Enable ( sD3 Enable)
When set t o 1b, t he I nt el 5 Series Express
Chipset needs t o ent er MAC power down
mode.
R/ W
Reserved 1b 5
Reserved. This bit is reset by power on reset
only.
Host _WU_Act ive 0b 4
Enables host wake up from t he 82578. This
bit is reset by power on reset only.
R/ W
Wakeup clocks st op 1b 3
Wake- up clocks are st opped while wake up is
disabled.
R/ W
MACPD_enable 1b 2
Writ t en as 1b when needs t o globally enable
t he MAC power down feat ure while t he
82578 support s WoL. When set t o 1b, pages
800 and 801 are enabled for configurat ion
and Host _WU_Act ive, ME_WU_Act ive are not
blocked for writ es.
R/ W
Reserved 00b 1: 0 Reserved RO
Tabl e 42. Pow er Management Cont r ol Regi st er PHY Addr ess 01, Page 769, Regi st er 21
Reserved 0x00 15: 9 Reserved, writ e t o 0x00 RO
Collision t hreshold 0x0F 8: 1 Number of ret ries for a collided packet . R/ W
Ret ry lat e collision 0b 0 Ret ry lat e collision. R/ W
Tabl e 43. SMBus Cont r ol Regi st er PHY Addr ess 01, Page 769, Regi st er 23
Reserved 0x0000 15: 2 Reserved RO
dis_SMB_filt ering 0b 1
When set , disables filt ering of Rx packet s for
t he SMBus.
I n wake up mode, t his configurat ion is
ignored and t he filt ers are enabled.
R/ W
Reserved 0b 0 Reserved. RO
69
8.7 St at i st i cs Regi st er s
This regist er count s t he number of t imes t hat a successfully t ransmit t ed packet
encount ered a single collision. This regist er only increment s if t ransmit s are enabled
and t he 82578 is in half- duplex mode.
When 16 or more collisions have occurred on a packet , t his regist er increment s,
regardless of t he value of collision t hreshold. I f collision t hreshold is set below 16, t his
count er wont increment . This regist er only increment s if t ransmit s are enabled and t he
82578 is in half- duplex mode.
Tabl e 44. Rat e Adapt at i on Cont r ol Regi st er PHY Addr ess 01, Page 769, Regi st er 25
Reserved 0100010b 15: 9 Reserved, writ e as read. RWP
rx_en_rxdv_preamble 1b 8
Enable generat ion of early preamble based on
RX_DV in t he receive pat h.
R/ W
rx_en_crs_preamble 0b 7
Enable generat ion of early preamble based on
CRS in t he receive pat h.
R/ W
reserved 0b 6 Reserved, writ e as read. RWP
rx_flip_bad_sfd 1b 5
Align t he packet s st art of frame delimit er t o a
byt e boundary in t he receive pat h.
R/ W
read_delay_fd 10001b 4: 0 Reserved, writ e as read. RWP
Tabl e 45. Fl ow Cont r ol Tr ansmi t Ti mer Val ue PHY Addr ess 01, Page 769, Regi st er 27
Name Def aul t Bi t s Descr i pt i on Ty pe
Flow Cont rol Transmit Timer
Value
0x0000 15: 0
The TTV field is insert ed int o a t ransmit t ed
frame ( eit her XOFF frames or any pause frame
value in any soft ware t ransmit t ed packet s) . I t
count s in unit s of slot t ime. I f soft ware needs
t o send an XON frame, it must set TTV t o
0x0000 prior t o init iat ing t he pause frame.
RW
Tabl e 46. Si ngl e Col l i si on Count - SCC PHY Addr ess 01, Page 778, Regi st er s 16 - 17
Bi t Ty pe Reset Descr i pt i on
31: 0 RO/ V 0x00
SCC
Number of t imes a t ransmit encount ered a single collision.
Tabl e 47. Ex cessi v e Col l i si ons Count - ECOL PHY Addr ess 01, Page 778, Regi st er 18 - 19
31: 0 RO/ V 0x00
ECC
Number of packet s wit h more t han 16 collisions.
Tabl e 48. Mul t i pl e Col l i si on Count - MCC PHY Addr ess 01, Page 778, Regi st er 20 - 21
31: 0 RO/ V 0x00
MCC
Number of t imes a successful t ransmit encount ered mult iple collisions.

70
This regist er count s t he number of t imes t hat a t ransmit encount ered more t han one
collision but less t han 16. This regist er only increment s if t ransmit s are enabled and t he
82578 is in half- duplex mode.
Lat e collisions are collisions t hat occur aft er one slot t ime. This regist er only increment s
if t ransmit s are enabled and t he 82578 is in half- duplex mode.
This regist er count s t he t ot al number of collisions seen by t he t ransmit t er. This regist er
only increment s if t ransmit s are enabled and t he 82578 is in half- duplex mode. This
regist er applies t o clear as well as secure t raffic.
This regist er count s defer event s. A defer event occurs when t he t ransmit t er cannot
immediat ely send a packet due t o t he medium busy eit her because anot her device is
t ransmit t ing, t he I PG t imer has not expired, half- duplex deferral event s, recept ion of
XOFF frames, or t he link is not up. This regist er only increment if t ransmit s are
enabled. The behavior of t his count er is slight ly different in t he 82578 relat ive t o t he
82542. For t he 82578, t his count er does not increment for st reaming t ransmit s t hat are
deferred due t o TX I PG.
This regist er count s t he number of successful packet t ransmission in which t he CRS
input from t he 82578 was not assert ed wit hin one slot t ime of st art of t ransmission
from t he MAC. St art of t ransmission is defined as t he assert ion of TX_EN t o t he 82578.
Tabl e 49. Lat e Col l i si ons Count - LATECOL PHY Addr ess 01, Page 778, Regi st er 23 - 24
31: 0 RO/ V 0x00
LCC
Number of packet s wit h lat e collisions.
Tabl e 50. Col l i si on Count - COLC PHY Addr ess 01, Page 778, Regi st er 25 - 26
31: 0 RO/ V 0x00
COLC
Tot al number of collisions experienced by t he t ransmit t er.
Tabl e 51. Def er Count - DC PHY Addr ess 01, Page 778, Regi st er 27 - 28
31: 0 RO/ V 0x00
CDC
Number of defer event s.
Tabl e 52. Tr ansmi t w i t h No CRS - TNCRS PHY Addr ess 01, Page 778, Regi st er 29 - 30
31: 0 RO/ V 0x00
TNCRS
Number of t ransmissions wit hout a CRS assert ion from t he 82578.
71
The 82578 should assert CRS during every t ransmission. Failure t o do so might indicat e
t hat t he link has failed, or t he 82578 has an incorrect link configurat ion. This regist er
only increment s if t ransmit s are enabled. This regist er is only valid when t he 82578 is
operat ing at half duplex.
8.8 PCI e Regi st er s
Tabl e 53. PCI e FI FOs Cont r ol / St at us PHY Addr ess 01, Page 770, Regi st er 16)
Rx FI FO overflow 0b 8 Rx FI FO overflow occurred. RO/ SC
Reserved 0b 7 Reserved RO
Tx FI FO overflow 0b 6 Tx FI FO overflow occurred. RO/ SC
Tabl e 54. PCI e Pow er Management Cont r ol PHY Addr ess 01, Page 770, Regi st er 17
Burst enable 1b 15
Burst in 10/ 100 Mb/ s Enable
1b = Burst ing at 10/ 100 Mb/ s speed is
enabled.
0b = Burst ing disabled at 10/ 100 Mb/ s.
RW
Reserved 00b 14: 13 Reserved R/ W
Reserved 000b 12: 10 Reserved. RO
Reserved 10b 9: 8 Reserved. R/ W
Reserved 1b 7 Reserved R/ W
Reserved 0b 0B Reserved R/ W

72
Tabl e 55. I n- Band Cont r ol PHY Addr ess 01, Page 770, Regi st er 18
1
Link st at us t ransmit t imeout 0x5 15: 8
Link st at us ret ransmission period in t ens of
microseconds.
R/ W
pcie_pad_use_dis 0b 7
Disables 1000 Mb/ s inband messages during
packet s in 10/ 100 Mb/ s mode.
R/ W
Max ret ries 0x7 6: 0
Maximum ret ries when not receiving an
acknowledge t o an inband message.
R/ W
1. All inband t imeout s are mult iplied by 1000 while in SMBus mode.
Tabl e 56. PCI e Di agnost i c PHY Addr ess 01, Page 770, Regi st er 20
1
Reserved 0x55 15: 8 Reserved, writ e as read. R/ W
I n- band st at us acknowledge
t imeout
0x04 7: 0
Timeout in microseconds for receiving an
acknowledge for an inband st at us message.
R/ W
Tabl e 57. Ti meout s PHY Addr ess 01, Page 770, Regi st er 21
1
Reserved 0000b 15: 12 Reserved, writ e as read. RWP
Tabl e 58. PCI e Kst at e Mi ni mum Dur at i on Ti meout PHY Addr ess 01, Page 770, Regi st er
23
1
Reserved 0x00 15: 5 Reserved, writ e as read. RWP
EI _min_dur t imeout 0x10 4: 0
These bit s define t he minimum t ime t he 82578
st ays in elect rical idle st at e once ent ered ( each
bit represent s 100 ns) .
R/ W
73
8.9 Gener al Regi st er s
The 82578 Capabilit y regist er is loaded wit h t he set of capabilit ies t hat correspond t o
t he select ed t he 82578 SKU. A change in SKU is reflect ed in a change in t his regist er. A
capabilit y is enabled when it s corresponding bit is set t o 1b.
Tabl e 59. 82578 Capabi l i t y PHY Addr ess 01, Page 776, Regi st er 19
Reserved 000000b 15: 10 Reserved for fut ure capabilit ies. RO
802. 1Q & 802. 1p 0b 8
802. 1Q & 802. 1p
Enables support for VLAN per 802. 1Q &
802. 1p.
RO
Receive Side Scaling 0b 7
Receive Side Scaling ( RSS)
Enables RSS.
RO
2 Tx and 2 Rx Queues 0b 6
Two Tx and 2 Rx Queues
When set , enables dual t ransmit and dual
receive queues. When cleared, a single receive
and a single t ransmit queue are enabled.
RO
Energy Det ect 0b 5
Energy Det ect
Enables energy det ect capabilit y.
RO
AC/ DC Aut o Link Speed
Connect
0b 4
AC/ DC Aut o Link Speed Connect
Enables different power management policy in
AC and bat t ery modes.
RO
Abilit y t o init iat e a t eam 0b 0
Abilit y t o init iat e a t eam; enables t eaming
capabilit y.
RO
Tabl e 60. OEM Bi t s PHY Addr ess 01, Page 0, Regi st er 25
Bi t s Fi el d Mode HW Rst Descr i pt i on
15: 11 Reserved R/ W 00000b
10 Aneg_now R/ W 0b Rest art aut o- negot iat ion. This bit is self clearing.
6 a1000_dis R/ W 0b
1
When set t o 1b, 1000 Mb/ s speed is disabled.
2 rev_aneg R/ W 0b
Low Power Link Up mechanism. Allows a link t o come up at
t he lowest possible speed in cases where power is more
import ant t han performance.
1. 0b is t he default value aft er power on reset . When PE_RST_N goes low ( swit ches t o SMBus) , it s value becomes
1b.

74
Tabl e 61. SMBus Addr ess PHY Addr ess 01, Page 0, Regi st er 26
1
Reserved 0x00 15: 12 Reserved RO
SMB fragment s size 0b 11
Select SMBus Fragment s Size
When set t o 1b, t he fragment size is 64 byt es,
ot herwise 32 byt es.
RW
APM Enable 0b 10 APM WoL enable. RW
PEC Enable 1b 9
Defines if t he 82578 support s PEC on t he
SMBus.
RW
SMBus Frequency 0b 8
0b = 100 KHz.
1b = Reserved
RW
SMBus Address Valid 0b 7
0b = Address not valid.
1b = SMBus address valid.
This bit is writ t en by t he MAC when t he SMBus
Addr ess field is updat ed. The 82578 cannot
send SMBus t ransact ions t o t he MAC unless
t his bit is set .
RW
SMBus Address 0x00 6: 0
This is t he MAC SMBus address. The 82578
uses it for mast er funct ionalit y.
RW
1. This regist er is reset only on int ernal power on reset .
Tabl e 62. Shadow Recei ve Addr ess Low 0 SRAL0 PHY Addr ess 01, Page 0, Regi st er s
27- 28
At t r i but e Bi t ( s)
I ni t i al
Val ue
Descr i pt i on
RW 31: 0 X
Receive Address Low ( RAL)
The lower 32 bit s of t he 48- bit Et hernet address n ( n= 0, 16) . RAL 0 is loaded
from words 0x0 and 0x1 in t he NVM.
Tabl e 63. Shadow Recei v e Addr ess Hi gh0 RAH0 PHY Addr ess 01, Page 0, Regi st er s 29
I ni t i al
Val ue
Descr i pt i on
RW 15: 0 X
Receive Address High ( RAH)
The upper 16 bit s of t he 48- bit Et hernet address n ( n= 0, 16) . RAH 0 is loaded
from word 0x2 in t he NVM.
RW 17: 16 X
Address Select ( ASEL)
Select s how t he address is t o be used and is decoded as follows:
00b = Dest inat ion address ( must be set t o t his in normal mode) .
01b = Source address.
10b = Reserved.
11b = Reserved.
RO 30: 18 0x00 Reserved, reads as 0b and ignored on writ es.
RW 31
See
Desc.
Address valid ( AV)
Cleared aft er mast er reset . I f t he NVM is present , t he Address Valid field of
Receive Address Regist er 0 is set t o one aft er a soft ware or PCI reset or NVM
read.
This bit is cleared by a mast er ( soft ware) reset .
75
NOTES:
1. When LED Blink mode is enabled t he appropriat e Led I nvert bit should be set t o zero.
2. The dynamic LED' s modes ( LI NK/ ACTI VI TY and ACTI VI TY) should be used wit h LED Blink mode enabled.
8.9.1 I nt er r upt s
The 82578 maint ains st at us bit s ( per int errupt cause) t o reflect t he source of t he
int errupt request . Syst em soft ware is expect ed t o clear t hese st at us bit s once t he
int errupt is being handled.
Tabl e 64. LED Conf i gur at i on PHY Addr ess 01, Page 0, Regi st er 30
Blink rat e 0b 15
Specifies t he blink mode of t he LEDs.
0b = Blinks at 200 ms on and 200 ms off.
1b = Blinks at 83 ms on and 83 ms off.
RW
LED2 Blink 0b 14
LED2_BLI NK Field
0b = No blinking.
1b = Blinking.
RW
LED2 I nvert 0b 13
LED2_I VRT Field
0b = Act ive low out put .
1b = Act ive high out put .
RW
LED2 Mode 110b 12: 10 Mode specifying what event / st at e/ pat t ern is displayed on LED2. RW
LED1 Blink 0b 9
LED1_BLI NK Field
0b = No blinking.
1b = Blinking.
RW
LED1 I nvert 0b 8
LED1_I VRT Field
RW
LED0 Blink 1b 4
LED0_BLI NK Field
0b = No blinking.
1b = Blinking.
RW
LED0 I nvert 0b 3
LED0_I VRT Field
RW

76
8.10 Wak e Up Regi st er s
8.10.1 Accessi ng Wak e Up Regi st er s Usi ng MDI C
When soft ware needs t o configure t he wake up st at e ( eit her read or writ e t o t hese
regist ers) t he MDI O page should be set t o 800 ( for host accesses) unt il t he page is not
changed t o a different value wake up regist er access is enabled. Aft er t he page was set
t o t he wake up page, t he address field is no longer t ranslat ed as reg_addr ( regist er
address) but as an inst ruct ion. I f t he given address is in t he [ 0. . 15] range, meaning
PHY regist ers, t he funct ionalit y remains unchanged. There are t wo valid inst ruct ions:
1. Address Set 0x11 Wake up space address is set for eit her reading or writ ing.
2. Dat a cycle 0x12 Wake up space accesses read or writ e cycle.
For t he 82578 t he wake area read cycle sequence of event s is as follows:
1. Set t ing page 800; t he soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
b. Op- Code = 01b ( writ e)
c. PHYADD = The 82578s address from t he MDI regist er
d. REGADD = Page set t ing
e. DATA = 800 ( wake up page)
2. Address set t ing; t he soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
d. REGADD = 0x11 ( address set )
e. DATA = XXXX ( address of t he regist er t o be read)
3. Reading a regist er; t he soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
b. Op- Code = 10b ( read)
d. REGADD = 0x12 ( dat a cycle for read)
e. DATA = YYYY ( dat a is valid when t he ready bit is set )
For t he 82578, t he wake area writ e cycle sequence of event s is as follows:
1. Set t ing page 800; t he soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
d. REGADD = Page set t ing
e. DATA = 800 ( wake up page)
77
2. Address set t ing; The soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
d. REGADD = 0x11 ( address set )
e. DATA = XXXX ( address of t he regist er t o be read)
3. Writ ing a regist er; t he soft ware device driver performs a writ e cycle t o t he MDI
regist er wit h:
a. Ready = 0b
d. REGADD = 0x12 ( dat a cycle for writ e)
e. DATA = YYYY ( dat a t o be writ t en t o t he regist er)
8.10. 2 Host Wak e Up Cont r ol St at us Regi st er Descr i pt i on
Tabl e 65. Recei ve Cont r ol RCTL PHY Addr ess 01, Page 800, Regi st er 0
I ni t i al
Val ue
Descr i pt i on
RW 0 0b
Unicast Promiscuous Enable ( UPE)
0b = Disabled.
1b = Enabled.
RW 1 0b
Mult icast Promiscuous Enable ( MPE)
0b = Disabled.
1b = Enabled.
RW 2 1b
Slave Access Enable
0b = Access disabled, t he filt ers are act ive.
1b = Access enabled, t he filt ers are not act ive.
RW 4: 3 00b
Mult icast Offset ( MO)
This det ermines which bit s of t he incoming mult icast address are used in
looking up t he bit vect or.
00b = [ 47: 38] .
01b = [ 46: 37] .
10b = [ 45: 36] .
11b = [ 43: 34] .
RW 5 0b
Broadcast Accept Mode ( BAM)
0b = I gnore broadcast ( unless it mat ches t hrough exact or imperfect filt ers)
1b = Accept broadcast packet s.
RW 6 0b
Pass MAC Cont rol Frames ( PMCF) .
0b = Do not ( specially) pass MAC cont rol frames.
1b = Pass any MAC cont rol frame ( t ype field value of 0x8808) .
RW 7 0b
Receive Flow Cont rol Enable ( RFCE)
I ndicat es t hat t he 82578 responds t o t he recept ion of flow cont rol packet s. I f
aut o- negot iat ion is enabled, t his bit is set t o t he negot iat ed duplex value.
RW 8 0b Reserved
RW 15: 9 0x00 Reserved

78
Not e: All wake up regist ers ( page 800- 801 except CTRL and I PAV) are not cleared wit h PHY
reset is assert ed. I t is only cleared when int ernal power on reset is de- assert ed or when
cleared by t he soft ware device driver.
Not e: Access t o page 800/ 801 should be done only in 10 Mb/ s and 100 Mb/ s.
PMCF cont rols t he usage of MAC cont rol frames ( including flow cont rol) . A MAC cont rol
frame in t his cont ext must be addressed t o t he flow cont rol mult icast address
0x0100_00C2_8001 and mat ch t he t ype field ( 0x8808) . I f PMCF= 1b, t hen frames
meet ing t his crit eria part icipat e in wake up filt ering.
Tabl e 66. Wak e Up Cont r ol WUC PHY Addr ess 01, Page 800, Regi st er 1
At t r i but e Bi t ( s) I ni t i al Val ue Descr i pt i on
RW/ SN 0 0b
Advance Power Management Enable ( APME)
I f set t o 1b, APM wake up is enabled.
RW/ V 1 0b
PME_En
I f set t o 1b, ACPI wake up is enabled.
RWC 2 0b
PME_St at us
This bit is set when t he 82578 receives a wake up event .
RO 3 0b Reserved
RW/ SN 4 0b
Link St at us Change Wake Enable ( LSCWE)
Enables wake on link st at us change as part of APM wake capabilit ies.
RW/ SN 5 0b
Link St at us Change Wake Override ( LSCWO)
I f set t o 1b, wake on link st at us change does not depend on t he LNKC bit
in t he WUFC regist er. I nst ead, it is det ermined by t he APM set t ings in t he
WUC regist er.
RO 15: 6 0x00 Reserved
79
This regist er is used t o enable each of t he predefined and flexible filt ers for wake up
support . A value of 1b means t he filt er is t urned on, and a value of 0b means t he filt er
is t urned off.
Tabl e 67. Wak e Up Fi l t er Cont r ol WUFC PHY Addr ess 01, Page 800, Regi st er 2
I ni t i al
Val ue
Descr i pt i on
RW 0 0b
LNKC
Link st at us change wake up enable.
RW 1 0b
MAG
Magic packet wake up enable.
RW 2 0b
EX
Direct ed exact wake up enable.
RW 3 0b
MC
Direct ed mult icast wake up enable.
RW 4 0b
BC
Broadcast wake up enable.
RW 5 0b Reserved
RW 6 0b
I PV4
Direct ed I Pv4 packet wake up enable.
RW 7 0b
I PV6
Direct ed I Pv6 packet wake up enable.
RO 8 0b Reserved.
RW 9 0
FLX4
Flexible filt er 3 enable.
RW 10 0b
FLX5
Flexible filt er 3 enable.
RW 11 0b
NoTCO
I gnore TCO packet s for host wake up. I f t he NoTCO bit is set , t hen any packet
t hat passes t he manageabilit y packet filt ering does not cause a host wake up
event even if it passes one of t he host wake up filt ers.
RW 12 0b
FLX0
Flexible filt er 0 enable
RW 13 0b
FLX1
RW 14 0b
FLX2
RW 15 0b
FLX3

80
This regist er is used t o record st at ist ics about all wake up packet s received. Not e t hat
packet s t hat mat ch mult iple crit eria might set mult iple bit s. Writ ing a 1b t o any bit
clears t hat bit .
This regist er is not cleared when PHY reset is assert ed. I t is only cleared when int ernal
power on reset is de- assert ed or when cleared by t he soft ware device driver.
Tabl e 68. Wak e Up St at us WUS PHY Addr ess 01, Page 800, Regi st er 3
I ni t i al
Val ue
Descr i pt i on
RWC 0 0b
LNKC
Link st at us changed
RWC 1 0b
MAG
Magic packet received
RWC 2 0b
EX
Direct ed exact packet received. The packet s address mat ched one of t he 7 pre-
programmed exact values in t he Receive Address regist ers.
RWC 3 0b
MC
Direct ed mult icast packet received. The packet was a mult icast packet t hat was
hashed t o a value t hat corresponded t o a 1- bit in t he mult icast t able array.
RWC 4 0b
BC
Broadcast packet received.
RWC 5 0b I Pv4 request packet received.
RWC 6 0b
I PV4
Direct ed I Pv4 packet received.
RWC 7 0b
I PV6
Direct ed I Pv6 packet received.
RO 8 0b Reserved, read as 0b.
RWC 9 0b
FLX4
Flexible filt er 4 mat ch.
RWC 10 0b
FLX5
RO 11 0b Reserved.
RWC 12 0b
FLX0
RWC 13 0b
FLX1
RWC 14 0b
FLX2
RWC 15 0b
FLX3
81
AV det ermines whet her t his address is compared against t he incoming packet . AV is
cleared by a mast er ( soft ware) reset .
ASEL enables t he 82578 t o perform special filt ering on receive packet s.
Not e: RAR0 should always be used t o st ore t he individual Et hernet MAC address of t he
Net work I nt erface Card ( NI C) .
Aft er reset , if t he NVM is present , t he first regist er ( Receive Address Regist er 0) is
loaded from t he I A field in t he NVM, it s Address Select field is 00b, and it s Address
Valid field is 1b. I f no NVM is present t he Address Valid field is 0b. The Address Valid
field for all of t he ot her regist ers are 0b.
Tabl e 69. Recei ve Addr ess Low RAL PHY Addr ess 01, Page 800, Regi st er s 16- 17 +
4* n
1
( n= 06)
I ni t i al
Val ue
Descr i pt i on
RW 31: 0 0
The lower 32 bit s of t he 48- bit Et hernet address n ( n= 0, 16) . RAL 0 is loaded
from words 0x0 and 0x1 in t he NVM.
1. While n is t he exact unicast / mult icast address ent ry and it is equals t o 0, 1, 6.
Tabl e 70. Recei ve Addr ess Hi gh RAH PHY Addr ess 01, Page 800, Regi st er s 18- 19 +
4* n
1
( n= 06)
I ni t i al
Val ue
Descr i pt i on
RW 15: 0 X
The upper 16 bit s of t he 48- bit Et hernet address n ( n= 0, 16) . RAH 0 is loaded
from word 0x2 in t he NVM.
RW 17: 16 X
Select s how t he address is t o be used and is decoded as follows:
10b = Reserved.
11b = Reserved.
RO 30: 18 0x00 Reserved, reads as 0b and ignored on writ es.
RW 31
See
Desc.
Address valid ( AV)
Cleared aft er mast er reset . I f t he NVM is present , t he Address Valid field of
Receive Address Regist er 0 is set t o one aft er a soft ware or PCI reset or NVM
read.
This bit is cleared by a mast er ( soft ware) reset .
1. While n is t he exact unicast / Mult icast address ent ry and it is equals t o 0, 1, 6

82
.
Tabl e 71. Shar ed Recei v e Addr ess Low SHRAL PHY Addr ess 01, Page 800, Regi st er s
44- 45 + 4* n ( n= 03)
I ni t i al
Val ue
Descr i pt i on
RW 31: 0 X
The lower 32 bit s of t he 48- bit Et hernet address n ( n= 03) .
Tabl e 72. Shar ed Recei v e Addr ess Hi gh SHRAH PHY Addr ess 01, Page 800, Regi st er s
46- 47 + 4* n ( n= 02)
I ni t i al
Val ue
Descr i pt i on
RW 15: 0 X
The upper 16 bit s of t he 48- bit Et hernet address n ( n= 03) .
RO 17: 16 0x00
Select s how t he address is t o be used. 00b means t hat it is used t o decode t he
dest inat ion MAC address.
RO 30: 18 0x00 Reserved, reads as 0b and is ignored on writ es.
RW 31 0b
Address valid ( AV)
When t his bit is set , t he relevant RAL and RAH are valid ( compared against t he
incoming packet ) .
Tabl e 73. Shar ed Recei v e Addr ess Hi gh 3 SHRAH[ 3] PHY Addr ess 01, Page 800,
Regi st er s 58- 59
I ni t i al
Val ue
Descr i pt i on
RW 15: 0 X
The upper 16 bit s of t he 48- bit Et hernet address n ( n= 03) .
RO 17: 16 00b
Select s how t he address is t o be used. 00b means t hat it is used t o decode t he
dest inat ion MAC address.
RO 29: 18 0x00 Reserved, reads as 0x00 and is ignored on writ es.
RW 30 0b
All Nodes Mult icast Address valid ( MAV)
The all nodes mult icast address ( 33: 33: 00: 00: 00: 01) is valid when t his bit is
set . Not e t hat 0x33 is t he first byt e on t he wire.
RW 31 0b
Address valid ( AV)
When t his bit is set , t he relevant address 3 is valid ( compared against t he
incoming packet ) .
83
The I Pv6 address t able is used t o st ore t he I Pv6 addresses for direct ed I Pv6 packet
wake ups and manageabilit y t raffic filt ering.
I P6AT can be used by t he host .
There is one regist er per 32 bit s of t he mult icast address t able for a t ot al of 32 regist ers
( t hus t he MTA[ 31: 0] designat ion) . The size of t he word array depends on t he number
of bit s implement ed in t he mult icast address t able. Soft ware must mask t o t he desired
bit on reads and supply a 32- bit word on writ es.
Not e: All accesses t o t his t able must be 32- bit .
Tabl e 74. I P Addr ess Val i d I PAV
1
PHY Addr ess 01, Page 800, Regi st er 64
RO 0 0b Reserved
RW 1 0b
V41
I Pv4 address 1 valid.
RW 2 0b
V42
RW 3 0b
V43
RO 4: 14 0x00 Reserved
RW 15 0b
V60
I Pv6 address valid.
1. The I P address valid indicat es whet her t he I P addresses in t he I P address t able are valid.
Tabl e 75. I Pv4 Addr ess Tabl e I P4AT
1
PHY Addr ess 01, Page 800, Regi st er s 82- 83 +
2* n ( n= 0, 1, 2)
RW 31: 0 X
I PADD
I P address n ( n= 0, 1, 2) .
1. The I Pv4 address t able is used t o st ore t he t hree I Pv4 addresses for I Pv4 request packet s and direct ed I Pv4
packet wake ups. I t is a 3- ent ry t able wit h t he following format :
Tabl e 76. I Pv6 Addr ess Tabl e I P6AT PHY Addr ess 01, Page 800, Regi st er s 88- 89 + 2* n
( n= 03)
RW 31: 0 X
I PV6 Address
I Pv6 address byt es n* 4n* 4+ 3 ( n= 0, 1, 2, 3) while byt e 0 is first on
t he wire and byt e 15 is last .
Tabl e 77. Mul t i cast Tabl e Ar r ay MTA[ 31: 0] PHY Addr ess 01, Page 800, Regi st er s 128-
191
I ni t i al
Val ue
Descr i pt i on
RW 31: 0 X
Bit Vect or.
Word- wide bit vect or specifying 32 bit s in t he mult icast address filt er t able.

84
Figure 9 shows t he mult icast lookup algorit hm. The dest inat ion address shown
represent s t he int ernally st ored ordering of t he received dest inat ion address. Not e t hat
Byt e 1 bit 0 shown in Figure 9 is t he first on t he wire. The bit s t hat are direct ed t o t he
mult icast t able array in t his diagram mat ch a mult icast offset in t he CTRL regist er
equals 00b. The complet e mult icast offset opt ions are:
Fi gur e 9. Mul t i cast Tabl e Ar r ay Al gor i t hm
There are 128 filt er values. The flexible filt er value is used t o st ore t he one value for
each byt e locat ion in a packet for each flexible filt er. I f t he corresponding mask bit is
one, t hen t he flexible filt er compares t he incoming dat a byt e t o t he values st ored in t his
t able.
Mul t i cast
Of f set
Bi t s Di r ect ed t o t he Mul t i cast Tabl e Ar r ay
00b DA[ 47: 38] = Byt e 6 bit s 7: 0, Byt e 5 bit s 1: 0
Tabl e 78. Fl ex i bl e Fi l t er Val ue Tabl e LSB FFVT_01 PHY Addr ess 01, Page 800, Regi st er s
256 + 2* n ( n= 0127)
RW 7: 0 X
Value 0
Value of filt er 0 byt e n ( n= 0, 1127) .
RW 15: 8 X
Value 1
85
I n t he 82578 since each address cont ains 16 bit s, only t he least significant byt es are
st ored in t hose addresses.
one, t hen t he flexible filt er compares t he incoming dat a byt e t o t he values st ored in t his
t able.
I n t he 82578 since each address cont ains 16 bit s, only t he most significant byt es are
st ored in t hose addresses.
Not e: Before writ ing t o t he flexible filt er value t able t he soft ware device driver must first
disable t he flexible filt ers by writ ing zeros t o t he Flexible Filt er Enable bit s of t he WUFC
regist er ( WUFC. FLXn) .
Tabl e 79. Fl ex i bl e Fi l t er Val ue Tabl e MSBs FFVT_23 PHY Addr ess 01, Page 800,
Regi st er s 257 + 2* n ( n= 0127)
RW 7: 0 X
Value 2
RW 15: 8 X
Value 3
Tabl e 80. Fl ex i bl e Fi l t er Val ue Tabl e FFVT_45 PHY Addr ess 01, Page 800, Regi st er s
512 + 2* n ( n= 0127)
RW 7: 0 X
Value 4
RW 15: 8 X
Value 5
Tabl e 81. Fl ex i bl e Fi l t er Mask Tabl e FFMT PHY Addr ess 01, Page 800, Regi st er s 768 +
n ( n= 0127)
RW 0 X
Mask 0
Mask for filt er 0 byt e n ( n= 0, 1127) .
RW 1 X
Mask 1
RW 2 X
Mask 2
RW 3 X
Mask 3
RW 4 X
Mask 4
RW 5 X
Mask 5
RO 15: 6 X Reserved.

86
There are 128 mask ent ries. The flexible filt er mask and t able is used t o st ore t he four
1- bit masks for each of t he first 128 dat a byt es in a packet , one for each flexible filt er.
I f t he mask bit is one, t he corresponding flexible filt er compares t he incoming dat a byt e
at t he index of t he mask bit t o t he dat a byt e st ored in t he flexible filt er value t able.
Not e: Before writ ing t o t he flexible filt er mask t able t he soft ware device driver must first
All reserved fields read as zeros and are ignored on writ es.
There are four flexible filt ers lengt hs. The flexible filt er lengt h t able st ores t he minimum
packet lengt hs required t o pass each of t he flexible filt ers. Any packet s t hat are short er
t han t he programmed lengt h wont pass t hat filt er. Each flexible filt er considers a
packet t hat doesnt have any mismat ches up t o t hat point t o have passed t he flexible
filt er when it reaches t he required lengt h. I t does not check any byt es past t hat point .
Not e: Before writ ing t o t he flexible filt er lengt h t able t he soft ware device driver must first
Tabl e 82. Fl ex i bl e Fi l t er Lengt h Tabl e FFLT03 PHY Addr ess 01, Page 800, Regi st er s
896 + n ( n= 03)
RW 10: 0 X
LEN
Minimum lengt h for flexible filt er n ( n= 0, 13) .
Tabl e 83. Fl ex i bl e Fi l t er Lengt h Tabl e FFLT45 PHY Addr ess 01, Page 800, Regi st er s
904 + n ( n= 01)
RW 10: 0 X
LEN
Minimum Lengt h for Flexible Filt er n ( n= 0, 1) .
82578 GbE PHYNon- Vol at i l e Memor y ( NVM)
87
9. 0 Non- Vol at i l e Memor y ( NVM)
This sect ion is int ended for designs using a 10/ 100/ 1000 Mb/ s MAC t hat is int egrat ed
int o an I nt el
5 Series Express Chipset in conj unct ion wit h an t he 82578 Physical Layer
Transceiver ( PHY) .
There are several LAN client s t hat might access t he NVM such as hardware, LAN driver,
and BI OS. Refer t o t he I nt el
5 Series Express Chipset Family Ext ernal Design

Specificat ion ( I nt el
5 Series Express Chipset EDS) and t he I nt el
5 Series Express
Chipset SPI Programming Guide for more det ails.
Unless ot herwise specified, all numbers in t his sect ion use t he following numbering
convent ion:
Numbers t hat do not have a suffix are decimal ( base 10) .
Numbers wit h a prefix of 0x are hexadecimal ( base 16) .
Numbers wit h a suffix of b are binary ( base 2) .
9.2 NVM Pr ogr ammi ng Pr ocedur e Over vi ew
The LAN NVM shares space on an SPI Flash device ( or devices) along wit h t he BI OS,
Manageabilit y Firmware, and a Flash Descript or Region. I t is programmed t hrough t he
I nt el
5 Series Express Chipset . This combined image is shown in Figure 10. The Flash
Descript or Region is used t o define vendor specific informat ion and t he locat ion,
allocat ed space, and read and writ e permissions for each region. The Manageabilit y
( ME) Region cont ains t he code and configurat ion dat a for ME funct ions such as I nt el

Act ive Management Technology. The syst em BI OS is cont ained in t he BI OS Region. The
ME Region and BI OS Region are beyond t he scope of t his document and a more
det ailed explanat ion of t hese areas can be found in t he I nt el

Family Ext ernal Design Specificat ion ( I nt el
5 Series Express Chipset EDS) . This

document describes t he LAN image cont ained in t he Gigabit Et hernet ( GbE) region.
88
Non- Vol at i l e Memor y ( NVM) 82578 GbE PHY
Fi gur e 10. LAN NVM Regi ons
To access t he NVM, it is essent ial t o correct ly set up t he following:
1. A valid Flash Descript or Region must be present . Det ails for t he Flash Descript or
Region are cont ained in t he I nt el
5 Series Express Chipset EDS. This process is

described in det ail in t he I nt el
Act ive Management Technology OEM Bring- Up

Guide.
The I nt el
Act ive Management Technology OEM Bring- Up Guide can be obt ained by
cont act ing your local I nt el represent at ive.
2. The GbE region must be part of t he original image flashed ont o t he part .
3. For I nt el LAN t ools and drivers t o work correct ly, t he BI OS must set t he VSCC
regist er( s) correct ly. There are t wo set s of VSCC regist ers, t he upper ( UVSCC) and
lower ( LVSCC) . Not e t hat t he LVSCC regist er is only used if t he NVM at t ribut es
change. For example, t he use of a second flash component , a change in erase size
bet ween segment s, et c. Due t o t he archit ect ure of t he I nt el
5 Series Express
Chipset , if t hese regist ers are not set correct ly, t he LAN t ools might not report an
error message even t hough t he NVM cont ent s remain unchanged. Refer t o t he
I nt el
5 Series Express Chipset EDS for more informat ion

Flash Descriptor
Region 0
GbE
Region 3
BIOS
Region 1
ME
Region 2
89
4. The GbE region of t he NVM must be accessible. To keep t his region accessible, t he
Prot ect ed Range regist er of t he GbE LAN Memory Mapped Configurat ion regist ers
must be set t o t heir default value of 0x0000 0000. ( The GbE Prot ect ed Range
regist ers are described in t he I nt el
5 Series Express Chipset EDS) .

5. The sect or size of t he NVM must equal 256 byt es, 4 KB, or 64 KB. When a Flash
device t hat uses a 64 KB sect or erase is used, t he GbE region size must equal
128 KB. I f t he Flash part uses a 4 KB or 256- byt e sect or erase, t hen t he GbE region
size must be set t o 8 KB.
The NVM image cont ains bot h st at ic and dynamic dat a. The st at ic dat a is t he basic
plat form configurat ion, and includes OEM specific configurat ion bit s as well as t he
unique Print ed Circuit Board Assembly ( PBA) . The dynamic dat a holds t he product s
Et hernet I ndividual Address ( I A) and Checksum. This file can be creat ed using a t ext
edit or.
9.3 LAN NVM For mat and Cont ent s
Table 11 list s t he NVM maps for t he LAN region. Each word list ed is described in det ail
in t he following sect ions.
Tabl e 11. LAN NVM Addr ess Map
LAN
Wor d
Of f set
NVM
By t e
Of f set
Used
By
15 0
I mage
Val ue
0x00 0x00 HW- Shared Et hernet Address Byt e 2, 1 I A ( 2, 1)
0x03 0x06 SW Reserved 0x0800
0x04 0x08 SW Reserved 0xFFFF
0x05 0x0A SW I mage Version I nformat ion 1
0x06 0x0C SW Reserved 0xFFFF
0x07 0x0E SW Reserved 0xFFFF
0x08 0x10 SW PBA Low
0x09 0x12 SW PBA High
0x0A 0x14 HW- PCI PCI I nit Cont rol Word
0x0B 0x16 HW- PCI Subsyst em I D
0x0C 0x18 HW- PCI Subsyst em Vendor I D
0x0D 0x1A HW- PCI Device I D 0x10EF
0x0E 0x1C HW- PCI Reserved
0x0F 0x1E HW- PCI Reserved
0x10 0x20 HW- PCI LAN Power Consumpt ion
0x11 0x22 HW Reserved
0x12 0x24 Reserved
0x13 0x26 HW- Shared Shared I nit Cont rol Word
0x14 0x28 HW- Shared Ext ended Configurat ion Word 1
0x15 0x2A HW- Shared Ext ended Configurat ion Word 2
0x16 0x2C HW- Shared Ext ended Configurat ion Word 3
0x17 0x2E HW- Shared OEM Configurat ion Default s
90
Table not es:
SW = Soft ware: This is access from t he net work configurat ion t ools and drivers.
PXE = PXE Boot Agent : This is access from t he PXE opt ion ROM code in BI OS.
HW- Shared = Hardware - Shared: This is read when t he shared configurat ion is
reset .
HW- PCI = Hardware - PCI : This is read when t he PCI Configurat ion is reset .
9.3.1 Har dw ar e Accessed Wor ds
This sect ion describes t he NVM words t hat are loaded by t he MAC hardware.
9.3.1.1 Et her net Addr ess ( Wor ds 0x 00- 0x 02)
The Et hernet I ndividual Address ( I A) is a 6- byt e field t hat must be unique for each
Net work I nt erface Card ( NI C) or LAN on Mot herboard ( LOM) , and t hus unique for each
copy of t he NVM image. The first t hree byt es are vendor specific - for example, t he I A
is equal t o [ 00 AA 00] or [ 00 A0 C9] for I nt el product s. The value from t his field is
loaded int o t he Receive Address Regist er 0 ( RAL0/ RAH0) .
For t he purpose of t his sect ion, t he I A byt e numbering convent ion is indicat ed as
follows; byt e 1, bit 0 is first on t he wire and byt e 6, bit 7 is last . Not e t hat byt e 1, bit 0
is t he unicast / mult icast address indicat ion while zero means unicast address. Byt e 1,
bit 1 ident ifies t he global/ local indicat ion while zero means a global address.
0x18 0x30 HW- Shared LED 0 - 2
0x19: 0x2F 0x32: 0x5E HW- Shared Reserved 0x0000
LAN
Wor d
Of f set
NVM
By t e
Of f set
Used
By
15 0
I mage
Val ue
0x30: 0x3E 0x60: 0x7C PXE PXE Soft ware Region
0x3F 0x7E SW
Soft ware Checksum ( Byt es 0x00 t hrough
0x7D)
0x40: 0x4A 0x80: 0x94 HW G3 - > S5 LCD Configurat ion
I A By t e/ Val ue
Vendor 1 2 3 4 5 6
I nt el Original 00 AA 00 variable variable variable
I nt el New 00 A0 C9 variable variable variable
91
9. 3. 1. 2 PCI I ni t Cont r ol Wor d ( Wor d 0x 0A)
This word cont ains init ializat ion values t hat :
Set s default s for some int ernal regist ers
Enables/ disables specific feat ures
Det ermines which PCI configurat ion space values are loaded from t he NVM
9.3.1. 3 Subsy st em I D ( Wor d 0x 0B)
I f t he Load Subsyst em I D in word 0x0A is set , t his word is read in t o init ialize t he
Subsyst em I D. Default value is 0x0000.
9. 3.1. 4 Subsy st em Vendor I D ( Wor d 0x 0C)
I f t he Load Subsyst em I D in word 0x0A is set , t his word is read in t o init ialize t he
Subsyst em Vendor I D. Default value is 0x8086.
9. 3.1. 5 Dev i ce I D ( Wor d 0x 0D)
I f t he Load Device I D in word 0x0A is set , t his word is read in t o init ialize t he Device I D
of t he 82578 PHY. Default value is 0x10EF.
9. 3.1. 6 Reser v ed Wor ds 0x 0E and 0x 0F
Bi t Name Def aul t Descr i pt i on
15: 13 Reserved 000b This field is reserved and must be set t o 000b.
12 Reserved 1b Reserved, must be set t o 1b.
11: 8 Reserved 0000b These bit s are reserved and must be set t o 0000b.
7 AUX PWR 1b
Auxiliary Power I ndicat ion
I f set and if PM Ena is set , D3cold wakeup is advert ised in t he I nt el

5 Series Express Chipset of t he PCI funct ion.
0b = No AUX power.
1b = AUX power.
6 PM Enable 1b
Power Management Enable ( PME-WoL)
Enables assert ing PME in t he PCI funct ion at any power st at e. This
bit affect s t he advert ised PME_Support indicat ion in t he I nt el
5
Series Express Chipset of t he PCI funct ion.
0b = Disable.
1b = Enable.
5: 3 Reserved 0x0 These bit s are reserved and must be set t o 0x0.
2 Reserved 0b Reserved, set t o 0b.
1
Load
Subsyst em
I Ds
1b
Load Subsyst em I Ds from NVM
When set t o 1b, indicat es t hat t he device is t o load it s PCI
Subsyst em I D and Subsyst em Vendor I D from t he NVM ( words 0Bh
and 0Ch) .
0
Load Device
I Ds
1b
Load Device I D from NVM
When set t o 1b, indicat es t hat t he device is t o load it s PCI Device I D
from t he NVM ( word 0Dh) .
92
9.3. 1.7 LAN Pow er Consumpt i on ( Wor d 0x 10)
This word is meaningful only if t he power management is enabled.
9.3. 1.8 Reser v ed ( Wor d 0x 11)
9.3. 1.9 Reser v ed ( Wor d 0x 12)
9.3.1.10 Shar ed I ni t Cont r ol Wor d ( Wor d 0x 13)
This word cont rols general init ializat ion values.
Bi t s Name Def aul t Descr i pt i on
15: 8 LAN D0 Power 00001000b
The value in t his field is reflect ed in t he PCI Power Management
Dat a regist er for D0 power consumpt ion and dissipat ion
( Dat a_Select = 0 or 4) . Power is defined in 100 mW unit s. The
power also includes t he ext ernal logic required for t he LAN
funct ion.
7: 5 Reserved 000b Reserved, set t o 000b.
4: 0 LAN D3 Power 0x1
The value in t his field is reflect ed in t he PCI Power Management
Dat a regist er for D3 power consumpt ion and dissipat ion
( Dat a_Select = 3 or 7) . Power is defined in 100 mW unit s. The
power also includes t he ext ernal logic required for t he LAN
funct ion. The most significant bit s in t he Dat a regist er t hat reflect s
t he power values are padded wit h zeros.
15: 0 Reserved 0x0000 Reserved, set t o 0x0000.
15: 14 Sign 10b
Valid I ndicat ion
A 2- bit valid indicat ion field indicat es t o t he device t hat t here is a
valid NVM present . I f t he valid field does not equal 10b t he MAC
does not read t he rest of t he NVM dat a and default values are used
for t he device configurat ion.
9 PHY PD Ena 0b
Enable PHY Power Down
When set , enables PHY power down at DMoff/ D3 or Dr and no
WoL. This bit is loaded t o t he PHY Power Down Enable bit in t he
Ext ended Device Cont rol ( CTRL_EXT) regist er.
1b = Enable PHY power down.
0b = PHY always powered up.
8 Reserved 1b Reserved, should be set t o 1b.
93
7: 6 PHYT 00b
PHY Device Type
I ndicat es t hat t he PHY is connect ed t o t he MAC and result ed mode
of operat ion of t he MAC/ PHY link buses.
00b = 82578.
01b = Reserved.
10b = Reserved.
11b = Reserved.
5 Reserved 01 Reserved, should be set t o 1b.
4 FRCSPD 0b
Default set t ing for t he Force Speed bit in t he Device Cont rol
regist er ( CTRL[ 11] ) .
3 FD 0b
Default set t ing for t he Full Duplex bit in t he Device Cont rol regist er
( CTRL[ 0] ) . The hardware default value is 1b.
1 CLK_CNT_1_4 0b
When set , aut omat ically reduces DMA frequency. Mapped t o t he
Device St at us regist er ( STATUS[ 31] ) .
0
Dynamic Clock
gat ing
1b
When set , enables dynamic clock gat ing of t he DMA and MAC
unit s. This bit is loaded t o t he DynCK bit in t he CTRL_EXT regist er.
94
9.3.1.11 Ex t ended Conf i gur at i on Wor d 1 ( Wor d 0x 14)
13
LCD Writ e
Enable
0b
When set , enables loading of t he ext ended LAN connect ed device
configurat ion area in t he 82578. This configurat ion area also
includes t he PHY t uning ( t uning for I EEE) in t he NVM. Since t his bit
is set t o 0b by default , PHY t uning does not t ake effect unt il t he LAN
driver and/ or firmware loads. When disabled, t he ext ended LAN
connect ed device configurat ion area is ignored. Loaded t o t he
EXTCNF_CTRL regist er.
12
OEM Writ e
Enable
0b
When set , enables aut o load of t he OEM bit s from t he PHY_CTRL
regist er t o t he PHY. OEM bit s include any LED configurat ion. Since
t his bit is set t o 0b by default , t he aut o- load of OEM bit s do not t ake
effect unt il t he LAN driver and/ or firmware loads. Loaded t o t he
Ext ended Configurat ion Cont rol regist er ( EXTCNF_CTRL[ 3] ) .
1b = OEM bit s writ t en t o t he 82578.
0b = No OEM bit s configurat ion.
11: 0
Ext ended
Configurat ion
Point er
0x208
Defines t he base address ( in Dwords) of t he Ext ended Configurat ion
area in t he NVM. The base address defines an offset value relat ive
t o t he beginning of t he LAN space in t he NVM. A value of 0x00 is not
support ed when operat ing wit h t he 82578. Loaded t o t he Ext ended
Configurat ion Cont rol regist er ( EXTCNF_CTRL[ 27: 16] ) .
15: 8
Ext ended PHY
Lengt h
0x00
Size ( in Dwords) of t he Ext ended PHY configurat ion area loaded t o
t he Ext ended Configurat ion Size regist er ( EXTCNF_SI ZE[ 23: 16] ) . I f
an ext ended configurat ion area is disabled by bit 13 in word 0x14,
it s lengt h must be set t o zero.
7: 0 Reserved 0x00 Reserved, must be set t o 0x00.
95
9. 3.1. 14 OEM Conf i gur at i on Def aul t s ( Wor d 0x 17)
This word defines t he OEM fields for t he PHY power management paramet ers loaded t o
t he PHY Cont rol ( PHY_CTRL) regist er.
14 GbE Disable 0b
When set , GbE operat ion is disabled in all power st at es ( including
D0a) .
11
GbE Disable in
non- D0a
1b
Disables GbE operat ion in non- D0a st at es. This bit must be set if GbE
Disable ( bit 14) is set .
10
LPLU Enable in
non- D0a
1b
Low Power Link Up
Enables a decrease in link speed in non- D0a st at es when power
policy and power management st at es dict at e so. This bit must be set
if LPLU Enable in D0a bit is set .
9
LPLU Enable in
D0a
0b
Low Power Link Up
Enables a decrease in link speed in all power st at es.
7: 0 Reserved 0x0 Reserved.
96
9.3. 1.15 LED 0 - 2 Conf i gur at i on Def aul t s ( Wor d 0x 18)
This NVM word specifies t he hardware default s for t he LED Cont rol ( LEDCTL) regist er
fields cont rolling t he LED1 ( LI NK_1000) , LED0 ( LI NK/ ACTI VI TY) and LED2 ( LI NK_100)
out put behaviors. Refer t o t he I nt el
5 Series Family PDG and t he 82578 Reference

Schemat ics for LED connect ion det ails. Also, Table 12 list s mode encodings for LED
out put s.
Not e: Due t o t he archit ect ure of t he 82578 t he cust omized LEDs set t ings are writ t en t o t he
82578 by t he LAN driver. As a result , t he default LEDs are writ t en during t he boot
process and when resuming from power st at es S3, S4, and S5 t o normal operat ion unt il
t he LAN driver writ es any cust om set t ings. This same behavior is also observed while in
S3 and t oggling from ac power ( wall out let ) t o dc power ( bat t ery) . Once t he LAN driver
loads aft er a syst em boot or when resuming from sleep st at es, t he LEDs funct ion as
defined in Word 0x18 of t he GbE region of t he NVM.
15 Blink Rat e 0b
Blink Rat e
0b = Blink at 200 ms on and 200 ms off.
1b = Blink at 83 ms on and 83 ms off.
14 LED2 Blink 0b
I nit ial Value of LED2_BLI NK Field
0b = Non- blinking.
1b = Blinking.
13 LED2 I nvert 0b
I nit ial Value of LED2_I VRT Field
0b = Act ive- low out put .
12: 10 LED2 Mode 110b
LED2 Mode
Specifies what event / st at e/ pat t ern is displayed on t he LED2 out put .
0110b = 100 Mb/ s link_up.
9 LED1 Blink 0b
0b = Non- blinking.
1b = Blinking.
8 LED1 I nvert 0b
7: 5 LED1 Mode 111b
LED1 Mode
0111b = 1000 Mb/ s link_up.
4 LED0 Blink 1b
0b = Non- blinking.
1b = Blinking.
3 LED0 I nvert 0b
2: 0 LED0 Mode 100b
LED0 Mode
100b = Filt er act ivit y on.
97
Tabl e 12. Mode Encodi ngs f or LED Out put s
9. 3.1. 16 Reser v ed ( Wor d 0x 19)
9. 3.1. 17 Reser v ed ( Wor d 0x 1A)
Mode Mnemoni c St at e / Ev ent I ndi cat ed
000b LI NK_10/ 1000
Assert ed when eit her 10 or 1000 Mb/ s link is
est ablished and maint ained.
001b LI NK_100/ 1000
Assert ed when eit her 100 or 1000 Mb/ s link is
est ablished and maint ained.
010b LI NK_UP
Assert ed when any speed link is est ablished and
maint ained.
011b ACTI VI TY
Assert ed when link is est ablished and packet s are
being t ransmit t ed or received.
100b LI NK/ ACTI VI TY
Assert ed when link is est ablished and when t here is
no t ransmit or receive act ivit y.
101b LI NK_10
Assert ed when a 10 Mb/ s link is est ablished and
maint ained.
110b LI NK_100
maint ained.
111b LI NK_1000
maint ained.
6
I nvalid image
CSUM
0b
When cleared t his bit indicat es t o t he NVM programming t ools
( EEUPDATE and LANConf ) t hat t he image checksum needs t o be
correct ed. When set , t he checksum is assumed t o be correct .
0 APM Enable 1b
APM Enable
I nit ial value of Advanced Power Management Wake Up Enable in t he
Wake Up Cont rol ( WUC. APME) regist er.
1b = Advanced power management enabled.
0b = Advanced power management disabled.
98
9.3. 1.18 Reser v ed ( Wor d 0x 1B)
9.3. 1.19 Reser v ed ( Wor d 0x 1C)
9.3. 1.20 Reser v ed ( Wor ds 0x 1D, 0x 1E, 0x 1F, and 0x 20)
9.3. 1.21 Reser v ed ( Wor d 0x 21)
9.3. 1.22 Reser v ed ( Wor d 0x 22)
9.3. 1.23 Reser v ed ( Wor d 0x 23)
4
K1_PLL_
st op_en
0b Enable PLL st op in K1.
3 K0s_100_En 0b Enables K0s mode when PHY link speed is 10/ 100 Mb/ s.
2 K0s_GbE_En 0b Enables K0s mode when PHY link speed is 1000 Mb/ s.
0 K1_En 0b When set t o 1b enables K1 low power mode.
15: 0 Reserved 0x10EF Reserved
15: 0 Reserved 0xBAAD Reserved
99
9. 3.1. 24 Reser v ed ( Wor d 0x 24)
9. 3.1. 25 Reser v ed ( Wor d 0x 25)
9. 3.1. 26 Reser v ed ( Wor d 0x 26)
9. 3.1. 27 Reser v ed ( Wor d 0x 27)
9.3.2 Sof t w ar e Accessed Wor ds
9.3.2. 1 PXE Wor ds ( Wor ds 0x 30 Thr ough 0x 3E)
Words 0x30 t hrough 0x3E ( byt es 0x60 t hrough 0x7D) have been reserved for
configurat ion and version values t o be used by PXE code.
15 Reserved 0b Reserved
13: 12 Reserved 00b Reserved
8: 0 Reserved 0x00 Reserved
15: 0 Reserved 0x00 Reserved
100
9.3.2.1.1 Boot Agent Mai n Set up Opt i ons ( Wor d 0x 30)
The boot agent soft ware configurat ion is cont rolled by t he NVM wit h t he main set up
opt ions st ored in word 0x30. These opt ions are t hose t hat can be changed by using t he
Cont rol- S set up menu or by using t he I BA I nt el Boot Agent ut ilit y. Not e t hat t hese
set t ings only apply t o Boot Agent soft ware.
Tabl e 13. Boot Agent Mai n Set up Opt i ons
Bi t Name Descr i pt i on
15: 14 Reserved Reserved, set t o 00b.
13 Reserved Reserved, must be set t o 0b.
12 FDP
Force Full Duplex.
Set t his bit t o 0b for half duplex and 1b for full duplex.
Not e t hat t his bit is a dont care unless bit s 10 and 11 are set .
11: 10 FSP
Force Speed.
These bit s det ermine speed.
01b = 10 Mb/ s.
10b = 100 Mb/ s.
11b = Not allowed.
All zeros indicat e aut o- negot iat e ( t he current bit st at e) .
Not e t hat bit 12 is a dont care unless t hese bit s are set .
9 Reserved
Reserved
Set t his bit t o 0b.
8 DSM
Display Set up Message.
I f t his bit is set t o 1b, t he "Press Cont rol- S" message appears aft er t he
t it le message.
The default for t his bit is 1b.
7: 6 PT
Prompt Time. These bit s cont rol how long t he "Press Cont rol- S" set up
prompt message appears, if enabled by DI M.
00b = 2 seconds ( default ) .
01b = 3 seconds.
10b = 5 seconds.
11b = 0 seconds.
Not e t hat t he Ct rl- S message does not appear if 0 seconds prompt t ime
is select ed.
5 Reserved Reserved
4: 3 DBS
Default Boot Select ion. These bit s select which device is t he default
boot device. These bit s are only used if t he agent det ect s t hat t he BI OS
does not support boot order select ion or if t he MODE field of word 0x31
is set t o MODE_LEGACY.
00b = Net work boot , t hen local boot .
01b = Local boot , t hen net work boot .
10b = Net work boot only.
11b = Local boot only.
2 Reserved Reserved
1: 0 PS
Prot ocol Select . These bit s select t he boot prot ocol.
00b = PXE ( default value) .
01b = Reserved.
Ot her values are undefined.
101
9.3.2. 1.2 Boot Agent Conf i gur at i on Cust omi zat i on Opt i ons ( Wor d 0x 31)
Word 0x31 cont ains set t ings t hat can be programmed by an OEM or net work
administ rat or t o cust omize t he operat ion of t he soft ware. These set t ings cannot be
changed from wit hin t he Cont rol- S set up menu or t he I BA I nt el Boot Agent ut ilit y. The
lower byt e cont ains set t ings t hat would t ypically be configured by a net work
administ rat or using t he I nt el Boot Agent ut ilit y; t hese set t ings generally cont rol which
set up menu opt ions are changeable. The upper byt e are generally set t ings t hat would
be used by an OEM t o cont rol t he operat ion of t he agent in a LOM environment ,
alt hough t here is not hing in t he agent t o prevent t heir use on a NI C implement at ion.
Tabl e 14. Boot Agent Conf i gur at i on Cust omi zat i on Opt i ons ( Wor d 0x 31)
15: 14 SI G
Signat ure
Set t hese bit s t o 11b t o indicat e valid dat a.
13: 12 Reserved Reserved, must be set t o 00b.
11 Cont inuous Ret ry Disabled ( 0b default ) .
10: 8 MODE
Select s t he agent ' s boot order set up mode. This field changes t he
agent ' s default behavior in order t o make it compat ible wit h syst ems
t hat do not complet ely support t he BBS and PnP Expansion ROM
st andards. Valid values and t heir meanings are:
000b = Normal behavior. The agent at t empt s t o det ect BBS and PnP
Expansion ROM support as it normally does.
001b = Force Legacy mode. The agent does not at t empt t o det ect BBS
or PnP Expansion ROM support s in t he BI OS and assumes t he BI OS is
not compliant . The BI OS boot order can be changed in t he Set up Menu.
010b = Force BBS mode. The agent assumes t he BI OS is BBS-
compliant , even t hough it might not be det ect ed as such by t he agent ' s
det ect ion code. The BI OS boot order CANNOT be changed in t he Set up
Menu.
011b = Force PnP I nt 18 mode. The agent assumes t he BI OS allows
boot order set up for PnP Expansion ROMs and hooks int errupt 18h ( t o
inform t he BI OS t hat t he agent is a boot able device) in addit ion t o
regist ering as a BBS I PL device. The BI OS boot order CANNOT be
changed in t he Set up Menu.
100b = Force PnP I nt 19 mode. The agent assumes t he BI OS allows
boot order set up for PnP Expansion ROMs and hooks int errupt 0x19 ( t o
inform t he BI OS t hat t he agent is a boot able device) in addit ion t o
regist ering as a BBS I PL device. The BI OS boot order CANNOT be
changed in t he Set up Menu.
101b = Reserved for fut ure use. I f specified, t reat ed as value 000b.
7: 6 Reserved Reserved, must be set t o 00b.
5 DFU
Disable Flash Updat e
I f set t o 1b, no updat es t o t he Flash image using PROSet is allowed.
The default for t his bit is 0b; allow Flash image updat es using PROSet .
4 DLWS
Disable Legacy Wakeup Support
I f set t o 1b, no changes t o t he Legacy OS Wakeup Support menu
opt ion is allowed.
The default for t his bit is 0b; allow Legacy OS Wakeup Support menu
opt ion changes.
3 DBS
Disable Boot Select ion
I f set t o 1b, no changes t o t he boot order menu opt ion is allowed.
The default for t his bit is 0b; allow boot order menu opt ion changes.
102
2 DPS
Disable Prot ocol Select
I f set t o 1b, no changes t o t he boot prot ocol is allowed.
The default for t his bit is 0b; allow changes t o t he boot prot ocol.
1 DTM
Disable Tit le Message
I f set t o 1b, t he t it le message displaying t he version of t he boot agent
is suppressed; t he Cont rol- S message is also suppressed. This is for
OEMs who do not want t he boot agent t o display any messages at
syst em boot .
The default for t his bit is 0b; allow t he t it le message t hat displays t he
version of t he boot agent and t he Cont rol- S message.
0 DSM
Disable Set up Menu
I f set t o 1b, no invoking t he set up menu by pressing Cont rol- S is
allowed. I n t his case, t he EEPROM can only be changed via an ext ernal
program.
The default for t his bit is 0b; allow invoking t he set up menu by
pressing Cont rol- S.
103
9.3.2. 1.3 Boot Agent Conf i gur at i on Cust omi zat i on Opt i ons ( Wor d 0x 32)
Word 0x32 is used t o st ore t he version of t he boot agent t hat is st ored in t he Flash
image. When t he Boot Agent loads, it can check t his value t o det ermine if any first - t ime
configurat ion needs t o be performed. The agent t hen updat es t his word wit h it s
version. Some diagnost ic t ools t o report t he version of t he Boot Agent in t he Flash also
read t his word. This word is only valid if t he PPB is set t o 0b. Ot herwise t he cont ent s
might be undefined.
Tabl e 15. Boot Agent Conf i gur at i on Cust omi zat i on Opt i ons ( Wor d 0x 32)
9.3.2. 1.4 I BA Capabi l i t i es ( Wor d 0x 33)
Word 0x33 is used t o enumerat e t he boot t echnologies t hat have been programmed
int o t he Flash. I t is updat ed by I BA configurat ion t ools and is not updat ed or read by
I BA.
15: 12 MAJOR PXE boot agent maj or version. The default for t hese bit s is 0x1.
11: 8 MI NOR PXE boot agent minor version. The default for t hese bit s is 0x2
7: 0 BUI LD PXE boot agent build number. The default for t hese bit s is 0x28.
104
Tabl e 16. I BA Capabi l i t i es
9.3.2.2 Check sum Wor d Cal cul at i on ( Wor d 0x 3F)
The Checksum word ( Word 0x3F, NVM byt es 0x7E and 0x7F) is used t o ensure t hat t he
base NVM image is a valid image. The value of t his word should be calculat ed such t hat
aft er adding all t he words ( 0x00- 0x3F) / byt es ( 0x00- 0x7F) , including t he Checksum
word it self, t he sum should be 0xBABA. The init ial value in t he 16 bit summing regist er
should be 0x0000 and t he carry bit should be ignored aft er each addit ion.
Not e: Hardware does not calculat e t he word 0x3F checksum during NVM writ e; it must be
calculat ed by soft ware independent ly and included in t he NVM writ e dat a. Hardware
does not comput e a checksum over words 0x00- 0x3F during NVM reads in order t o
det ermine validit y of t he NVM image; t his field is provided st rict ly for soft ware
verificat ion of NVM validit y. All hardware configurat ion based on word 0x00- 0x3F
cont ent is based on t he validit y of t he Signat ure field of t he NVM.
9.3.3 Basi c Conf i gur at i on Sof t w ar e Wor ds
This sect ion describes t he meaningful NVM words in t he basic configurat ion space t hat
are used by soft ware at word addresses 0x03- 0x09.
9.3. 3.1 Reser v ed ( Wor d 0x 3)
15: 14 SI G
Signat ure
These bit s must be set t o 01b t o indicat e t hat t his word has been
programmed by t he agent or ot her configurat ion soft ware.
13: 5 Reserved Reserved, must be set t o 0x00.
4 iSCSI boot capabilit y not present ( 0b default ) .
3 EFI
EFI EBC capabilit y is present in Flash.
0b = The EFI code is not present ( default ) .
1b = The EFI code is present .
2 Reserved Reserved, set t o 1b.
1 UNDI
PXE/ UNDI capabilit y is present in Flash.
1b = The PXE base code is present ( default ) .
0b = The PXE base code is not present .
0 BC
PXE base code is present in Flash.
0b = The PXE base code is present ( default ) .
1b = The PXE base code is not present .
11 LOM 1b
LOM
Set t o 1b.
105
9.3.3. 2 Reser v ed ( Wor ds 0x 04, 0x 06, and 0x 07)
9. 3.3. 3 I mage Ver si on I nf or mat i on ( Wor d 0x 05)
Not e: This is a reserved word and cannot be changed.
Care should be t aken t o use t he correct GbE NVM firmware revision for t he st epping
combinat ion of t he I nt el
5 Series Express Chipset and t he 82578. The following t able

list s t he NVM revision t hat is opt imized for use wit h t he silicon st epping combinat ion.
Not e: Using a newer revision NVM wit h an older silicon st epping or older revision NVM wit h a
newer silicon st epping could cause syst em inst abilit y and unpredict able behavior.
9. 3.3. 4 PBA Low and PBA Hi gh ( Wor ds 0x 08 and 0x 09)
The nine- digit Print ed Board Assembly ( PBA) number used for I nt el manufact ured
Net work I nt erface Cards ( NI Cs) and Lan on Mot herboard ( LOMs) are st ored in a four-
byt e field. The dash it self is not st ored, neit her is t he first digit of t he 3- digit suffix, as
it is always zero for t he affect ed product s. Not e t hat t hrough t he course of hardware
ECOs, t he suffix field ( byt e 4) is increment ed. The purpose of t his informat ion is t o
allow cust omer support ( or any user) t o ident ify t he exact revision level of a product .
Not e: Net work driver soft ware should not rely on t his field t o ident ify t he product or it s
capabilit ies.
Example: PBA number = 123456- 003 t o Word 0x08 = 0x1234; Word 0x09 = 0x5603.
15: 0 Reserved 0xFFFF Reserved
I nt el
5 Ser i es Ex pr ess
Chi pset St eppi ng
82578 St eppi ng/ PHY- Ver NVM Ver si on
B1 C0 0. 62
Bi t s Wor d Def aul t Descr i pt i on
15: 0 0x08 0xFFFF PBA low.
15: 0 0x09 0xFFFF PBA high.
106
9.4 I nt el
5 Ser i es Ex pr ess Chi pset / 82578 NVM Cont ent s

This sect ion list s t he NVM cont ent s for t he I nt el
5 Series Express Chipset and t he

82578.
Tabl e 17. LAN NVM Cont ent s
Wor d Descr i pt i on
0x00: 0x02 Et hernet I ndividual Address
0x03: 0x04 Reserved
0x05 I mage Version I nformat ion
0x06: 0x07 Reserved
0x08: 0x09 PBA Byt es
0x0A PCI I nit Cont rol Word
0x0B Subsyst em I D
0x0C Subsyst em Vendor I D
0x0D Device I D
0x0E Reserved
0x0F Reserved
0x10 LAN Power Consumpt ion
0x11 Reserved
0x12 Reserved
0x13 Shared I nit Cont rol Word
0x14: 0x16 Ext ended Configurat ion Words
0x17 OEM Configurat ion Default s
0x18 LED 0 - 2
0x19: 0x2F Reserved
0x30: 0x3E PXE Region
0x3F Soft ware Checksum
82578 GbE PHYI nt el
5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

107
10. 0 I nt el
5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng

I nt er f ace
10.1 Regi st er By t e Or der i ng
This sect ion defines t he st ruct ure of regist ers t hat cont ain fields carried over t he
net work. For example, L2, L3, L4 fields.
The following example is used t o describe byt e ordering over t he wire ( hex not at ion) :
Last First
. .., 06, 05, 04, 03, 02, 01, 00
where each byt e is sent wit h t he LS bit first . That is, t he bit order over t he wire for t his
example is:
Last First
. .., 0000 0011, 0000 0010, 0000 0001, 0000 0000
The general rule for regist er ordering is t o use host ordering ( also called lit t le endian) .
Using t he previous example, a 6- byt e fields ( such as a MAC address) is st ored in a CSR
in t he following manner:
The following list ed except ions use net work or dering ( also called big endian) . Using t he
previous example, a 16- bit field ( such as Et herType) is st ored in a CSR in t he following
manner:
Byt e 3 Byt e 2 Byt e 1 Byt e 0
Dword address ( N) 0x03 0x02 0x01 0x00
Dword address ( N + 4) . . . . . . 0x05 0x04
Dword aligned
or
Word aligned
. . . . . . 0x00 0x01
DW address ( N + 4) 0x00 0x01 . .. . . .
108
I nt el
5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace82578 GbE PHY
The following except ions use net work ordering:
All ETherType fields
The normal not at ion as it appears in t ext books, et c. is t o use net work ordering. For
example, t he following MAC address: 00-A0- C9- 00- 00- 00. The order on t he net work is
00, t hen A0, t hen C9, et c. However, t he host ordering present at ion would be:
10.2 Regi st er Convent i ons
All regist ers in t he MAC are defined t o be 32 bit s, so writ e cycles should be accessed as
32 bit double- words, There are some except ions t o t his rule:
Regist er pairs where t wo 32- bit regist ers make up a larger logical size
Reserved bit posit ions: Some regist ers cont ain cert ain bit s t hat are marked as
reserved. These bit s should never be set t o a value of 1b by soft ware. Reads from
regist ers cont aining reserved bit s might ret urn indet erminat e values in t he reserved bit
posit ions unless read values are explicit ly st at ed. When read, t hese reserved bit s
should be ignored by soft ware.
Reserved and/ or undefined addresses: any regist er address not explicit ly declared in
t his document should be considered t o be reserved, and should not be writ t en t o.
Writ ing t o reserved or undefined regist er addresses might cause indet erminat e
behavior. Reads from reserved or undefined configurat ion regist er addresses might
ret urn indet erminat e values unless read values are explicit ly st at ed for specific
addresses. Reserved fields wit hin defined regist ers are defined as Read- Only ( RO) .
When writ ing t o t hese regist ers, t he RO fields should be set t o t heir init ial value.
Reading from reserved fields might ret urn indet erminat e values.
I nit ial values: most regist ers define t he init ial hardware values prior t o being
programmed. I n some cases, hardware init ial values are undefined and are list ed as
such via t he t ext undefined, unknown, or X. Some of t hese configurat ion values might
need t o be set via NVM configurat ion or via soft ware in order for proper operat ion t o
occur. Not e t hat t his need is dependent on t he funct ion of t he bit . Ot her regist ers might
cit e a hardware default t hat is overridden by a higher- precedence operat ion.
Operat ions t hat might supersede hardware default s might also include a valid NVM
load, complet ion of a hardware operat ion ( such as hardware aut o- negot iat ion) , or
writ ing of a different regist er whose value is t hen reflect ed in anot her bit .
For regist ers t hat should be accessed as 32- bit double words, part ial writ es ( less t han a
32- bit double word) does not t ake effect ( t he writ e is ignored) . Part ial reads ret urn all
32 bit s of dat a regardless of t he byt e enables.
Not e: Part ial reads t o read- on- clear regist ers ( such as I CR) can have unexpect ed result s since
all 32 bit s are act ually read regardless of t he byt e enables. Part ial reads should not be
done.
Not e: All st at ist ics regist ers are implement ed as 32- bit regist ers. Though some logical
st at ist ics regist ers represent count ers in excess of 32 bit s in widt h, regist ers must be
accessed using 32- bit operat ions ( like independent access t o each 32- bit field) .
Dword address ( N) 00 C9 A0 00
Dword address ( N + 4) . .. ... 00 00

109
10.2. 1 PCI Conf i gur at i on and St at us Regi st er s - CSR Space
All configurat ion regist ers are list ed in Table 18. These regist ers are ordered by
grouping and are not necessarily list ed in order t hat t hey appear in t he address space.
Regist er based legend:
RW - Read writ e regist er.
RO - Read only regist er.
RO/ CR - Read only regist er, clear on read.
RO/ V - Read only regist er, read st at us is not const ant
RW/ RO - Read writ e by firmware; read only by soft ware.
RWC - Read writ e clear regist ers. Writ ing 0b has no affect . Writ ing 1b clears t he
appropriat e fields ( see det ailed descript ion of t he specific regist ers) .
RW/ V Read writ e regist er. This bit self- clears immediat ely.
RW/ SN Read writ e regist er init ial value loaded from NVM.
RC/ WC - Read writ e clear regist ers. Writ ing 0b has no affect . Writ ing 1b clears t he
appropriat e fields. Not e t hat a read might also clear t he regist er depending on
enablement ( see appropriat e regist ers) .
RWC/ CR/ V Read writ e regist er clear on read, clear on writ e.
WO - Writ e only regist ers. Reading from t hese regist ers does not reflect any
meaningful dat a. Generally t his would be all zero' s ( see det ailed descript ion of
appropriat e regist ers) .
Tabl e 18. Regi st er Summar y
Of f set Abbr ev i at i on Name RW Par agr aph
Gener al Regi st er Descr i pt i ons
0x00000 CTRL Device Cont rol Regist er RW 10. 2. 1. 1. 1
0x00008 STATUS Device St at us Regist er RO 10. 2. 1. 1. 2
0x0000C STRAP St rapping Opt ion Regist er RO 10. 2. 1. 1. 3
0x00018 CTRL_EXT Ext ended Device Cont rol Regist er RW 10. 2. 1. 1. 4
0x00020 MDI C MDI Cont rol Regist er RW 10. 2. 1. 1. 5
0x00028 FEXTNVM Fut ure Ext ended NVM Regist er RW 10. 2. 1. 1. 6
0x0002C FEXT Fut ure Ext ended Regist er RW 10. 2. 1. 1. 7
0x00038 BUSNUM Device and Bus Number RO 10. 2. 1. 1. 8
0x00170 FCTTV Flow Cont rol Transmit Timer Value RW 10. 2. 1. 1. 9
0x05F40 FCRTV Flow Cont rol Refresh Threshold Value RW 10. 2. 1. 1. 10
0x00F00 EXTCNF_CTRL Ext ended Configurat ion Cont rol RW 10. 2. 1. 1. 11
0x00F08 EXTCNF_SI ZE Ext ended Configurat ion Size RW 10. 2. 1. 1. 12
0x00F10 PHY_CTRL PHY Cont rol Regist er RW 10. 2. 1. 1. 13
0x00F18 PCI EANACFG PCI E Analog Configurat ion RW 10. 2. 1. 1. 14
0x01000 PBA Packet Buffer Allocat ion RW 10. 2. 1. 1. 15
0x01008 PBS Packet Buffer Size RW 10. 2. 1. 1. 16
0x0100C PBECCSTS Packet Buffer ECC St at us RW 10. 2. 1. 1. 17
0x01004 PBEEI Packet Buffer ECC Error I nj ect RW 10. 2. 1. 1. 18
110
I nt el
I nt er r upt Regi st er Descr i pt i ons
0x000C0 I CR I nt errupt Cause Read Regist er
RC/
WC
10. 2. 1. 2. 1
0x000C4 I TR I nt errupt Throt t ling Regist er RW 10. 2. 1. 2. 2
0x000C8 I CS I nt errupt Cause Set Regist er WO 10. 2. 1. 2. 3
0x000D0 I MS I nt errupt Mask Set / Read Regist er RW 10. 2. 1. 2. 4
0x000D8 I MC I nt errupt Mask Clear Regist er WO 10. 2. 1. 2. 5
0x000E0 Mask - I AM I nt errupt Acknowledge Aut o RW 10. 2. 1. 2. 6
Recei v e Regi st er Descr i pt i ons
0x00100 RCTL Receive Cont rol Regist er RW 10. 2. 1. 3. 1
0x00104 RCTL1 Receive Cont rol Regist er 1 RW 10. 2. 1. 3. 2
0x02008 ERT Early Receive Threshold RW 10. 2. 1. 3. 3
0x02170 PSRCTL Packet Split Receive Cont rol Regist er RW 10. 2. 1. 3. 4
0x02160 FCRTL Flow Cont rol Receive Threshold Low RW 10. 2. 1. 3. 5
0x02168 FCRTH Flow Cont rol Receive Threshold High RW 10. 2. 1. 3. 6
0x02800 RDBAL
Receive Descript or Base Address Low
Queue
RW 10. 2. 1. 3. 7
0x02804 RDBAH
Receive Descript or Base Address High
Queue
RW 10. 2. 1. 3. 8
0x02808 RDLEN Receive Descript or Lengt h Queue RW 10. 2. 1. 3. 9
0x02810 RDH Receive Descript or Head Queue RW 10. 2. 1. 3. 10
0x02818 RDT Receive Descript or Tail Queue RW 10. 2. 1. 3. 11
0x02820 RDTR I nt errupt Delay Timer ( Packet Timer) RW 10. 2. 1. 3. 12
0x02828 RXDCTL Receive Descript or Cont rol RW 10. 2. 1. 3. 13
0x0282C RADV Receive I nt errupt Absolut e Delay Timer RW 10. 2. 1. 3. 14
0x02C00 RSRPD Receive Small Packet Det ect I nt errupt RW 10. 2. 1. 3. 15
0x02C08 RAI D Receive ACK I nt errupt Delay Regist er RW 10. 2. 1. 3. 16
0x05000 RXCSUM Receive Checksum Cont rol RW 10. 2. 1. 3. 17
0x05008 RFCTL Receive Filt er Cont rol Regist er RW 10. 2. 1. 3. 18
0x05200- 0x0527C MTA[ 31: 0] Mult icast Table Array RW 10. 2. 1. 3. 19
0x05400 + 8* n
( n= 06)
RAL Receive Address Low RW 10. 2. 1. 3. 20
0x05404 + 8* n
( n= 06)
RAH Receive Address High RW 10. 2. 1. 3. 21
0x05438 + 8* n
( n= 03)
SRAL Shared Receive Address Low RW 10. 2. 1. 3. 22
0x0543C + 8* n
( n= 02)
SRAH Shared Receive Address High 02 RW 10. 2. 1. 3. 23
0x05454 SHRAH[ 3] Shared Receive Address High 3 RW 10. 2. 1. 3. 24
0x05818 MRQC
Mult iple Receive Queues Command
Regist er
RW 10. 2. 1. 3. 25
0x05C00 + 4* n
( n= 031)
RETA Redirect ion Table RW 10. 2. 1. 3. 26
0x05C80 + 4* n
( n= 09)
RSSRK Random Key Regist er RW 10. 2. 1. 3. 27
Of f set Abbr evi at i on Name RW Par agr aph

111
Not e: Cert ain regist ers maint ain an alias address designed for backward compat ibilit y wit h
soft ware writ t en for t he previous devices. Regist ers t hat have an alias address can be
accessed by soft ware at eit her t he new offset or t he alias offset . I t is recommended
t hat soft ware t hat is writ t en solely for t he I nt el
5 Series Express Chipset and t he

82578 use t he new address offset .
Tr ansmi t Regi st er Descr i pt i ons
0x00400 TCTL Transmit Cont rol Regist er RW 10. 2. 1. 4. 1
0x00410 TI PG Transmit I PG Regist er RW 10. 2. 1. 4. 2
0x00458 AI T Adapt ive I FS Throt t le RW 10. 2. 1. 4. 3
0x03800 TDBAL Transmit Descript or Base Address Low RW 10. 2. 1. 4. 4
0x03804 TDBAH Transmit Descript or Base Address High RW 10. 2. 1. 4. 5
0x03808 TDLEN Transmit Descript or Lengt h RW 10. 2. 1. 4. 6
0x03810 TDH Transmit Descript or Head RW 10. 2. 1. 4. 7
0x03818 TDT Transmit Descript or Tail RW 10. 2. 1. 4. 8
0x03840 TARC Transmit Arbit rat ion Count RW 10. 2. 1. 4. 9
0x03820 TI DV Transmit I nt errupt Delay Value RW 10. 2. 1. 4. 9
0x03828 TXDCTL Transmit Descript or Cont rol RW 10. 2. 1. 4. 10
0x0382C TADV Transmit Absolut e I nt errupt Delay Value RW 10. 2. 1. 4. 11
Management Regi st er Descr i pt i ons
0x05800 WUC Wake Up Cont rol Regist er RW 10. 2. 1. 5. 1
0x05808 WUFC Wake Up Filt er Cont rol Regist er RW 10. 2. 1. 5. 2
0x05810 WUS Wake Up St at us Regist er RW 10. 2. 1. 5. 3
0x5838 I PAV I P Address Valid RW 10. 2. 1. 5. 4
0x05840 + 8* n
( n= 13)
I P4AT I Pv4 Address Table RW 10. 2. 1. 5. 5
0x05880 + 4* n
( n= 03)
I P6AT I Pv6 Address Table RW 10. 2. 1. 5. 6
0x05F00 + 8* n
( n= 035)
FFLT Flexible Filt er Lengt h Table RW 10. 2. 1. 5. 7
0x09000 + 8* n
( n= 0127)
FFMT Flexible Filt er Mask Table RW 10. 2. 1. 5. 8
0x09800 + 8* n
( n= 0127)
FFVT Flexible Filt er Value Table RW 10. 2. 1. 5. 10
0x09804 + 8* n
( n= 0127)
FFVT2 Flexible Filt er Value Table RW 10. 2. 1. 5. 10
Of f set Abbr ev i at i on Name RW Par agr aph
112
I nt el
10. 2. 1. 1 Gener al Regi st er Descr i pt i ons
10.2.1.1.1 Devi ce Cont r ol Regi st er - CTRL ( 0x 00000; RW)
0 RW/ SN 1b
Full Duplex ( FD) .
0b = Half duplex.
1b = Full duplex.
Cont rols t he MAC duplex set t ing when explicit ly set by soft ware. Loaded
from t he NVM word 0x13.
1 RO 0b Reserved. Writ e as 0b for fut ure compat ibilit y
2 RW 0b
Mast er Disable. When set , t he MAC blocks new mast er request s on t he
PCI device. Once no mast er request s are pending by t his funct ion, t he
Mast er Enable St at us bit is cleared.
5: 3 RO 000b Reserved. Writ e as 0b for fut ure compat ibilit y.
6 RO 1b Reserved.
7 RO 0b Reserved. Must be set t o 0b.
9: 8 RW 10b
Speed select ion ( SPEED) . These bit s might det ermine t he speed
configurat ion and are writ t en by soft ware aft er reading t he PHY
configurat ion t hrough t he MDI O int erface. These signals are ignored when
aut o- speed det ect ion is enabled.
0) b = 10 Mb/ s.
0) b = 100 Mb/ s.
10b = 1000 Mb/ s.
11b = Not used.
10 RO 0b Reserved. Writ e as 0b for fut ure compat ibilit y.
11 RW/ SN 0b
Force Speed ( FRCSPD) . This bit is set when soft ware needs t o manually
configure t he MAC speed set t ings according t o t he Speed bit s ( bit s 9: 8) .
When using t he 82578, not e t hat it must resolve t o t he same speed
configurat ion or soft ware must manually set it t o t he same speed as t he
MAC. The value is loaded from word 0x13 in t he NVM.
Not e t hat t his bit is superseded by t he CTRL_EXT. SPD_BYPS bit , which
has a similar funct ion.
12 RW 0b
Force Duplex ( FRCDPLX) . When set t o 1b, soft ware might override t he
duplex indicat ion from t he 82578 t hat is indicat ed in t he FDX t o t he MAC.
Ot herwise, t he duplex set t ing is sampled from t he 82578 FDX indicat ion
int o t he MAC on t he assert ing edge of t he PHY link signal. When assert ed,
t he CTRL. FD bit set s duplex.
13 RO 0b Reserved.
14 RW/ SN 0b Reserved.
15 RO 0b Reserved. Reads as 0.
18: 16 RW 0b0 Reserved.
19 RW 0b
Memory Error Handling Enable ( MEHE) . When set t o 1b, t he I nt el 5
Series Express Chipset react ion t o correct able and uncorrect able memory
errors det ect ion are act ivat ed.
20 1b Reserved.
24: 21 RO 0x0 Reserved.
25 RW 0b Reserved.
26 RW/ V 0b
Host Soft ware Reset ( SWRST) . This bit performs a reset t o t he PCI dat a
pat h and t he relevant shared logic. Writ ing 1b init iat es t he reset . This bit
is self- clearing.
27 RW 0b
Receive Flow Cont rol Enable ( RFCE) . I ndicat es t hat t he MAC responds t o
receiving flow cont rol packet s. I f aut o- negot iat ion is enabled, t his bit is
set t o t he negot iat ed duplex value.

113
Not e: Fields loaded from t he NVM are set by t he NVM only if t he signat ure bit s of t he NVM' s
I nit ializat ion Cont rol Word mat ch 01b.
This regist er, as well as t he Ext ended Device Cont rol regist er ( CTRL_EXT) , cont rols t he
maj or operat ional modes for t he MAC. While soft ware writ es t o t his regist er t o cont rol
MAC set t ings, several bit s ( such as FD and SPEED) might be overridden depending on
ot her bit set t ings and t he result ant link configurat ion is det ermined by t he 82578' s
aut o- negot iat ion resolut ion.
The FD ( duplex) and SPEED configurat ions of t he MAC are normally det ermined from
t he link configurat ion process. Soft ware might specifically override/ set t hese MAC
set t ings via cert ain bit s in a forced- link scenario; if so, t he values used t o configure t he
MAC must be consist ent wit h t he 82578 set t ings.
Manual link configurat ion is cont rolled t hrough t he 82578' s MI I management int erface.
Host Soft ware Reset ( bit 26) , might be used t o globally reset t he ent ire host dat a pat h
and shared logic. This regist er is provided primarily as a last - dit ch soft ware mechanism
t o recover from an indet erminat e or suspect ed hung hardware st at e. Most regist ers
( receive, t ransmit , int errupt , st at ist ics, et c. ) , and st at e machines are set t o t heir
power- on reset values, approximat ing t he st at e following a power- on or PCI reset . One
int ernal configurat ion regist er, t he Packet Buffer Allocat ion ( PBA) regist er, ret ains it s
value t hrough a soft ware reset .
Not e: To ensure t hat t he global device reset has fully complet ed and t hat t he MAC responds
t o subsequent accesses, programmers must wait approximat ely 1 ms aft er set t ing
before at t empt ing t o check t o see if t he bit has cleared or t o access ( read or writ e) any
ot her device regist er.
Not e: This regist er' s address is also reflect ed at address 0x00004 for legacy reasons. Neit her
t he soft ware driver nor firmware should use it since it might be unsupport ed in next
generat ions.
28 RW 0b
Transmit Flow Cont rol Enable ( TFCE) . I ndicat es t hat t he MAC t ransmit s
flow cont rol packet s ( XON and XOFF frames) based on receiver fullness. I f
aut o- negot iat ion is enabled, t his bit is set t o t he negot iat ed duplex value.
29 RO 0b Reserved.
30 RW 0b
VLAN Mode Enable ( VME) . When set t o 1b, all packet s t ransmit t ed from
MAC t hat have VLE set is sent wit h an 802. 1Q header added t o t he
packet . The cont ent s of t he header come from t he t ransmit descript or and
from t he VLAN t ype regist er. On receive, VLAN informat ion is st ripped
from 802. 1Q packet s.
31 RW/ V 0b
LAN Connect ed Device Reset ( LCD_RST) . Cont rols an inband message t o
t he 82578.
0b = Normal operat ion
1b = Reset t o PHY is assert ed.
The LCD_RST funct ionalit y is gat ed by t he FWSM. RSPCI PHY bit . I f t he
FWSM. RSPCI PHY bit is not set t o 1b, t hen set t ing t he LCD_RST has no
impact . For proper operat ion, soft ware or firmware must also set t he
SWRST bit in t he regist er at t he same t ime. This bit is self- clearing.
114
I nt el
10.2.1.1.2 Devi ce St at us Regi st er - STATUS ( 0x 00008; RO)
Bi t s At t r i but e Reset Descr i pt i on
0 RO/ V X
Full Duplex ( FD) .
0b = Half duplex.
1b = Full duplex.
Reflect s duplex set t ing of t he MAC and/ or link.
1 RO/ V X
Link up ( LU) .
0b = No link est ablished.
1b = Link est ablished.
For t his t o be valid, t he Set Link Up bit of t he Device Cont rol regist er
( CTRL. SU) must be set .
3: 2 RO/ V 00b
PHY Type I ndicat ion ( PHYTYPE) . I ndicat es t hat t he 82578 at t ached t o t he
MAC and result ed mode of operat ion of t he MAC/ 82578 Link buses.
00 = 82578.
01 = Reserved.
10 = Reserved.
11 = Reserved.
This field is loaded from t he Shared I nit cont rol word in t he NVM.
4 RO/ V X
Transmission Paused ( TXOFF) . I ndicat ion of pause st at e of t he t ransmit
funct ion when symmet rical flow cont rol is enabled.
5 RO/ V 1b
PHY Power Up not ( PHYPWR) . RO bit t hat indicat es t he power st at e of t he
82578.
0b = The 82578 is powered on in t he act ive st at e.
1b = The 82578 is in t he power down st at e.
The PHYPWR bit is valid only aft er PHY reset is assert ed.
Not e: The PHY power up indicat ion reflect s t he st at us of t he LANPHYPC
signaling t o t he 82578.
7: 6 RO/ V X
Link speed set t ing ( SPEED) . This bit reflect s t he speed set t ing of t he MAC
and/ or link.
00b = 10 Mb/ s.
01b = 100 Mb/ s.
10b = 1000 Mb/ s.
11b = 1000 Mb/ s.
8 RO/ V X
Mast er Read Complet ions Blocked. This bit is set when t he MAC receives a
complet ion wit h an error ( EP = one or st at us! = successful) .
I t is cleared on PCI reset .
9 RW/ V/ C 0b
LAN I nit Done. This bit is assert ed following complet ion of t he LAN
init ializat ion from t he Flash.
Soft ware is expect ed t o clear t his field t o make it usable for t he next
init ializat ion done event .
10 RW/ V/ C 1b
PHY Reset Assert ed ( PHYRA) . This bit is R/ W. Hardware set s t his bit
following t he assert ion of a 82578 reset ( eit her hardware or inband) . The
bit is cleared on writ ing 0b t o it .
19 RO/ V 1b
Mast er Enable St at us. Cleared by t he MAC when t he Mast er Disable bit is
set and no mast er request s are pending by t his funct ion, ot herwise t his bit
is set . This bit indicat es t hat no mast er request s are issued by t his
funct ion as long as t he Mast er Disable bit is set .
29: 20 RO 0x0 Reserved. Reads as 0.
30 RO 0b Reserved.
31 RO/ SN 1b
Clock Cont rol ( CLK_CNT_1_4) . This bit is loaded from t he NVM word
0x13 and indicat es t he MAC support s lowering it s DMA clock t o of it s
value.

115
FD reflect s t he act ual MAC duplex configurat ion. This normally reflect s t he duplex
set t ing for t he ent ire link, as it normally reflect s t he duplex configurat ion negot iat ed
bet ween t he PHY and link part ner ( copper link) or MAC and link part ner ( fiber link) .
Link up provides a useful indicat ion of whet her somet hing is at t ached t o t he port .
Successful negot iat ion of feat ures/ link paramet ers result s in link act ivit y. The link
st art up process ( and consequent ly t he durat ion for t his act ivit y aft er reset ) might be
several 100' s of ms. I t reflect s whet her t he PHY' s link indicat ion is present .
TXOFF indicat es t he st at e of t he t ransmit funct ion when symmet rical flow cont rol has
been enabled and negot iat ed wit h t he link part ner. This bit is set t o 1b when
t ransmission is paused due t o t he recept ion of an XOFF frame. I t is cleared upon
expirat ion of t he pause t imer or t he receipt of an XON frame.
SPEED indicat es t he act ual MAC speed configurat ion. These bit s normally reflect t he
speed of t he act ual link, negot iat ed by t he PHY and link part ner, and reflect ed int ernally
from t he PHY t o t he MAC. These bit s might represent t he speed configurat ion of t he
MAC only, if t he MAC speed set t ing has been forced via soft ware ( CTRL. SPEED) . Speed
indicat ions are mapped as shown below:
00b = 10 Mb/ s
01b = 100 Mb/ s
10b = 1000 Mb/ s
11b = 1000 Mb/ s
116
I nt el
10.2.1.1.3 St r appi ng Opt i on Regi st er - STRAP ( 0x 0000C; RO)
This regist er reflect s t he values of t he soft st rapping opt ions fet ched from t he NVM
descript or in t he I nt el
5 Series Express Chipset space. These signals are sampled by

t he MAC following LAN_RST# or global reset ( PCI reset assert ion) .
10.2.1.1.4 Ex t ended Devi ce Cont r ol Regi st er - CTRL_EXT ( 0x 00018; RW)
Bi t ( s) Type Reset Descr i pt i on
0 RO 1b Reserved.
5: 1 RO 0x0
LAN NVM Size ( NVMS) . LAN NVM space size is indicat ed in mult iples of 4
KB. LAN NVM size might very from 4 KB t o 128 KB ( a zero value means 4
KB) .
16 RO 0b MAC SMBus address enable ( LCSMBADDEN) .
23: 17 RO 0x0 MAC SMBus address ( LCSMBADD) .
24 RO 0b PHY SMBus address enable ( LCDSMBADDEN) .
31: 25 RO 0x0 PHY SMBus address ( LCDSMBADD) .
Bi t s Ty pe Reset Descr i pt i on
12 RW/ V 1b Reserved.
14: 13 00b Reserved.
15 RW 0b
Speed Select Bypass ( SPD_BYPS) . When set t o 1, all speed det ect ion
mechanisms are bypassed, and t he device is immediat ely set t o t he speed
indicat ed by CTRL. SPEED. This provides a met hod for soft ware t o have full
cont rol of t he speed set t ings of t he device when t he change t akes place by
overriding hardware clock swit ching circuit ry.
19 RW/ SN 0b
Dynamic Clock Gat ing ( DynCK) . When set , t his bit enables dynamic clock
gat ing of t he DMA and MAC unit s. Refer t o t he descript ion of t he
DynWakeCK in t his regist er. This bit is loaded from NVM word 0x13.
20 RW/ SN 1b
PHY Power Down Enable ( PHYPDEN) . When set , t his bit enables t he 82578
t o ent er a low- power st at e when t he MAC is at t he DMoff / D3 or Dr wit h
no WoL. This bit is loaded from word 0x13 in t he NVM.
25 RW 0b
DMA Clock Cont rol ( DMACKCTL) . Cont rols t he DMA clock source in non-
GbE mode ( 10/ 100 and no Link) . I n GbE mode, t he DMA clock source is
always GLCI PLL divided by t wo. I n normal operat ion, t his bit should be in
t he default st at e in which t he DMA clock source in non- GbE is mosc_clk.
I n t est mode t he DMACKCTL and PLLGat eDis should be set t o 1b and
CLK_CNT_1_4 in t he NVM should not be set . I n t his mode, t he DMA clock
source is GLCI PLL divided by t wo.
26 RW 0b
Disable St at ic GLCI PLL Gat ing ( PLLGat eDis) . By default t he PLL is
funct ional only when t he GLCI link is required, and inact ive when it is not
required ( at non- GbE mode if LCI is available) . When set t o 1b t he GLCI
PLL is always act ive.
27 RW 0b
I nt errupt Acknowledge Aut o- Mask Enable ( I AME) . When t his bit is set , a
read or writ e t o t he I CR regist er has t he side effect of writ ing t he value in
t he I AM regist er t o t he I MC regist er. When t his bit is 0b, t his feat ure is
disabled.

117
This regist er provides ext ended cont rol of device funct ionalit y beyond t hat provided by
t he Device Cont rol ( CTRL) regist er.
Not e: I f soft ware uses t he EE_RST funct ion and needs t o ret ain current configurat ion
informat ion, t he cont ent s of t he cont rol regist ers should be read and st ored by
soft ware. Cont rol regist er values are changed by a read of t he NVM, which occurs aft er
assert ing t he EE_RST bit .
Not e: The EEPROM reset funct ion might read configurat ion informat ion out of t he NVM, which
affect s t he configurat ion of PCI configurat ion space BAR set t ings. The changes t o t he
BAR' s are not visible unless t he syst em is reboot ed and t he BI OS is allowed t o re- map
t hem.
Not e: The SPD_BYPS bit performs a similar funct ion as t he CTRL. FRCSPD bit in t hat t he
device' s speed set t ings are det ermined by t he value soft ware writ es t o t he CRTL. SPEED
bit s. However, wit h t he SPD_BYPS bit assert ed, t he set t ings in CTRL. SPEED t ake effect
immediat ely rat her t han wait ing unt il aft er t he device' s clock swit ching circuit ry
performs t he change.
28 RW 0b
Driver loaded ( DRV_LOAD) . This bit should be set by t he driver aft er it was
loaded and cleared when t he driver unloads or aft er a soft reset . The
Manageabilit y Cont roller ( MC) loads t his bit t o indicat e t hat t he driver has
loaded.
29 RW 0b
I NT_TI MERS_CLEAR_ENA. When set , t his bit enables t he clear of t he
int errupt t imers following an I MS clear. I n t his st at e, successive int errupt s
occur only aft er t he t imers expire again. When cleared, successive
int errupt s following I MS clear might happen immediat ely.
30 0b Reserved.
31 RO 0b Reserved. Reads as 0.
118
I nt el
10.2.1.1.5 MDI Cont r ol Regi st er - MDI C ( 0x 00020; RW)
This regist er is used by soft ware t o read or writ e Management Dat a I nt erface ( MDI )
regist ers in t he 82578.
Not e: I nt ernal logic uses MDI C t o communicat e wit h t he 82578. All fields in t hese regist ers
are indicat ed as "/ V" since t he int ernal logic might use t hem t o access t he 82578. Since
hardware uses t his regist er, all hardware, soft ware and firmware must use semaphore
logic ( t he ownership flags) before accessing t he MDI C.
For an MDI read cycle t he sequence of event s is as follows:
1. The CPU performs a writ e cycle t o t he MI I regist er wit h:
Ready = 0b
I nt errupt Enable bit set t o 1b or 0b
Op- Code = 10b ( read)
PHYADD = The 82578 address from t he MDI regist er
REGADD = The regist er address of t he specific regist er t o be accessed ( 0
t hrough 31)
2. The MAC applies t he following sequence on t he MDI O signal t o t he 82578:
< PREAMBLE> < 01> < 10> < PHYADD> < REGADD> < Z>
where t he Z st ands for t he MAC t ri- st at ing t he MDI O signal.
3. The 82578 ret urns t he following sequence on t he MDI O signal:
< 0> < DATA> < I DLE>
4. The MAC discards t he leading bit and places t he following 16 dat a bit s in t he MI I
regist er.
5. The MAC assert s an I nt errupt indicat ing MDI done, if t he I nt errupt Enable bit was
set .
6. The MAC set s t he Ready bit in t he MI I regist er indicat ing t he read is complet e.
15: 0 RW/ V X
Dat a ( DATA) . I n a Writ e command, soft ware places t he dat a bit s and t he
MAC shift s t hem out t o t he 82578. I n a Read command, t he MAC reads
t hese bit s serially from t he 82578 and soft ware can read t hem from t his
locat ion.
20: 16 RW/ V 0x0 PHY Regist er address ( REGADD) . For example, regist er 0, 1, 2, 31.
25: 21 RW/ V 0x0 PHY Address ( PHYADD) .
27: 26 RW/ V 00b
Op- code ( OP) .
01b = MDI writ e.
10b = MDI read.
Ot her values are reserved.
28 RW/ V 1b
Ready bit ( R) . Set t o 1b by t he MAC at t he end of t he MDI t ransact ion ( for
example, indicat es a read or writ e complet ed) . I t should be reset t o 0b by
soft ware at t he same t ime t he command is writ t en.
29 RW/ V 0b
I nt errupt Enable ( I ) . When set t o 1b by soft ware, it causes an int errupt t o
be assert ed t o indicat e t he end of an MDI cycle.
30 RW/ V 0b
Error ( E) . This bit set is t o 1b by hardware when it fails t o complet e an
MDI read. Soft ware should make sure t his bit is clear ( 0b) before making
a MDI read or writ e command.
31 RO 0b Reserved. Writ e as 0b for fut ure compat ibilit y.

119
7. The CPU might read t he dat a from t he MI I regist er and issue a new MDI command.
For an MDI Writ e cycle t he sequence of event s is as follows:
1. The CPU performs a writ e cycle t o t he MI I regist er wit h:
Ready = 0b
I nt errupt Enable bit set t o 1b or 0b
Op- Code = 01b ( writ e)
PHYADD = The 82578 address from t he MDI regist er
REGADD = The regist er address of t he specific regist er t o be accessed ( 0
t hrough 31)
Dat a = specific dat a for desired cont rol of t he 82578
2. The MAC applies t he following sequence on t he MDI O signal t o t he 82578:
< PREAMBLE> < 01> < 01> < PHYADD> < REGADD> < 10> < DATA> < I DLE>
3. The MAC assert s an I nt errupt indicat ing MDI done if t he I nt errupt Enable bit was
set .
4. The MAC set s t he Ready bit in t he MI I regist er t o indicat e st ep 2 has been
complet ed.
5. The CPU might issue a new MDI command.
Not e: An MDI read or writ e might t ake as long as 64 ms from t he CPU writ e t o t he Ready bit
assert ion.
I f an invalid opcode is writ t en by soft ware, t he MAC does not execut e any accesses t o
t he 82578 regist ers.
I f t he 82578 does not generat e a zero as t he second bit of t he t urnaround cycle for
reads, t he MAC abort s t he access, set s t he E ( error) bit , writ es 0xFFFF t o t he dat a field
t o indicat e an error condit ion, and set s t he ready bit .
10.2.1.1.6 Fut ur e Ex t ended NVM Regi st er - FEXTNVM ( 0x 00028; RW)
This regist er is init ialized t o a hardware default only at LAN_RST# reset . Soft ware
should not modify t hese fields t o values ot her t han t heir recommended values. Bit s
15: 0 of t his regist er are loaded from t he NVM word 0s19 and bit s 31: 16 are loaded
from t he NVM word 0x1A.
0 RW/ SN 0b Reserved
1 RW/ SN 0b
dma_clk_enable_d. Enable dynamic clock st op. When t his bit is set t o 1b,
clk is always t icking. The default value is 0b ( hardware and NVM) .
2 RW/ SN 0b
wake_dma_clk_enable_d. Enable dynamic clock st op. When t his bit is set
t o 1b, clk is always t icking. The default value is 0b ( hardware and NVM)
3 RW/ SN 0b
gpt _clk_enable_d. Enable dynamic clock st op. When t his bit is set t o 1b,
clk is always t icking. The default value is 0b ( hardware and NVM)
4 RW/ SN 0b
mac_clk_enable_d. Enable dynamic clock st op. When t his bit is set t o 1b,
clk is always t icking. The default value is 0b ( hardware and NVM)
5 RW/ SN 0b
m2k_clk_enable_d. Enable dynamic clock st op. When t his bit is set t o 1b,
clk is always t icking. The default value is 0b ( hardware and NVM) .
6 RW/ SN 0b
I nvalid I mage CSUM. When cleared, t his bit indicat es t o t he I nt el NVM
programming t ools ( eeupdat e) t hat t he image CSUM needs t o be
correct ed. When set t he CSUM is assumed t o be correct .
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I nt el
9: 7 RW/ SN 0x0 Reserved.
10 RW/ SN 0b
Enable MDI O Wat chdog Timer ( MDI OWat chEna) . When set t o 0b, t he
100 ms MDI O wat chdog t imer is enabled.
Default NVM set t ing = 1b.
11 RW/ SN 0b
Updat e DMA PTR.
0b = The point er t o t he packet header is updat ed at t he st art of t he
packet .
1b = The point er t o t he packet header is updat ed at t he end of t he
previous packet ( legacy behavior) .
12 RW/ SN 0b
MAC Synchronizat ion.
1b = I n GbE mode, t he MAC does not need t o wait for synchronizat ion
bet ween clock domains ( t he clock domains are t he same) and t he
synchronizat ion st age is skipped.
0b = The synchronizat ion st age is not skipped.
When operat ing in 10/ 100 Mb/ s, t he synchronizat ion is st ill needed,
t herefore it is never skipped.
14 RW/ SN 0b
Aut o PHYI NT Clear.
0b = Clears t he int errupt indicat ion from t he 82578 immediat ely aft er t he
I CR is read.
15 RW/ SN 0b
Drop Rx Packet .
0b = Causes packet dropping when it comes, if no descript ors while early
receive is enabled.
20 RW/ SN 0b
Disable CLK gat e Enable Due t o D3hot . When set , disables assert ion of
bb_clkgat en due t o D3hot .
27 RW/ SN 0b
Soft ware LCD Config Enable. This bit has no impact on hardware but
rat her influences t he soft ware flow. The soft ware should init ialize t he
82578 using t he ext ended configurat ion image in t he NVM only when bot h
t he Soft ware LCD Config Enable bit is set and t he LCD Writ e Enable bit in
t he EXTCNF_CTRL regist er is cleared.
31: 28 RW/ SN 00b Reserved.

121
10.2.1.1.7 Fut ur e Ex t ended Regi st er - FEXT ( 0x 0002C; RW)
This regist er is init ialized t o a hardware default only at LAN_RST# reset . Soft ware
should not modify t hese fields t o values ot her t han t heir recommended values.
C
10.2.1.1.8 Devi ce and Bus Number - BUSNUM ( 0x 00038; RO)
10.2.1.1.9 Fl ow Cont r ol Tr ansmi t Ti mer Val ue - FCTTV ( 0x 00170; RW)
0 0b Reserved.
1 RO 0b Reserved.
3: 2 RO/ V 00b Reserved.
7: 4 RW 0x0 Reserved.
8 RW 0b
Hardware/ Soft ware CRC Mismat ch Trigger. When set t o 1b t he MAC
generat es a t rigger signal each t ime t here is a mismat ch bet ween t he
soft ware calculat ed CRC and hardware calculat ed CRC.
This feat ure is ignored when CRC calculat ion is off- loaded t o hardware.
9 RW 0b
Writ e Disable Ghost and DMA RAMs on CRC Mismat ch. When set t o 1b,
disables any writ es t o t he following RAMs in t he event of CRC mismat ch
unt il reset :
Ghost read PCI descript or
Ghost read PCI dat a
The four RAMs in t he descript or engine
The packet buffer
10 RW 0b
When set t o 1b, enables t he dat a visibilit y of t he ghost read PCI descript or
and PCI dat a RAMs t o t he NOA.
11 RW 0b
Visibilit y in/ out read dat a select . 1b = in.
Bit 10 of t he FEXT regist er must be set t o 1b.
12 RW 0b
Visibilit y dat a/ desc read Ram select . 1b = dat a.
Bit 10 of t he FEXT regist er must be set t o 1b.
13 RW 0b When set t o 1b, t he ghost read RAMs are readable by t he slave bus.
17: 14 RW 0x0 Must be set t o 0x0.
31: 18 RW 0x0 Fut ure Ext ended. Reserved for fut ure set t ing.
10: 8 RO 000b Funct ion Number. The MAC is a single PCI funct ion being funct ion 0.
15: 11 RO 0x19
Device Number. During normal operat ion, t he MAC has a predefined
device number equal t o 25 ( 0x19) .
23: 16 RO 0x0
Bus Number. The MAC capt ures it s bus number during host configurat ion
writ e cycles t ype 0 aimed at t he device. This field is init ialized by
LAN_RST# reset , PCI reset , and D3 t o D0 t ransit ion.
15: 0 RW X
Transmit Timer Value ( TTV) .
I ncluded in XOFF frame.
31: 16 RO 0x0 Reserved. Read as 0b. Should be writ t en t o 0b for fut ure compat ibilit y.
122
I nt el
The 16- bit value in t he TTV field is insert ed int o a t ransmit t ed frame ( eit her XOFF
frames or any PAUSE frame value in any soft ware t ransmit t ed packet s) . I t count s in
unit s of slot t ime. I f soft ware needs t o send an XON frame, it must set TTV t o zero prior
t o init iat ing t he PAUSE frame.
Not e: The MAC uses a fixed slot t ime value of 64 byt e t imes.
10.2.1.1.10 Fl ow Cont r ol Ref r esh Thr eshol d Val ue - FCRTV ( 0x 05F40; RW)
10.2.1.1.11 Ex t ended Conf i gur at i on Cont r ol - EXTCNF_CTRL ( 0x 00F00; RW)
15: 0 RW X
Flow Cont rol Refresh Threshold ( FCRT) . This value indicat es t he t hreshold
value of t he flow cont rol shadow count er. When t he count er reaches t his
value, and t he condit ions for a pause st at e are st ill valid ( buffer fullness
above low t hreshold value) , a pause ( XOFF) frame is sent t o t he link
part ner.
The FCRTV t imer count int erval is t he same as ot her flow cont rol t imers
and count s at slot t imes of 64 byt e t imes.
I f t his field cont ains a zero value, t he flow cont rol refresh is disabled.
31: 16 RO 0x0 Reserved. Read as 0b. Should be writ t en t o 0b for fut ure compat ibilit y.
0 RW/ SN 0b
LCD Writ e Enable. When set , enables t he ext ended PHY configurat ion area
in t he MAC. When disabled, t he ext ended PHY configurat ion area is
ignored. Loaded from NVM word 0x14.
2: 1 RW/ SN 00b Reserved
3 RW/ SN 1b
OEM Writ e Enable. When set , enables aut o load of t he OEM bit s from t he
PHY_CTRL regist er t o t he PHY. Loaded from NVM word 0x14.
4 RO 0b Reserved.
5 RW/ V 0b
Soft ware Semaphore FLAG ( SWFLAG) . This bit is set by t he device driver
t o gain access permission t o shared CSR regist ers wit h t he firmware and
hardware.
The bit is init ialized on power up PCI reset and soft ware reset .
6 RO/ V 0b
MDI O Hardware Ownership. Hardware request s access t o MDI O. Part of
t he arbit rat ion scheme for MDI O access. This is a RO bit .
27: 16 RW/ SN 0x001
Ext ended Configurat ion Point er. Defines t he base address ( in Dwords) of
t he ext ended configurat ion area in t he NVM.
31: 28 RW 0b Reserved.

123
10.2.1.1.12 Ex t ended Conf i gur at i on Si ze - EXTCNF_SI ZE ( 0x 00F08; RW)
10.2.1.1.13 PHY Cont r ol Regi st er - PHY_CTRL ( 0x 00F10; RW)
This regist er is init ialized t o a hardware default at LAN_RST# reset .
23: 16 RW/ SN 0x0
Ext ended LCD Lengt h. Size ( in Dwords) of t he ext ended PHY configurat ion
area loaded from Ext ended Configurat ion word 2 in t he NVM. I f an
ext ended configurat ion area is disabled by t he LCD Writ e Enable field in
word 0x14 in t he NVM, t his lengt h must be set t o zero.
15: 0 RW/ SN 0x0 Reserved
31: 29 RO 0x0 Reserved
28: 25 RO 0x0
SKU Read Dat a. These four bit s cont ain t he SKU value read from t he
82578 SKU regist er. Using t hese bit s, t he SKU mechanism det ermines t he
Device I D.
24 RO 0x0 Reserved.
23 RO 0x0 SKU done. This bit indicat es t he t erminat ion of SKU read.
16: 7 RO 0x0 Reserved
6 RW/ SN 0b
Global GbE Disable. Prevent s t he 82578 from aut o negot iat ing 1000 Mb/ s
link in all power st at es ( including D0a) . This bit is init ialized by word 0x17,
bit 14 in t he NVM.
5: 4 RO 00b Reserved.
3 RW/ SN 1b
GbE Disable at Non D0a. Prevent s t he 82578 from aut o negot iat ing
1000 Mb/ s link in all power st at es except D0a ( DR, D0u and D3) . Bit is
init ialized by word 0x17, bit 11 in t he NVM. This bit must be set since GbE
is not support ed in Sx by t he plat form.
2 RW/ SN 1b
LPLU in Non D0a. Enables t he 82578 t o negot iat e for slowest possible link
( reverse aut o negot iat e) in all power st at es except D0a ( DR, D0u and D3) .
This bit is init ialized by word 0x17, bit 10 in t he NVM.
1 RW/ SN 0b
LPLU in D0a. Enables t he 82578 t o negot iat e for t he slowest possible link
( reverse aut o negot iat e) in all power st at es ( including D0a) . This bit
overrides t he LPLU in non- D0abit . This bit is init ialized by word 0x17, bit 9
in t he NVM.
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10.2.1.1.14 PCI E Anal og Conf i gur at i on - PCI EANACFG ( 0x 00F18; RW)
10.2.1.1.15 Pack et Buf f er Al l ocat i on - PBA ( 0x 01000; RW)
This regist er set s t he on- chip receive and t ransmit st orage allocat ion rat io.
Not e: Programming t his regist er does not aut omat ically re- load or init ialize int ernal packet -
buffer RAM point ers. Soft ware must reset bot h t ransmit and receive operat ion ( using
t he global device reset CTRL. SWRST bit ) aft er changing t his regist er in order for it t o
t ake effect . The PBA regist er it self is not reset by assert ion of t he soft ware reset , but is
only reset upon init ial hardware power on.
Not e: I f early receive funct ionalit y is not enabled ( indicat e field/ regist er) , t he receive packet
buffer should be larger t han t he maximum expect ed received packet + 32 byt es.
Not e: For best performance, t he t ransmit buffer allocat ion should be set t o accept t wo full-
sized packet s.
Not e: Transmit packet buffer size should be configured t o be more t han 4 KB.
10.2.1.1.16 Pack et Buf f er Si ze - PBS ( 0x 01008; RW)
0 RW 0b
I nvert Polarit y. I ndicat es t o t he GP unit t o invert bit polarit y ( only
receiver) . t his bit is set from t he NVM.
6: 1 RW 0x20 Command Mode Volt age Select .
31: 7 RO 0x0 Reserved. Read as 0b ignore on writ e.
4: 0 RW 0x
Receive packet buffer allocat ion ( RXA) . Defines t he size of t he Rx buffer in
K byt e unit s. Default is KB.
15: 5 RO X Reserved.
20: 16 RO 0x
Transmit Packet Buffer Allocat ion ( TXA) . Defines t he size of t he Tx buffer in
KB unit s. This field is read only and equals t o t he Packet Buffer Size ( PBS)
minus RXA ( t he default value of t he PBS is KB) .
5: 0 0x0
Packet Buffer Size ( PBS) . Defines t he t ot al packet buffer size bot h for
t ransmit and receive in 1 KB granularit y. Soft ware should keep t his
regist er at a value of decimal ( equals KB) .
31: 6 RO 0x0 Reserved. Read as zero.

125
This regist er set s t he on- chip receive and t ransmit st orage allocat ion size. The
allocat ion value is read/ writ e for t he lower six bit s. The division bet ween t ransmit and
receive is done according t o t he PBA regist er.
Not e: Programming t his regist er does not aut omat ically re- load or init ialize int ernal packet -
buffer RAM point ers. Soft ware must reset bot h t ransmit and receive operat ion ( using
t he global device reset CTRL. SWRST bit ) aft er changing t his regist er in order for it t o
t ake effect . The PBS regist er it self is not reset by assert ion of t he soft ware reset , but is
only reset upon init ial hardware power on.
Not e: Programming t his regist er should be aligned wit h programming t he PBA regist er
hardware operat ion, if PBA and PBS are not coordinat ed is not det ermined.
10.2.1.1.17 Pack et Buf f er ECC St at us - PBECCSTS ( 0x 0100C; RW)
10.2.1.1.18 Pack et Buf f er ECC Er r or I nj ect - PBEEI ( 0x 01004; RW)
Bi t Type Reset Descr i pt i on
7: 0 RC 0x0
Correct able Error Count ( Corr_err_cnt ) . This count er is increment ed every
t ime a correct able error is det ect ed. The count er st ops count ing aft er
reaching 0xFF. Cleared by read.
15: 8 RC 0x0
Uncorrect able Error Count ( uncorr_err_cnt ) . This count er is increment ed
every t ime an uncorrect able error is det ect ed. The count er st ops count ing
aft er reaching 0xFF. Cleared by read.
16 RW 0b ECC enable.
17 RW 0b
St op on First Error ( SOFE) . When set , t he ECC t est capt ures t he failing
address int o Last Failure Address ( LFA) .
19: 18 RO 0x0 Reserved. Read as zero.
31: 20 RO 0x0
Last Failure Address ( LFA) . When St op on first Error ( SOFE) bit is set t o 1b,
when t here is ECC failure, t he LFA regist er capt ures t he failing address of
t he failure.
0 RW 0b
I nj ect an error on Tx Buffer on header line. When t his bit is set , an error is
inj ect ed in t he next writ e cycle t o a header line of t he Tx buffer. Aut o
cleared by hardware when an error is inj ect ed if PBECCI NJ. ENECCADD is
clear ( 0b) .
1 RW 0b
I nj ect an error on Tx Buffer on dat a line. When t his bit is set , an error is
inj ect ed in t he next writ e cycle t o a dat a line of t he Tx buffer. Aut o cleared
by hardware when an error is inj ect ed if PBECCI NJ. ENECCADD is clear
( 0b) .
2 RW 0b
I nj ect an error on Rx Buffer on header line. When t his bit is set , an error is
inj ect ed in t he next writ e cycle t o a header line of t he Rx buffer. Aut o
cleared by hardware when an error is inj ect ed if PBECCI NJ. ENECCADD is
clear ( 0b) .
3 RW 0b
I nj ect an error on Rx Buffer on dat a line. When t his bit is set , an error is
inj ect ed in t he next writ e cycle t o a dat a line of t he Rx buffer. Aut o cleared
by hardware when an error is inj ect ed if PBECCI NJ. ENECCADD is clear
( 0b) .
23: 16 RW 0x0 Error 1 bit locat ion ( value of 0xFF - No error inj ect ion on t his bit ) .
31: 24 RW 0x0 Error 2 bit locat ion ( value of 0xFF - No error inj ect ion on t his bit ) .
126
I nt el
10.2.1.1.19 Pack et Buf f er ECC I nj ect i on - PBECCI NJ ( 0x 01010; RW)
10. 2. 1. 2 I nt er r upt Regi st er Descr i pt i ons
10.2.1.2.1 I nt er r upt Cause Read Regi st er - I CR ( 0x 000C0; RC/ WC)
This regist er is RC or WC. I f enabled, read access also clears t he I CR cont ent aft er it is
post ed t o soft ware. Ot herwise, a writ e cycle is required t o clear t he relevant bit fields.
Writ e a 1b clears t he writ t en bit while writ ing 0b has no affect ( wit h t he except ion of
t he I NT_ASSERTED bit .
11: 0 RW 0x0 Address 0 I nj ect ion - Error inj ect ion first address in packet buffer.
23: 12 RW 0x0 Address 1 I nj ect ion - Error inj ect ion second address in packet buffer.
24 RW 0b
Enable ECC I nj ect ion t o Address ( ENACCADD) . When set t o 0b, t he
addresses for ECC inj ect ion from t his regist er are ignored.
0 RWC/ CR/ V 0b
Transmit Descript or Writ t en Back ( TXDW) . Set when hardware processes a
descript or wit h eit her RS set . I f using delayed int errupt s ( I DE set ) , t he
int errupt is delayed unt il aft er one of t he delayed- t imers ( TI DV or TADV)
expires.
1 RWC/ CR/ V 0b
Transmit Queue Empt y ( TXQE) . Set when, t he last descript or block for a
t ransmit queue has been used. When configured t o use more t han one
t ransmit queue t his int errupt indicat ion is issued if one of t he queues is
empt y and is not cleared unt il all t he queues have valid descript ors.
2 RWC/ CR/ V 0b
Link St at us Change ( LSC) . This bit is set each t ime t he link st at us changes
( eit her from up t o down, or from down t o up) . This bit is affect ed by t he
LI NK indicat ion from t he 82578.
3 RO 0b Reserved.
4 RWC/ CR/ V 0b
Receive Descript or Minimum Threshold hit ( RXDMT0) . I ndicat es t hat t he
minimum number of receive descript ors RCTL. RDMTS are available and
soft ware should load more receive descript ors.
5 RWC/ CR/ V 0b
Disable Soft ware Writ e Access ( DSW) . The DSW bit indicat es t hat firmware
changed t he st at us of t he DI SSW or t he DI SSWLNK bit s in t he FWSM
regist er.
6 RWC/ CR/ V 0b
Receiver Overrun ( RXO) . Set on receive dat a FI FO overrun. Could be
caused eit her because t here are no available buffers or because receive
bandwidt h is inadequat e.
7 RWC/ CR/ V 0b Receiver Timer I nt errupt ( RXT0) . Set when t he t imer expires.
8 RWC/ CR/ V 0b
LCAPD Exit I nt errupt ( LCAPD) . Set when t he I nt el
5 Series Express
Chipset t akes t he MAC out of LCAPD st at e.
9 RWC/ CR/ V 0b MDI O Access Complet e ( MDAC) . Set when t he MDI O access complet es.
12 RWC/ CR/ V 0b PHY I nt errupt ( PHYI NT) . Set when t he 82578 generat es an int errupt .
13 RO 0b Reserved.
14 RWC/ CR/ V 0b Reserved.
15 RWC/ CR/ V 0b
Transmit Descript or Low Threshold hit ( TXD_LOW) . I ndicat es t hat t he
descript or ring has reached t he t hreshold specified in t he Transmit
Descript or Cont rol regist er.

127
This regist er cont ains all int errupt condit ions for t he MAC. Each t ime an int errupt
causing event occurs, t he corresponding int errupt bit is set in t his regist er. An int errupt
is generat ed each t ime one of t he bit s in t his regist er is set , and t he corresponding
int errupt is enabled via t he I nt errupt Mask Set / Read regist er ( see Sect ion 10. 2. 1.3. 5) .
Each t ime an int errupt causing event occurs, all t imers of delayed int errupt s are cleared
and t heir cause event is set in t he I CR.
Read I CR regist er is affect ed different ly in t he following cases:
Case 1 - I nt errupt Mask regist er equals 0x0000 ( mask all) - I CR cont ent is
cleared.
Case 2 - I nt errupt was assert ed ( I CR. I NT_ASSERTED= 1) - I CR cont ent is
cleared and aut o mask is act ive, meaning, t he I AM regist er is writ t en t o t he
I MC regist er.
Case 3 - I nt errupt was not assert ed ( I CR. I NT_ASSERTED= 0) - Read has no
side affect .
Writ ing a 1b t o any bit in t he regist er also clears t hat bit . Writ ing a 0b t o any bit has no
effect on t hat bit . The I NT_ASSERTED bit is a special case. Writ ing a 1b or 0b t o t his bit
has no affect . I t is cleared only when all int errupt sources are cleared.
10.2.1.2.2 I nt er r upt Thr ot t l i ng Regi st er - I TR ( 0x 000C4; RW)
Soft ware can use t his regist er t o pace ( or even out ) t he delivery of int errupt s t o t he
host CPU. This regist er provides a guarant eed int er- int errupt delay bet ween int errupt s
assert ed by t he net work cont roller, regardless of net work t raffic condit ions. To
independent ly validat e configurat ion set t ings, soft ware can use t he following algorit hm
t o convert t he int er- int errupt int erval value t o t he common ' int errupt s/ sec'
performance met ric:
I nt errupt s/ sec = ( 256 x 10
- 9
sec x int erval)
- 1

For example, if t he int erval is programmed t o 500d, t he net work cont roller guarant ees
t he CPU is not int errupt ed by t he net work cont roller for 128 ms from t he last int errupt .
16 RWC/ CR/ V 0b
Small Receive Packet Det ect ed ( SRPD) . I ndicat es t hat a packet size
< RSRPD. SI ZE regist er has been det ect ed and t ransferred t o host
memory. The int errupt is only assert ed if RSRPD.SI ZE regist er has a non-
zero value.
17 RWC/ CR/ V 0b
Receive ACK Frame Det ect ed ( ACK) . I ndicat es t hat an ACK frame has been
received and t he t imer in RAI D. ACK_DELAY has expired.
21: 18 RWC/ CR/ V 0x0 Reserved.
22 RWC/ CR/ V 0b ECC Error ( ECCER) . I ndicat es an uncorrect able EEC error occurred.
30: 23 RO 0x0 Reserved. Reads as 0b.
31 RWC/ CR/ V 0b
I nt errupt Assert ed ( I NT_ASSERTED) . This bit is set when t he LAN port has
a pending int errupt . I f t he I nt errupt is enabled in t he PCI configurat ion
space, an int errupt is assert ed.
15: 0 RW 0x0
I NTERVAL. Minimum int er- int errupt int erval. The int erval is specified in
256 ns unit s. Zero disables int errupt t hrot t ling logic.
31: 16 RO 0x0 Reserved. Should be writ t en wit h 0b t o ensure fut ure compat ibilit y.
128
I nt el
I nversely, int er- int errupt int erval value can be calculat ed as:
int er- int errupt int erval = ( 256 x 10
- 9
sec x int errupt s/ sec)
- 1

The opt imal performance set t ing for t his regist er is very syst em and configurat ion
specific. An init ial suggest ed range for t he int erval value is 65- - 5580 ( 28B - 15CC) .
Not e: When working at 10/ 100 Mb/ s and running at clock t he int erval t ime is mult iplied by
four.
10.2.1.2.3 I nt er r upt Cause Set Regi st er - I CS ( 0x 000C8; WO)
Soft ware uses t his regist er t o set an int errupt condit ion. Any bit writ t en wit h a 1b set s
t he corresponding int errupt . This result s in t he corresponding bit being set in t he
I nt errupt Cause Read regist er ( see Sect ion 10.2. 1. 3) , and an int errupt is generat ed if
one of t he bit s in t his regist er is set , and t he corresponding int errupt is enabled via t he
I nt errupt Mask Set / Read regist er ( see Sect ion 10.2.1. 3. 5) .
Bit s writ t en wit h 0b are unchanged.
0 WO X TXDW. Set s t ransmit descript or writ t en back.
1 WO X TXQE. Set s t ransmit queue empt y.
2 WO X LSC. Set s link st at us change.
3 RO X Reserved.
4 WO X RXDMT. Set s receive descript or minimum t hreshold hit .
5 WO X DSW. Set s block soft ware writ e accesses.
6 WO X RXO. Set s receiver overrun. Set on receive dat a FI FO overrun.
7 WO X RXT. Set s receiver t imer int errupt .
8 WO X LCAPD. Set s LCAPD int errupt .
9 WO X MDAC. Set s MDI O access complet e int errupt .
12 WO X PHYI NT. Set s PHY int errupt .
13 RO X Reserved.
14 WO X Reserved.
15 WO X TXD_LOW. Transmit descript or low t hreshold hit .
16 WO X Small Receive Packet Det ect ed ( SRPD) and t ransferred.
17 WO X ACK. Set receive ACK frame det ect ed.
18 WO X MNG. Set t he manageabilit y event int errupt .
19 WO X Reserved.
20 WO X Reserved.
21 RO X Reserved.
22 WO X ECCER Set uncorrect able EEC error.
31: 23 RO X Reserved. Should be writ t en wit h 0b t o ensure fut ure compat ibilit y.

129
10.2.1.2.4 I nt er r upt Mask Set / Read Regi st er - I MS ( 0x 000D0; RW)
Reading t his regist er ret urns which bit s have an int errupt mask set . An int errupt is
enabled if it s corresponding mask bit is set t o 1b, and disabled if it s corresponding
mask bit is set t o 0b. An int errupt is generat ed each t ime one of t he bit s in t his regist er
is set , and t he corresponding int errupt condit ion occurs. The occurrence of an int errupt
condit ion is reflect ed by having a bit set in t he I nt errupt Cause Read regist er ( see
Sect ion 10. 2. 1.3) .
A part icular int errupt might be enabled by writ ing a 1b t o t he corresponding mask bit in
t his regist er. Any bit s writ t en wit h a 0b are unchanged.
Not e: I f soft ware desires t o disable a part icular int errupt condit ion t hat had been previously
enabled, it must writ e t o t he I nt errupt Mask Clear regist er ( see Sect ion 10. 2. 1.3. 6) ,
rat her t han writ ing a 0b t o a bit in t his regist er.
When t he CTRL_EXT. I NT_TI MERS_CLEAR_ENA bit is set , t hen following writ ing all 1b' s
t o t he I MS regist er ( enable all int errupt s) all int errupt t imers are cleared t o t heir init ial
value. This aut o clear provides t he required lat ency before t he next I NT event .
0 RWS 0b TXDW. Set s t ransmit descript or writ t en back.
1 RWS 0b TXQE. Set s t ransmit queue empt y.
2 RWS 0b LSC. Set s link st at us change.
3 RO 0b Reserved.
4 RWS 0b RXDMT0. Set s mask for receive descript or minimum t hreshold hit .
5 RWS 0b DSW. Set s mask for block soft ware writ e accesses.
6 RWS 0b RXO. Set s mask for receiver overrun. Set on receive dat a FI FO overrun.
7 RWS 0b RXT0. Set s mask for receiver t imer int errupt .
8 RWS 0b
LCAPD. Set s mask for LCAPD int errupt . LCAPD mask is set aft er reset t o
enable LCAPD int errupt ( driven by I nt el
5 Series Express Chipset ) .

9 RWS 0b MDAC. Set s mask for MDI O access complet e int errupt .
12 RWS 0b PHYI NT. Set s mask for PHY int errupt .
13 RO 0b Reserved.
14 RWS 0b Reserved.
15 RWS 0b TXD_LOW. Set s t he mask for t ransmit descript or low t hreshold hit .
16 RWS 0b SRPD. Set s mask for small receive packet det ect ion.
17 RWS 0b ACK. Set s t he mask for receive ACK frame det ect ion.
18 RWS 0b MNG. Set s mask for manageabilit y event int errupt .
19 RWS 0b Reserved.
20 RWS 0b Reserved.
21 RO 0b Reserved.
22 RWS 0b ECCER Set s mask for uncorrect able EEC error
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10.2.1.2.5 I nt er r upt Mask Cl ear Regi st er - I MC ( 0x 000D8; WO)
Soft ware uses t his regist er t o disable an int errupt . I nt errupt s are present ed t o t he bus
int erface only when t he mask bit is a 1b and t he cause bit is a 1b. The st at us of t he
mask bit is reflect ed in t he I nt errupt Mask Set / Read regist er, and t he st at us of t he
cause bit is reflect ed in t he I nt errupt Cause Read regist er ( see Sect ion 10.2. 1. 3) .
Soft ware blocks int errupt s by clearing t he corresponding mask bit . This is accomplished
by writ ing a 1b t o t he corresponding bit in t his regist er. Bit s writ t en wit h 0b are
unchanged ( t heir mask st at us does not change) .
I n summary, t he sole purpose of t his regist er is t o enable soft ware a way t o disable
cert ain, or all, int errupt s. Soft ware disables a given int errupt by writ ing a 1b t o t he
corresponding bit in t his regist er.
0 WO 0b TXDW. Set s t ransmit descript or writ t en back.
1 WO 0b TXQE. Set s t ransmit queue empt y.
2 WO 0b LSC. Set s link st at us change.
3 RO 0b Reserved.
4 WO 0b RXDMT0. Clears mask for receive descript or minimum t hreshold hit .
5 WO 0b DSW. Clears mask for block soft ware Writ e accesses.
6 WO 0b RXO. Clears mask for receiver overrun.
7 WO 0b RXT0. Clears mask for receiver t imer int errupt .
8 WO 0b LCAPD. Clears mask for LCAPD int errupt .
9 WO 0b MDAC. Clears mask for MDI O access complet e int errupt .
11: 10 RO 00b Reserved. Reads as 0b.
12 WO 0b PHYI NT. Clears PHY int errupt .
13 RO 0b Reserved.
14 WO 0b Reserved.
15 WO 0b TXD_LOW. Clears t he mask for t ransmit descript or low t hreshold hit .
16 WO 0b SRPD. Clears mask for small receive packet det ect int errupt .
17 WO 0b ACK. Clears t he mask for receive ACK frame det ect int errupt .
18 WO 0b MNG. Clears mask for t he manageabilit y event int errupt .
19 WO 0b Reserved.
20 WO 0b Reserved.
21 RO 0b Reserved.
22 WO 0b ECCER Clears t he mask for uncorrect able EEC error.

131
10.2.1.2.6 I nt er r upt Ack now l edge Aut o- Mask - I AM ( 0x 000E0; RW)
10. 2. 1. 3 Recei v e Regi st er Descr i pt i ons
10.2.1.3.1 Recei ve Cont r ol Regi st er - RCTL ( 0x 00100; RW)
31: 0 RW 0x0
I AM_VALUE. When t he CTRL_EXT. I AME bit is set and t he
I CR.I NT_ASSERTED= 1, an I CR read or writ e has t he side effect of writ ing
t he cont ent s of t his regist er t o t he I MC regist er.
0 RO 0b
Reserved. This bit represent s a hardware reset of t he receive- relat ed
port ion of t he device in previous cont rollers, but is no longer applicable.
Only a full device reset CTRL. SWRST is support ed. Writ e as 0b for fut ure
compat ibilit y.
1 RW 0b
Enable ( EN) . The receiver is enabled when t his bit is 1b. Writ ing t his bit t o
0b st ops recept ion aft er receipt of any in progress packet s. All subsequent
packet s are t hen immediat ely dropped unt il t his bit is set t o 1b.
Not e t hat t his bit cont rols only DMA funct ionalit y t o t he host . Packet s are
count ed by t he st at ist ics even when t his bit is cleared.
2 RW 0b
St ore bad packet s ( SBP) .
0b = Do not st ore bad packet s.
1b = St ore bad packet s.
Not e t hat CRC errors before t he SFD are ignored. Any packet must have a
valid SFD in order t o be recognized by t he MAC ( even bad packet s) .
Not e: Packet errors are not rout ed t o manageabilit y even if t his bit is set .
3 RW 0b
Unicast promiscuous enable ( UPE) .
0b = Disabled.
1b = Enabled.
4 RW 0b
Mult icast promiscuous enable ( MPE) .
0b = Disabled.
1b = Enabled.
5 RW 0b
Long packet enable ( LPE) .
0b = Disabled.
1b = Enabled.
7: 6 RW 00b Reserved.
9: 8 RW 0b
Receive Descript or Minimum Threshold Size ( RDMTS) . The corresponding
int errupt is set each t ime t he fract ional number of free descript ors
becomes equal t o RDMTS. Table 84 list s which fract ional values correspond
t o RDMTS values. See Sect ion 10.2. 1. 4. 8 for det ails regarding RDLEN.
11: 10 RW 00b
Descript or Type ( DTYP) .
00b = Legacy or ext ended descript or t ype.
01b = Packet split descript or t ype.
10b and 11b = Reserved.
13: 12 RW 00b
Mult icast Offset ( MO) . This det ermines which bit s of t he incoming
mult icast address are used in looking up t he bit vect or.
00b = 47: 38.
01b = [ 46: 37.
10b = 45: 36.
11b = 43: 34.
14 RW 0b Reserved.
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15 RW 0b
Broadcast Accept Mode ( BAM) .
0b = I gnore broadcast ( unless it mat ches t hrough exact or imperfect
filt ers) .
1 = Accept broadcast packet s.
17: 16 RW 00b
Receive Buffer Size ( BSI ZE) .
RCTL. BSEX zero:
00b = 2048 byt es.
01b = 1024 byt es.
10b = 512 byt es.
11b = 256 byt es.
RCTL. BSEX one:
00b = Reserved.
01b = 16384 byt es.
10b = 8192 byt es.
11b = 4096 byt es.
BSI ZE is only used when DTYP 00b. When DTYP 01b, t he buffer sizes
for t he descript or are cont rolled by fields in t he PSRCTL regist er.
BSI ZE is not relevant when t he FLXBUF is ot her t han zero, in t hat case,
FLXBUF det ermines t he buffer size.
21: 18 RO 0x0 Reserved. Should be writ t en wit h 0b.
22 RW 0b Reserved.
23 RW 0b
Pass MAC Cont rol Frames ( PMCF) .
0b = Do not ( specially) pass MAC cont rol frames.
1 = Pass any MAC cont rol frame ( t ype field value of 0x8808) t hat does not
cont ain t he pause opcode of 0x0001.
24 RO 0b Reserved. Should be writ t en wit h 0b t o ensure fut ure compat ibilit y.
25 RW 0b
Buffer Size Ext ension ( BSEX) .
Modifies buffer size indicat ion ( BSI ZE) .
0b = Buffer size is as defined in BSI ZE.
1b = Original BSI ZE values are mult iplied by 16.
26 RW 0b
St rip Et hernet CRC from incoming packet ( SECRC) .
0b = Does not st rip CRC.
1b = St rips CRC.
The st ripped CRC is not DMA' d t o host memory and is not included in t he
lengt h report ed in t he descript or.
30: 27 RW 0x0
FLXBUF. Det ermines a flexible buffer size. When t his field is 0000b, t he
buffer size is det ermined by BSI ZE. I f t his field is different from 0000b, t he
receive buffer size is t he number represent ed in KB:
For example, 0001 = 1 KB ( 1024 byt es) .

133
LPE cont rols whet her long packet recept ion is permit t ed. Hardware discards long
packet s if LPE is 0b. A long packet is one longer t han 1522 byt es. I f LPE is 1b, t he
maximum packet size t hat t he device can receive is byt es.
RDMTS{ 1, 0} det ermines t he t hreshold value for free receive descript ors according t o
t he following t able:
Tabl e 84. RDMTS Val ues
BSI ZE cont rols t he size of t he receive buffers and permit s soft ware t o t rade- off
descript or performance versus required st orage space. Buffers t hat are 2048 byt es
require only one descript or per receive packet maximizing descript or efficiency. Buffers
t hat are 256 byt es maximize memory efficiency at a cost of mult iple descript ors for
packet s longer t han 256 byt es.
PMCF cont rols t he DMA funct ion of t he MAC cont rol frames ( ot her t han flow cont rol) . A
MAC cont rol frame in t his cont ext must be addressed t o eit her t he MAC cont rol frame
mult icast address or t he st at ion address, mat ch t he t ype field and NOT mat ch t he
PAUSE opcode of 0x0001. I f PMCF = 1b t hen frames meet ing t his crit eria is DMA' d t o
host memory.
The SECRC bit cont rols whet her hardware st rips t he Et hernet CRC from t he received
packet . This st ripping occurs prior t o any checksum calculat ions. The st ripped CRC is
not DMA' d t o host memory and is not included in t he lengt h report ed in t he descript or.
RDMTS Fr ee Buf f er Thr eshol d
00b 1/ 2
01b 1/ 4
10b 1/ 8
11b Reserved
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10.2.1.3.2 Recei ve Cont r ol Regi st er 1 - RCTL1 ( 0x 00104; RW)
7: 0 RO 0x0
Reserved. This bit represent s a hardware reset of t he receive- relat ed
port ion of t he device in previous cont rollers, but is no longer applicable.
Only a full device reset CTRL. SWRST is support ed. Writ e as 0b for fut ure
compat ibilit y.
9: 8 RW 00b
Receive Descript or Minimum Threshold Size ( RDMTS) . The corresponding
int errupt is set each t ime t he fract ional number of free descript ors
becomes equal t o RDMTS. Table 84 list s which fract ional values
correspond t o RDMTS values. See Sect ion 10. 2. 1. 4. 8 for det ails regarding
RDLEN.
11: 10 RW 00b
Descript or Type ( DTYP) .
00b = Legacy or Ext ended descript or t ype.
01b = Packet Split descript or t ype.
10b and 11b = Reserved.
The value of RCTL1. DTYP should be t he same as RCTL. DTYP
17: 16 RW 00b
Receive Buffer Size ( BSI ZE) .
RCTL. BSEX zero:
00b = 2048 Byt es.
01b = 1024 Byt es.
10b = 512 Byt es.
11b = 256 Byt es.
RCTL. BSEX one:
00b = Reserved.
01b = 16384 Byt es.
10b = 8192 Byt es.
11b = 4096 Byt es.
BSI ZE is only used when DTYP 00b. When DTYP 01b, t he buffer sizes
for t he descript or are cont rolled by fields in t he PSRCTL regist er.
BSI ZE is not relevant when t he FLXBUF is ot her t han zero, in t hat case,
FLXBUF det ermines t he buffer size.
25 RW 0b
Buffer Size Ext ension ( BSEX) .
Modifies buffer size indicat ion ( BSI ZE above) .
0b = Buffer size is as defined in BSI ZE.
1b = Original BSI ZE values are mult iplied by 16.
26 RW 0b Reserved. Should be writ t en wit h 0b.
30: 27 RW 0x0
FLXBUF. Det ermine a flexible buffer size. When t his field is 0000b, t he
buffer size is det ermined by BSI ZE. I f t his field is different from 0000b,
t he receive buffer size is t he number represent ed in KB.
For example, 0001b = 1 KB ( 1024 byt es) .

135
10.2.1.3.3 Ear l y Recei ve Thr eshol d - ERT ( 0x 02008; RW)
This regist er cont ains t he Rx t hreshold value. This t hreshold det ermines how many
byt es of a given packet should be in t he MAC' s on- chip receive packet buffer before it
at t empt s t o begin t ransmission of t he frame on t he host bus. This regist er enables
soft ware t o configure t he early receive mode.
This field has a granularit y of eight byt es. So, if t his field is writ t en t o 0x20, which
corresponds t o a t hreshold of 256 ( decimal) byt es. I f t he size of a given packet is
smaller t han t he t hreshold value, or if t his regist er is set t o 0b, t hen t he MAC st art s t he
PCI t ransfer only aft er t he ent ire packet is cont ained in t he MAC' s receive packet buffer.
t he MAC examines t his regist er on a cycle- by- cycle basis t o det ermine if t here is
enough dat a t o st art a t ransfer for t he given frame over t he PCI bus.
Once t he MAC acquires t he bus, it at t empt s t o DMA all of t he dat a collect ed in t he
int ernal receive packet buffer so far.
The only negat ive affect of set t ing t his value t oo low is t hat it causes addit ional PCI
burst s for t he packet . I n ot her words, t his regist er enables soft ware t o t rade- off lat ency
versus bus ut ilizat ion. Too high a value effect ively eliminat es t he early receive benefit s
( at least for short packet s) and t oo low a value det eriorat es PCI bus performance due
t o a large number of small burst s for each packet . The RUTEC st at ist ic count s cert ain
cases where t he ERT has been set t oo low, and t hus provides soft ware a feedback
mechanism t o bet t er t une t he value of t he ERT.
I t should also be not ed t hat t his regist er has an effect only when t he receive packet
buffer is nearly empt y ( t he only dat a in t he packet buffer is from t he packet t hat is
current ly on t he wire) .
Not e: When early receive is used in parallel t o t he packet split feat ure, t he minimum value of
t he ERT regist er should be bigger t han t he header size t o enable t he act ual packet split .
12: 0 RW 0x0
Receive Threshold Value ( RxThreshold) . This t hreshold is in unit s of eight
byt es.
31: 22 RO 0x0 Reserved. Reads as 0b. Should be writ t en t o 0b for fut ure compat ibilit y.
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10.2.1.3.4 Pack et Spl i t Recei v e Cont r ol Regi st er - PSRCTL ( 0x 02170)
Not e: I f soft ware set s a buffer size t o zero, all buffers following t hat one must be set t o zero
as well. Point ers in t he receive descript ors t o buffers wit h a zero size should be set t o
anyt hing but NULL point ers.
10.2.1.3.5 Fl ow Cont r ol Recei ve Thr eshol d Low - FCRTL ( 0x 02160; RW)
This regist er cont ains t he receive t hreshold used t o det ermine when t o send an XON
packet . I t count s in unit s of byt es. The lower t hree bit s must be programmed t o zero
( 8- byt e granularit y) . Soft ware must set XONE t o enable t he t ransmission of XON
frames. Each t ime hardware crosses t he receive high t hreshold ( becoming more full) ,
and t hen crosses t he receive low t hreshold and XONE is enabled ( = 1b) , hardware
t ransmit s an XON frame.
Not e t hat flow cont rol recept ion/ t ransmission are negot iat ed capabilit ies by t he aut o-
negot iat ion process. When t he MAC is manually configured, flow cont rol operat ion is
det ermined by t he RFCE and TFCE bit s of t he Device Cont rol regist er.
6: 0 RW 0x2
Receive Buffer Size for Buffer 0 ( BSI ZE0) .
The value is in 128- byt e resolut ion. Value can be from 128 byt es t o 16256
byt es ( 15. 875 KB) . Default buffer size is 256 byt es. Soft ware should not
program t his field t o a zero value.
13: 8 RW 0x4
The value is in 1 KB resolut ion. Value can be from 1 KB t o 63 KB. Default
buffer size is 4 KB. Soft ware should not program t his field t o a zero value.
15: 14 RO 00b Reserved. Should be writ t en wit h 0b t o ensure fut ure compat ibilit y.
21: 16 RW 0x4
buffer size is 4 KB. Soft ware might program t his field t o any value.
29: 24 RW 0x0
buffer size is 0 KB. Soft ware might program t his field t o any value.
2: 0 RO 0x0
Reserved. The underlying bit s might not be implement ed in all versions of
t he chip. Must be writ t en wit h 0b.
15: 3 RW 0x0
Receive Threshold Low ( RTL) . FI FO low wat er mark for flow cont rol
t ransmission.
31 RW 0b
XON Enable ( XONE) .
0b = Disabled.
1b = Enabled.

137
10.2.1.3.6 Fl ow Cont r ol Recei ve Thr eshol d Hi gh - FCRTH ( 0x 02168; RW)
This regist er cont ains t he receive t hreshold used t o det ermine when t o send an XOFF
packet . I t count s in unit s of byt es. This value must be at least eight byt es less t han t he
maximum number of byt es allocat ed t o t he Receive Packet Buffer ( PBA, RXA) , and t he
lower t hree bit s must be programmed t o zero ( 8- byt e granularit y) . Each t ime t he
receive FI FO reaches t he fullness indicat ed by RTH, hardware t ransmit s a PAUSE frame
if t he t ransmission of flow cont rol frames is enabled.
Not e t hat flow cont rol recept ion/ t ransmission are negot iat ed capabilit ies by t he aut o-
negot iat ion process. When t he MAC is manually configured, flow cont rol operat ion is
det ermined by t he RFCE and TFCE bit s of t he Device Cont rol regist er.
10.2.1.3.7 Recei ve Descr i pt or Base Addr ess Low Queue - RDBAL ( 0x 02800; RW)
This regist er cont ains t he lower bit s of t he 64- bit descript or base address. The lower
four bit s are always ignored. The receive descript or base address must point t o a 16-
byt e aligned block of dat a.
10.2.1.3.8 Recei ve Descr i pt or Base Addr ess Hi gh Queue - RDBAH ( 0x 02804; RW)
This regist er cont ains t he upper 32 bit s of t he 64- bit descript or base address.
2: 0 RO 0x0 Reserved. Must be writ t en wit h 0.
15: 3 RW 0x0
Receive Threshold High ( RTH) . FI FO high wat er mark for flow cont rol
t ransmission.
3: 0 RO 0x0 Reserved. I gnored on writ es. Ret urns 0b on reads.
31: 4 RW X Receive Descript or Base Address Low ( RDBAL) .
Bi t s Type Reset Descr i pt i on
31: 0 RW X Receive Descript or Base Address [ 63: 32] ( RDBAH) .
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10.2.1.3.9 Recei ve Descr i pt or Lengt h Queue- RDLEN ( 0x 02808; RW)
This regist er set s t he number of byt es allocat ed for descript ors in t he circular descript or
buffer. I t must be 128- byt e aligned.
Not e: The descript or ring must be equal t o or larger t han eight descript ors.
10.2.1.3.10 Recei ve Descr i pt or Head Queue - RDH ( 0x 02810; RW)
This regist er cont ains t he head point er for t he receive descript or buffer. The regist er
point s t o a 16- byt e dat um. Hardware cont rols t he point er. The only t ime t hat soft ware
should writ e t o t his regist er is aft er a reset ( hardware reset or CTRL. SWRST) and
before enabling t he receive funct ion ( RCTL. EN) . I f soft ware were t o writ e t o t his
regist er while t he receive funct ion was enabled, t he on- chip descript or buffers might be
invalidat ed and hardware could be become unst able.
10.2.1.3.11 Recei ve Descr i pt or Tai l Queue - RDT ( 0x 02818; RW)
This regist er cont ains t he t ail point er for t he receive descript or buffer. The regist er
point s t o a 16- byt e dat um. Soft ware writ es t he t ail regist er t o add receive descript ors
for hardware t o process.
10.2.1.3.12 I nt er r upt Del ay Ti mer ( Pack et Ti mer ) - RDTR ( 0x 02820; RW)
This regist er is used t o delay int errupt not ificat ion for t he receive descript or ring by
coalescing int errupt s for mult iple received packet s. Delaying int errupt not ificat ion helps
maximize t he number of receive packet s serviced by a single int errupt .
6: 0 RO 0x0 Reserved. I gnore on writ e. Reads back as 0b.
19: 7 RW 0x0 Descript or Lengt h ( LEN)
15: 0 RW/ V 0x0 Receive Descript or Head ( RDH) .
15: 0 RW 0x0 Receive Descript or Tail ( RDT) .
15: 0 RW 0x0
Receive Delay Timer. Receive packet delay t imer measured in increment s of 1. 024
ms.
31 WO 0b Flush Part ial Descript or Block ( FPD) , when set t o 1b, ignored ot herwise. Reads 0b.

139
This feat ure operat es by init iat ing a count down t imer upon successfully receiving each
packet t o syst em memory. I f a subsequent packet is received BEFORE t he t imer
expires, t he t imer is re- init ialized t o t he programmed value and rest art s it s
count down. I f t he t imer expires due t o NOT having received a subsequent packet wit hin
t he programmed int erval, pending receive descript or writ e backs are flushed and a
receive t imer int errupt is generat ed.
Set t ing t he value t o 0b represent s no delay from a receive packet t o t he int errupt
not ificat ion, and result s in immediat e int errupt not ificat ion for each received packet .
Writ ing t his regist er wit h FPD set init iat es an immediat e expirat ion of t he t imer, causing
a writ e back of any consumed receive descript ors pending writ e back, and result s in a
receive t imer int errupt in t he I CR.
Receive int errupt s due t o a Receive Absolut e Timer ( RADV) expirat ion cancels a
pending RDTR int errupt . The RDTR count down t imer is reloaded but st opped, so as t o
avoid generat ion of a spurious second int errupt aft er t he RADV has been not ed, but
might be rest art ed by a subsequent received packet .
Not e: FPD is self- clearing.
10.2.1.3.13 Recei ve Descr i pt or Cont r ol - RXDCTL ( 0x 02828; RW)
Not e: This regist er was not fully validat ed. Soft ware should set it t o 0x0000 during normal
operat ion.
This regist er cont rols t he fet ching and writ e back of receive descript ors. The t hree
t hreshold values are used t o det ermine when descript ors is read from and writ t en t o
host memory. The values might be in unit s of cache lines or descript ors ( each
descript or is 16 byt es) based on t he GRAN flag. I f GRAN= zero ( specificat ions are in
cacheline granularit y) , t he t hresholds specified ( based on t he cache line size specified
in t he PCI configurat ion space CLS field) must not represent great er t han 31
descript ors.
Not e: When ( WTHRESH = 0b) or ( WTHRESH = 1b and GRAN = 1b) only descript ors wit h t he
RS bit set is writ t en back.
5: 0 RW 0x00 Prefet ch Threshold ( PTHRESH) .
13: 8 RW 0x00 Host Threshold ( HTHRESH) .
14 RW 0b Reserved.
15 RW 0b Reserved.
21: 16 RW 0x01 Writ e- Back Threshold ( WTHRESH) .
24 RW 0b
Granularit y ( GRAN) . Unit s for t he t hresholds in t his regist er.
0b = Cache lines.
1b = Descript ors.
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PTHRESH is used t o cont rol when a prefet ch of descript ors is considered. This t hreshold
refers t o t he number of valid, unprocessed receive descript ors t he chip has in it s on-
chip buffer. I f t his number drops below PTHRESH, t he algorit hm considers prefet ching
descript ors from host memory. This fet ch does not happen however unless t here are at
least HTHRESH valid descript ors in host memory t o fet ch.
Not e: HTHRESH should be given a non- zero value when ever PTHRESH is used.
WTHRESH cont rols t he writ e back of processed receive descript ors. This t hreshold
refers t o t he number of receive descript ors in t he on- chip buffer which are ready t o be
writ t en back t o host memory. I n t he absence of ext ernal event s ( explicit flushes) , t he
writ e back occurs only aft er at least WTHRESH descript ors are available for writ e back.
Not e: Possible values:
GRAN = 1 ( descript or granularit y) :
PTHRESH = 0.. .31
WTHRESH = 0. .. 31
HTHRESH = 0.. .31
GRAN = 0 ( cache line granularit y) :
PTHRESH = 0.. . 3 ( for 16 descript ors cache line - 256 byt es)
WTHRESH = 0. .. 3
HTHRESH = 0.. .4
Not e: For any WTHRESH value ot her t han zero, t he packet and absolut e t imers must get a
non- zero value for WTHRESH feat ure t o t ake affect .
Not e: Since t he default value for writ e- back t hreshold is one, t he descript ors are normally
writ t en back as soon as one cache line is available. WTHRESH must cont ain a non- zero
value t o t ake advant age of t he writ e- back burst ing capabilit ies of t he MAC.
10.2.1.3.14 Recei ve I nt er r upt Absol ut e Del ay Ti mer - RADV ( 0x 0282C; RW)
I f t he packet delay t imer is used t o coalesce receive int errupt s, it ensures t hat when
receive t raffic abat es, an int errupt is generat ed wit hin a specified int erval of no
receives. During t imes when receive t raffic is cont inuous, it might be necessary t o
ensure t hat no receive remains unnot iced for t oo long an int erval. This regist er might
be used t o ENSURE t hat a receive int errupt occurs at some predefined int erval aft er
t he first packet is received.
When t his t imer is enabled, a separat e absolut e count down t imer is init iat ed upon
successfully receiving each packet t o syst em memory. When t his absolut e t imer
expires, pending receive descript or writ e backs are flushed and a receive t imer
int errupt is generat ed.
15: 0 RW 0x0
Receive Absolut e Delay Timer. Receive absolut e delay t imer measured in
increment s of 1. 024 ms ( 0b = disabled) .

141
Set t ing t his regist er t o zero disables t he absolut e t imer mechanism ( t he RDTR regist er
should be used wit h a value of zero t o cause immediat e int errupt s for all receive
packet s) .
Receive int errupt s due t o a Receive Packet Timer ( RDTR) expirat ion cancels a pending
RADV int errupt . I f enabled, t he RADV count down t imer is reloaded but halt ed, so as t o
avoid generat ion of a spurious second int errupt aft er t he RDTR has been not ed.
10.2.1.3.15 Recei ve Smal l Pack et Det ect I nt er r upt - RSRPD ( 0x 02C00; RW)
10.2.1.3.16 Recei ve ACK I nt er r upt Del ay Regi st er - RAI D ( 0x 02C08; RW)
I f an immediat e ( non- scheduled) int errupt is desired for any received ACK frame, t he
ACK_DELAY should be set t o zero.
10.2.1.3.17 Recei ve Check sum Cont r ol - RXCSUM ( 0x 05000; RW)
The Receive Checksum Cont rol regist er cont rols t he receive checksum offloading
feat ures of t he MAC. The MAC support s t he offloading of t hree receive checksum
calculat ions: t he packet checksum, t he I P header checksum, and t he TCP/ UDP
checksum.
PCSD: The packet checksum and I P I dent ificat ion fields are mut ually exclusive wit h t he
RSS hash. Only one of t he t wo opt ions is report ed in t he Rx descript or. The
RXCSUM. PCSD affect is shown in t he following t able:
11: 0 RW 0x0
SI ZE. I f t he int errupt is enabled any receive packet of size < = SI ZE assert s an
int errupt . SI ZE is specified in byt es and includes t he headers and t he CRC. I t does
not include t he VLAN header in size calculat ion if it is st ripped.
15: 0 RW 0x0
ACK_DELAY. ACK delay t imer measured in increment s of 1. 024 ms. When t he
Receive ACK frame det ect int errupt is enabled in t he I MS regist er, ACK packet s
being received uses a unique delay t imer t o generat e an int errupt . When an ACK
is received, an absolut e t imer loads t o t he value of ACK_DELAY. The int errupt
signal is set only when t he t imer expires. I f anot her ACK packet is received while
t he t imer is count ing down, t he t imer is not reloaded t o ACK_DELAY.
7: 0 RW 0x00 Packet Checksum St art ( PCSS) .
8 RW 1b I P Checksum Offload Enable ( I POFL) .
9 RW 1b TCP/ UDP Checksum Offload Enable ( TUOFL) .
12 RW 0b I P Payload Checksum Enable ( I PPCSE) .
13 RW 0b Packet Checksum Disable ( PCSD) .
14 RW 0b Reserved.
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PCSS I PPCSE: The PCSS and t he I PPCSE cont rol t he packet checksum calculat ion. As
previously not ed, t he packet checksum shares t he same locat ion as t he RSS field. The
packet checksum is report ed in t he receive descript or when t he RXCSUM. PCSD bit is
cleared.
I f RXCSUM. I PPCSE cleared ( t he default value) , t he checksum calculat ion t hat is
report ed in t he Rx packet checksum field is t he unadj ust ed 16 bit ones complement of
t he packet . The packet checksum st art s from t he byt e indicat ed by RXCSUM. PCSS
( zero corresponds t o t he first byt e of t he packet ) , aft er VLAN st ripping if enabled ( by
CTRL. VME) . For example, for an Et hernet I I frame encapsulat ed as an 802. 3ac VLAN
packet and wit h RXCSUM. PCSS set t o 14, t he packet checksum would include t he ent ire
encapsulat ed frame, excluding t he 14- byt e Et hernet header ( DA, SA, t ype/ lengt h) and
t he 4- byt e VLAN t ag. The packet checksum does not include t he Et hernet CRC if t he
RCTL.SECRC bit is set . Soft ware must make t he required offset t ing comput at ion ( t o
back out t he byt es t hat should not have been included and t o include t he pseudo-
header) prior t o comparing t he packet checksum against t he TCP checksum st ored in
t he packet .
I f t he RXCSUM. I PPCSE is set , t he packet checksum is aimed t o accelerat e checksum
calculat ion of fragment ed UDP packet s.
Not e: The PCSS value should not exceed a point er t o I P header st art or else it erroneously
calculat es I P header checksum or TCP/ UDP checksum.
RXCSUM. I POFLD is used t o enable t he I P Checksum offloading feat ure. I f
RXCSUM. I POFLD is set t o one, t he MAC calculat es t he I P checksum and indicat e a pass/
fail indicat ion t o soft ware via t he I P Checksum Error bit ( I PE) in t he ERROR field of t he
receive descript or. Similarly, if RXCSUM. TUOFLD is set t o one, t he MAC calculat es t he
TCP or UDP checksum and indicat e a pass/ fail indicat ion t o soft ware via t he TCP/ UDP
Checksum Error bit ( TCPE) . Similarly, if RFCTL. I Pv6_DI S and RFCTL. I P6Xsum_DI S are
cleared t o zero and RXCSUM. TUOFLD is set t o one, t he MAC calculat es t he TCP or UDP
checksum for I Pv6 packet s. I t t hen indicat es a pass/ fail condit ion in t he TCP/ UDP
Checksum Error bit ( RDESC. TCPE) .
This applies t o checksum offloading only. Support ed frame t ypes:
Et hernet I I
Et hernet SNAP
This regist er should only be init ialized ( writ t en) when t he receiver is not enabled ( only
writ e t his regist er when RCTL. EN = 0) .
RXCSUM. PCSD 0 ( Check sum Enabl e) 1 ( Check sum Di sabl e)
Legacy Rx descript or
( RCTL. DTYP = 00b)
Packet checksum is report ed in t he
Rx descript or
Not support ed
Ext ended or header split Rx
descript or
( RCTL. DTYP = 01b)
Packet checksum and I P
ident ificat ion are report ed in t he Rx
descript or
RSS hash value is report ed in t he Rx
descript or

143
10.2.1.3.18 Recei ve Fi l t er Cont r ol Regi st er - RFCTL ( 0x 05008; RW)
10.2.1.3.19 Mul t i cast Tabl e Ar r ay - MTA[ 31: 0] ( 0x 05200- 0x 0527C; RW)
There is one regist er per 32 bit s of t he Mult icast Address Table for a t ot al of 32
regist ers ( t hus t he MTA[ 31: 0] designat ion) . The size of t he word array depends on t he
number of bit s implement ed in t he mult icast address t able. Soft ware must mask t o t he
desired bit on reads and supply a 32- bit word on writ es.
Not e: All accesses t o t his t able must be 32- bit .
Figure 19 shows t he mult icast lookup algorit hm. The dest inat ion address shown
represent s t he int ernally st ored ordering of t he received DA. Not e t hat Byt e 1 bit 0
indicat ed in t his diagram is t he first on t he wire. The bit s t hat are direct ed t o t he
mult icast t able array in t his diagram mat ch a Mult icast offset in t he CTRL equals 00b.
The complet e mult icast offset opt ions are:
0 RW 0b
iSCSI Disable ( I SCSI _DI S) . Disable t he iSCSI filt ering for header split
funct ionalit y.
5: 1 RW 0x0
iSCSI DWord Count ( I SCSI _DWC) . This field indicat ed t he Dword count of t he
iSCSI header, which is used for packet split mechanism.
6 RW 0b
NFS Writ e Disable ( NFSW_DI S) . Disable filt ering of NFS writ e request headers for
header split funct ionalit y.
7 RW 0b
NFS Read Disable ( NFSR_DI S) . Disable filt ering of NFS read reply headers for
header split funct ionalit y.
9: 8 RW 00b
NFS Version ( NFS_VER) .
00b = NFS version 2.
11b = Reserved for fut ure use.
10 RW 0b Reserved.
11 RW 0b Reserved.
12 RW 0b
ACK Accelerat e Disable ( ACKDI S) . When t his bit is set t he MAC does not
accelerat e int errupt on TCP ACK packet s.
13 RW 0b
ACK dat a Disable ( ACKD_DI S) .
1b = MAC recognizes ACK packet s according t o t he ACK bit in t he TCP header +
No CP dat a
0b = MAC recognizes ACK packet s according t o t he ACK bit only.
This bit is relevant only if t he ACKDI S bit is not set .
14 RW 0b
I P Fragment Split Disable ( I PFRSP_DI S) . When t his bit is set t he header of I P
fragment ed packet s are not set .
15 RW 0b
Ext ended St at us Enable ( EXSTEN) . When t he EXSTEN bit is set or when t he
packet split receive descript or is used, t he MAC writ es t he ext ended st at us t o t he
Rx descript or.
17: 16 0x0 Reserved.
31: 0 RW X
Bit Vect or. Word wide bit vect or specifying 32 bit s in t he mult icast address filt er
t able.
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Fi gur e 19. Mul t i cast Tabl e Ar r ay Al gor i t hm
10.2.1.3.20 Recei ve Addr ess Low - RAL ( 0x 05400 + 8* n ( n= 06) ; RW)
While n is t he exact unicast / mult icast address ent ry and it is equals t o 0, 1, 6.
10.2.1.3.21 Recei ve Addr ess Hi gh - RAH ( 0x 05404 + 8* n ( n= 06) ; RW)
While n is t he exact unicast / mult icast address ent ry and it is equals t o 0, 1, 6.
Mul t i cast Of f set Bi t s Di r ect ed t o t he Mul t i cast Tabl e Ar r ay
47:40 39:32 31:24 23:16 15:8 7:0
pointer[9:5]
Multicast Table Array
32 x 32
(1024 bit vector)
...
...
pointer[4:0]
word
bit
?
Destination Address
MO1:0]
31: 0 RW X
Receive Address Low ( RAL) . The lower 32 bit s of t he 48- bit Et hernet address n
( n= 0, 16) . RAL 0 is loaded from words 0 and 1 in t he NVM.

145
AV det ermines whet her t his address is compared against t he incoming packet . AV is
cleared by a mast er ( soft ware) reset .
ASEL enables t he MAC t o perform special filt ering on receive packet s.
Not e: The first receive address regist er ( RAR0) is also used for exact mat ch pause frame
checking ( DA mat ches t he first regist er) . Therefore RAR0 should always be used t o
st ore t he individual Et hernet MAC address of t he adapt er.
Aft er reset , if t he NVM is present , t he first regist er ( Receive Address regist er 0) is
loaded from t he I A field in t he NVM, it s Address Select field is 00b, and it s Address
Valid field is 1b. I f no NVM is present t he Address Valid field is 0b. The Address Valid
field for all of t he ot her regist ers is zero.
10.2.1.3.22 Shar ed Recei v e Addr ess Low - SHRAL[ n] ( 0x 05438 + 8* n ( n= 03) ; RW)
10.2.1.3.23 Shar ed Recei v e Addr ess Hi gh 02 - SHRAH[ n] ( 0x 0543C + 8* n ( n= 02) ;
RW)
15: 0 RW X
Receive Address High ( RAH) . The upper 16 bit s of t he 48- bit Et hernet address n
( n= 0, 16) . RAH 0 is loaded from word 2 in t he NVM.
17: 16 RW X
Address Select ( ASEL) . Select s how t he address is t o be used. Decoded as follows:
10b = Reserved.
11b = Reserved.
18 RW 0b
VMDq out put index ( VI ND) . Defines t he VMDq out put index associat ed wit h a
receive packet t hat mat ches t his MAC address ( RAH and RAL) .
30: 19 RO 0x0 Reserved. Reads as 0b. I gnored on writ e.
31 RW
See as
follows
Address Valid ( AV) . Cleared aft er mast er reset . I f t he NVM is present , t he Address
Valid field of t he Receive Address Regist er 0 is set t o 1b aft er a soft ware or PCI
reset or NVM read.
This bit is cleared by mast er ( soft ware) reset .
31: 0 RW X
Receive Address Low ( RAL) . The lower 32 bit s of t he 48- bit Et hernet address n
( n= 03) .
15: 0 RW X
( n= 03) .
17: 16 RO 00b
Address Select ( ASEL) . Select s how t he address is t o be used. 00b means t hat it is
used t o decode t he dest inat ion MAC address.
18 RW 0b
31 RW 0b
Address valid ( AV) . When t his bit is set , t he relevant RAL, RAH are valid ( compared
against t he incoming packet ) .
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10.2.1.3.24 Shar ed Recei ve Addr ess Hi gh 3 - SHRAH[ 3] ( 0x 05454; RW)
10.2.1.3.25 Mul t i pl e Recei ve Queues Command r egi st er - MRQC ( 0x 05818; RW)
15: 0 RW X
( n= 03) .
17: 16 RO 00b
Address Select ( ASEL) . Select s how t he address is t o be used. 00b means t hat it is
used t o decode t he dest inat ion MAC address.
18 RW 0b
30 RW 0b
All Nodes Mult icast Address valid ( MAV) . The all nodes mult icast address
( 33: 33: 00: 00: 00: 01) is valid when t his bit is set . Not e t hat 0x33 is t he first byt e
on t he wire.
31 RW 0b
Address valid ( AV) . When t his bit is set t he relevant address 3 is valid ( compared
against t he incoming packet ) .
1: 0 RW 0x00b
Mult iple Receive Queues Enable ( MRxQueue) . Enables support for mult iple receive
queues and defines t he mechanism t hat cont rols queue allocat ion. This field can
be modified only when receive t o host is not enabled ( RCTL. EN = 0) .
00b = Mult iple receive queues are disabled.
01b = Mult iple receive queues as defined by Microsoft * RSS. The RSS field enable
bit s define t he header fields used by t he hash funct ion.
10b = VMDq enable, enables VMDq operat ion as defined in sect ion receive.
queuing for virt ual machine devices.
11b = Reserved.
15: 2 0x0 Reserved.
21: 16 RW 0x0
RSS Field Enable. Each bit , when set , enables a specific field select ion t o be used
by t he hash funct ion. Several bit s can be set at t he same t ime.
Bit [ 16] = Enable TcpI Pv4 hash funct ion.
Bit [ 17] = Enable I Pv4 hash funct ion.
Bit [ 18] = Enable TcpI Pv6 hash funct ion.
Bit [ 19] = Enable I Pv6Ex hash funct ion.
Bit [ 20] = Enable I Pv6 hash funct ion.
Bit [ 21] = Reserved.

147
10.2.1.3.26 Redi r ect i on Tabl e - RETA ( 0x 05C00 + 4* n ( n= 031) ; RW)
The redirect ion t able is a 32 ent ry t able. Each ent ry is composed of four t ags each 8-
bit s wide. Only t he first or last six bit s of each t ag are used ( five bit s for t he CPU index
and 1 bit for queue index) .
Not e: RETA cannot be read when RSS is enabled.
10.2.1.3.27 Random Key Regi st er - RSSRK ( 0x 05C80 + 4* n ( n= 09) ; RW)
The RSS Random Key regist er st ores a 40- byt e key ( 10 Dword ent ry t able) used by t he
RSS hash funct ion.
Of f set 31: 24 23: 16 15: 8 7: 0
0x05C00 + n* 4 Tag 4* n+ 3 Tag 4* n+ 2 Tag 4* n+ 1 Tag 4* n
4: 0 RW X CPU I NDX 0. CPU index for Tag 4* n ( n= 0, 1, 31) .
6: 5 RO X Reserved.
7 RW X QUE I NDX 0. Queue I ndex for Tag 4* n ( n= 0, 1, 31) .
12: 8 RW X CPU I NDX 1. CPU index for Tag 4* n+ 1 ( n= 0, 1, 31) .
15 RW X QUE I NDX 1. Queue I ndex for Tag 4* n+ 1 ( n= 0, 1, 31) .
7: 0 RW 0x0 K0. Byt e n* 4 of t he RSS random key ( n= 0, 1, 9) .
15: 8 RW 0x0 K1. Byt e n* 4+ 1 of t he RSS random key ( n= 0, 1, 9) .
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10. 2. 1. 4 Tr ansmi t Regi st er Descr i pt i ons
10.2.1.4.1 Tr ansmi t Cont r ol Regi st er - TCTL ( 0x 00400; RW)
Two fields deserve special ment ion: CT and COLD. Soft ware might choose t o abort
packet t ransmission in less t han t he Et hernet mandat ed 16 collisions. For t his reason,
hardware provides CT.
0 RW 0b
I P I dent ificat ion 15 bit ( I PI D15) .
When set t o 1b, t he I P I dent ificat ion field is increment ed and wrapped around on
15- bit base. For example, if I P I D is equal t o 0x7FFF t hen t he next value is
0x0000; if I P I D is equal t o 0xFFFF t hen t he next value is 0x8000.
When set t o 0b, t he I P I dent ificat ion field is increment ed and wrapped around on
16- bit base. I n t his case, t he value following 0x7FFF is 0x8000, and t he value
following 0xFFFF is 0x0000.
The purpose of t his feat ure is t o enable t he soft ware t o manage t wo sub- groups of
connect ions.
1 RW 0b
Enable ( EN) . The t ransmit t er is enabled when t his bit is set t o 1b. Writ ing t his bit
t o 0b st ops t ransmission aft er any in- progress packet s are sent . Dat a remains in
t he t ransmit FI FO unt il t he MAC is re- enabled. Soft ware should combine t his wit h
reset if t he packet s in t he FI FO should be flushed.
2 RO 0b Reserved. Reads as 0b. Should be writ t en t o 0b for fut ure compat ibilit y.
3 RW 1b
Pad Short Packet s ( PSP) . Wit h valid dat a, NOT padding symbols.
0b = Do not pad
1b = Pad.
Padding makes t he packet 64 byt es. This is not t he same as t he minimum collision
dist ance.
I f padding of short packet s is allowed, t he value in Tx descript or lengt h field
should be not less t han 17 byt es.
11: 4 RW 0x0F
Collision Threshold ( CT) . This det ermines t he number of at t empt s at re-
t ransmission prior t o giving up on t he packet ( not including t he first t ransmission
at t empt ) . While t his can be varied, it should be set t o a value of 15 in order t o
comply wit h t he I EEE specificat ion requiring a t ot al of 16 at t empt s. The Et hernet
back- off algorit hm is implement ed and clamps t o t he maximum number of slot -
t imes aft er 10 ret ries. This field only has meaning when in half- duplex operat ion.
21: 12 RW 0x3F
Collision Dist ance ( COLD) . Specifies t he minimum number of byt e t imes t hat must
elapse for proper CSMA/ CD operat ion. Packet s are padded wit h special symbols,
not valid dat a byt es. Hardware checks and pads t o t his value plus one byt e even
in full- duplex operat ion. Default value is 64- byt e t o 512- byt e t imes.
22 RW/ V 0b
Soft ware XOFF Transmission ( SWXOFF) . When set t o a 1b, t he MAC schedules t he
t ransmission of an XOFF ( PAUSE) frame using t he current value of t he PAUSE
t imer. This bit self clears upon t ransmission of t he XOFF frame.
23 RW 0b Reserved.
24 RW 0b
Re- t ransmit on Lat e Collision ( RTLC) . Enables t he MAC t o re- t ransmit on a lat e
collision event .
27: 25 RW 0x0 Reserved. Used t o be UNORTX and TXDSCMT in predecessors.
28 1b Reserved.
30: 29 RW 01b
Read Request Threshold ( RRTHRESH) . These bit s define t he t hreshold size for t he
int ermediat e buffer t o det ermine when t o send t he read command t o t he packet
buffer. Threshold is defined as follow:
RRTHRESH 00b Threshold 2 lines of 16 byt es.
RRTHRESH 11b Threshold No t hreshold ( t ransfer dat a aft er all of t he request is
in t he RFI FO) .
31 RO 0b Reserved. Reads as 0. Should be writ t en t o 0 for fut ure compat ibilit y.

149
Wire speeds of 1000 Mb/ s result in a very short collision radius wit h t radit ional
minimum packet sizes. COLD specifies t he minimum number of byt es in t he packet t o
sat isfy t he desired collision dist ance. I t is import ant t o not e t hat t he result ing packet
has special charact ers appended t o t he end. These are NOT regular dat a charact ers.
Hardware st rips special charact ers for packet s t hat go from 1000 Mb/ s environment s t o
100 Mb/ s environment s. Not e t hat hardware evaluat es t his field against t he packet size
in full duplex as well.
Not e: While 802. 3x flow cont rol is only defined during full- duplex operat ion, t he sending of
PAUSE frames via t he SWXOFF bit is not gat ed by t he duplex set t ings wit hin t he MAC.
Soft ware should not writ e a 1b t o t his bit while t he MAC is configured for half- duplex
operat ion.
RTLC configures t he MAC t o perform re- t ransmission of packet s when a lat e collision is
det ect ed. Not e t hat t he collision window is speed dependent : 64 byt es for
10/ 100 Mb/ s and 512 byt es for 1000 Mb/ s operat ion. I f a lat e collision is det ect ed when
t his bit is disabled, t he t ransmit funct ion assumes t he packet is successfully
t ransmit t ed. This bit is ignored in full- duplex mode.
10.2.1.4.2 Tr ansmi t I PG Regi st er - TI PG ( 0x 00410; RW)
This regist er cont rols t he I nt er Packet Gap ( I PG) t imer. I PGT specifies t he I PG lengt h for
back- t o- back t ransmissions in bot h full and half duplex. Not e t hat an offset of 4- byt e
t imes is added t o t he programmed value t o det ermine t he t ot al I PG. Therefore, a value
of eight is recommended t o achieve a 12- byt e t ime I PG.
I PGR1 specifies t he port ion of t he I PG in which t he t ransmit t er defers t o receive event s.
This should be set t o 2/ 3 of t he t ot al effect ive I PG, or eight .
I PGR specifies t he t ot al I PG t ime for non back- t o- back t ransmissions ( t ransmission
following deferral) in half duplex.
An offset of 5- byt e t imes is added t o t he programmed value t o det ermine t he t ot al I PG
aft er a defer event . Therefore, a value of seven is recommended t o achieve a 12- byt e
t ime effect ive I PG for t his case. Not e t he I PGR should never be set t o a value great er
t han I PGT. I f I PGR is set t o a value equal t o or larger t han I PGT, it overrides t he I PGT
I PG set t ing in half duplex, result ing in int er packet gaps t hat are larger t han int ended
by I PGT in t hat case. Full duplex is unaffect ed by t his, and always relies on I PGT only.
I n summary, t he recommended TI PG value t o achieve 802. 3 compliant minimum
t ransmit I PG values in full and half duplex is 0x00702008.
9: 0 RW 0x8
I PG Transmit Time ( I PGT) . Specifies t he I PG lengt h for back- t o- back t ransmissions
equal t o [ ( I PGT+ 4) x 8] bit t ime.
19: 10 RW 0x8
I PG Receive Time 1 ( I PGR1) . Specifies t he defer I PG part 1 ( during which carrier
sense is monit ored) . Equal t o ( I PGR1 x 8) when DJHDX= 0 and equals t o
( I PGR1+ 2) x 8 when DJHDX= 1.
29: 20 RW 0x9
I PG Receive Time 2 ( I PGR2) . Specifies t he defer I PG. Equal t o ( I PGR2+ 3) x 8
when DJHDX= 0 and equal t o ( I PGR2+ 5) x 8 when DJHDX= 1.
31: 30 RO 00b Reserved. Reads as 0b. Should be writ t en t o 0b for fut ure compat ibilit y.
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10.2.1.4.3 Adapt i ve I FS Thr ot t l e - AI T ( 0x 00458; RW)
Adapt ive I FS t hrot t les back- t o- back t ransmissions in t he t ransmit packet buffer and
delays t heir t ransfer t o t he CSMA/ CD t ransmit funct ion, and t hus can be used t o delay
t he t ransmission of back- t o- back packet s on t he wire. Normally, t his regist er should be
set t o zero. However, if addit ional delay is desired bet ween back- t o- back t ransmit s,
t hen t his regist er might be set wit h a value great er t han zero.
The Adapt ive I FS field provides a similar funct ion t o t he I PGT field in t he TI PG regist er
( see Sect ion 10.2. 1. 5.2) . However, it only affect s t he init ial t ransmission t iming, not re-
t ransmission t iming.
Not e: I f t he value of t he Adapt iveI FS field is less t han t he I PGTransmit Time field in t he
Transmit I PG regist ers t hen it has no effect , as t he chip select s t he maximum of t he t wo
values.
10.2.1.4.4 Tr ansmi t Descr i pt or Base Addr ess Low - TDBAL ( 0x 03800 + n* 0x 100[ n= 0. . 1] ;
RW)
This regist er cont ains t he lower bit s of t he 64- bit descript or base address. The lower
four bit s are ignored. The t ransmit descript or base address must point t o a 16- byt e
aligned block of dat a.
10.2.1.4.5 Tr ansmi t Descr i pt or Base Addr ess Hi gh - TDBAH ( 0x 03804 +
n* 0x 100[ n= 0..1] ; RW)
This regist er cont ains t he upper 32 bit s of t he 64- bit descript or base address.
15: 0 RW 0x0000 Adapt ive I FS value ( AI FS) . This value is in unit s of 8 ns.
31: 16 RO 0x0000 Reserved. This field should be writ t en wit h 0b.
3: 0 RO 0x0 Reserved. I gnored on writ es. Ret urns 0b on reads
31: 4 RW X Transmit Descript or Base Address Low ( TDBAL)
31: 0 RW X Transmit Descript or Base Address [ 63: 32] ( TDBAH) .

151
10.2.1.4.6 Tr ansmi t Descr i pt or Lengt h - TDLEN ( 0x 03808 ; RW)
This regist er cont ains t he descript or lengt h and must be 128- byt e aligned.
Not e: The descript or ring must be equal t o or larger t han eight descript ors.
10.2.1.4.7 Tr ansmi t Descr i pt or Head - TDH ( 0x 03810; RW)
This regist er cont ains t he head point er for t he t ransmit descript or ring. I t point s t o a
16- byt e dat um. Hardware cont rols t his point er. The only t ime t hat soft ware should
writ e t o t his regist er is aft er a reset ( hardware reset or CTRL. SWRST) and before
enabling t he t ransmit funct ion ( TCTL.EN) . I f soft ware were t o writ e t o t his regist er
while t he t ransmit funct ion was enabled, t he on- chip descript or buffers might be
invalidat ed and hardware could be become confused.
10.2.1.4.8 Tr ansmi t Descr i pt or Tai l - TDT ( 0x 03818; RW)
Not e: This regist er cont ains t he t ail point er for t he t ransmit descript or ring. I t point s t o a 16-
byt e dat um. Soft ware writ es t he t ail point er t o add more descript ors t o t he t ransmit
ready queue. Hardware at t empt s t o t ransmit all packet s referenced by descript ors
bet ween head and t ail.
10.2.1.4.9 Tr ansmi t I nt er r upt Del ay Val ue - TI DV ( 0x 03820; RW)
This regist er is used t o delay int errupt not ificat ion for t ransmit operat ions by coalescing
int errupt s for mult iple t ransmit t ed buffers. Delaying int errupt not ificat ion helps
maximize t he amount of t ransmit buffers reclaimed by a single int errupt . This feat ure
ONLY applies t o t ransmit descript or operat ions where ( a) int errupt - based report ing is
request ed ( RS set ) and ( b) t he use of t he t imer funct ion is request ed ( I DE is set ) .
6: 0 RO 0x0 Reserved. I gnore on writ e. Reads back as 0b.
19: 7 RW 0x0 Descript or Lengt h ( LEN) .
31: 20 RO 0x0 Reserved. Reads as 0b. Should be writ t en t o 0b.
15: 0 RW/ V 0x0 Transmit Descript or Head ( TDH) .
15: 0 RW 0x0 Transmit Descript or Tail ( TDT) .
31: 16 RO 0x0 Reserved. Reads as 0b. Should be writ t en t o 0 for fut ure compat ibilit y.
15: 0 RW 0x0
I nt errupt Delay Value ( I DV) . Count s in unit s of 1. 024 ms. A value of zero is not
allowed.
31 WO 0b Flush Part ial Descript or Block ( FPD) . when set t o 1b; ignored ot herwise. Reads 0b.
152
I nt el
This feat ure operat es by init iat ing a count down t imer upon successfully t ransmit t ing
t he buffer. I f a subsequent t ransmit delayed- int errupt is scheduled BEFORE t he t imer
expires, t he t imer is re- init ialized t o t he programmed value and rest art s it s
count down. When t he t imer expires, a t ransmit - complet e int errupt ( I CR. TXDW) is
generat ed.
Set t ing t he value t o zero is not allowed. I f an immediat e ( non- scheduled) int errupt is
desired for any t ransmit descript or, t he descript or I DE should be set t o zero.
The occurrence of eit her an immediat e ( non- scheduled) or absolut e t ransmit t imer
int errupt halt s t he TI DV t imer and eliminat e any spurious second int errupt s.
Transmit int errupt s due t o a Transmit Absolut e Timer ( TADV) expirat ion or an
immediat e int errupt ( RS/ RSP= 1b, I DE= 0b) cancels a pending TI DV int errupt . The TI DV
count down t imer is reloaded but halt ed, t hough it might be rest art ed by a processing a
subsequent t ransmit descript or.
Writ ing t his regist er wit h FPD set init iat es an immediat e expirat ion of t he t imer, causing
a writ e back of any consumed t ransmit descript ors pending writ e back, and result s in a
t ransmit t imer int errupt in t he I CR.
Not e: FPD is self- clearing.

153
10.2.1.4.10 Tr ansmi t Descr i pt or Cont r ol - TXDCTL ( 0x 03828; RW)
Not e: This regist er was not fully validat ed. Soft ware should set it t o 0x0000 during nominal
operat ion.
This regist er cont rols t he fet ching and writ e back of t ransmit descript ors. The t hree
t hreshold values are used t o det ermine when descript ors is read from and writ t en t o
host memory. The values might be in unit s of cache lines or descript ors ( each
descript or is 16 byt es) based on t he GRAN flag.
Not e: When GRAN = one all descript ors is writ t en back ( even if not request ed) .
PTHRESH is used t o cont rol when a prefet ch of descript ors is considered. This t hreshold
refers t o t he number of valid, unprocessed t ransmit descript ors t he chip has in it s on-
chip buffer. I f t his number drops below PTHRESH, t he algorit hm considers prefet ching
descript ors from host memory. This fet ch does not happen however, unless t here are at
least HTHRESH valid descript ors in host memory t o fet ch.
Not e: HTHRESH should be given a non- zero value each t ime PTHRESH is used.
WTHRESH cont rols t he writ e back of processed t ransmit descript ors. This t hreshold
refers t o t he number of t ransmit descript ors in t he on- chip buffer which are ready t o be
writ t en back t o host memory. I n t he absence of ext ernal event s ( explicit flushes) , t he
writ e back occurs only aft er at least WTHRESH descript ors are available for writ e back.
Possible values:
GRAN = 1 ( descript or granularit y) :
PTHRESH = 0. .31
WTHRESH = 0. . 31
HTHRESH = 0. .31
GRAN = 0 ( cacheline granularit y) :
PTHRESH = 0. . 3 ( for 16 descript ors cacheline - 256 byt es)
5: 0 RW 0x00 Prefet ch Threshold ( PTHRESH) .
13: 8 RW 0x00 Host Threshold ( HTHRESH) .
21: 16 RW 0x00 Writ e- Back Threshold ( WTHRESH) .
24 RW 0x0
Granularit y ( GRAN) . Unit s for t he t hresholds in t his regist er.
0b = Cache lines.
1b = Descript ors.
31: 25 RW 0x0
Transmit descript or Low Threshold ( LWTHRESH) .
I nt errupt assert ed when t he number of descript ors pending service in t he t ransmit
descript or queue ( processing dist ance from t he TDT) drops below t his t hreshold.
154
I nt el
WTHRESH = 0. .3
HTHRESH = 0.. 4
Not e: For any WTHRESH value ot her t han zero - The packet and absolut e t imers must get a
non zero value for t he WTHRESH feat ure t o t ake affect .
Not e: Since t he default value for writ e- back t hreshold is zero, descript ors are normally
writ t en back as soon as t hey are processed. WTHRESH must be writ t en t o a non- zero
value t o t ake advant age of t he writ e- back burst ing capabilit ies of t he MAC. I f t he
WTHRESH is writ t en t o a non- zero value t hen all of t he descript ors are writ t en back
consecut ively no mat t er t he set t ing of t he RS bit .
Since writ e back of t ransmit descript ors is opt ional ( under t he cont rol of RS bit in t he
descript or) , not all processed descript ors are count ed wit h respect t o WTHRESH.
Descript ors st art accumulat ing aft er a descript or wit h RS is set . Furt hermore, wit h
t ransmit descript or burst ing enabled, all of t he descript ors are writ t en back
consecut ively no mat t er t he set t ing of t he RS bit .
LWTHRESH cont rols t he number of prefet ched t ransmit descript ors at which a t ransmit
descript or- low int errupt ( I CR. TXD_LOW) is report ed. This might enable soft ware t o
operat e more efficient ly by maint aining a cont inuous addit ion of t ransmit work,
int errupt ing only when hardware nears complet ion of all submit t ed work. LWTHRESH
specifies a mult iple of eight descript ors. An int errupt is assert ed when t he number of
descript ors available t ransit ions from ( t hreshold level= 8* LWTHRESH) + 1 ( t hreshold
level= 8* LWTHRESH) . Set t ing t his value t o zero disables t his feat ure.
10.2.1.4.11 Tr ansmi t Absol ut e I nt er r upt Del ay Val ue- TADV ( 0x 0382C; RW)
The t ransmit int errupt delay t imer ( TI DV) might be used t o coalesce t ransmit
int errupt s. However, it might be necessary t o ensure t hat no complet ed t ransmit
remains unnot iced for t oo long an int erval in order ensure t imely release of t ransmit
buffers. This regist er might be used t o ENSURE t hat a t ransmit int errupt occurs at
some predefined int erval aft er a t ransmit is complet ed. Like t he delayed- t ransmit t imer,
t he absolut e t ransmit t imer ONLY applies t o t ransmit descript or operat ions where ( a)
int errupt - based report ing is request ed ( RS set ) and ( b) t he use of t he t imer funct ion is
request ed ( I DE is set ) .
This feat ure operat es by init iat ing a count down t imer upon successfully t ransmit t ing
t he buffer. When t he t imer expires, a t ransmit - complet e int errupt ( I CR. TXDW) is
generat ed. The occurrence of eit her an immediat e ( non- scheduled) or delayed t ransmit
t imer ( TI DV) expirat ion int errupt halt s t he TADV t imer and eliminat e any spurious
second int errupt s.
Set t ing t he value t o zero disables t he t ransmit absolut e delay funct ion. I f an immediat e
( non- scheduled) int errupt is desired for any t ransmit descript or, t he descript or I DE
should be set t o zero.
15: 0 RW 0x0 I nt errupt Delay Value ( I DV) . Count s in unit s of 1. 024 ms. ( 0b = disabled)

155
10. 2. 1. 5 Pow er Management Regi st er Descr i pt i ons
10.2.1.5.1 Wak e Up Cont r ol Regi st er - WUC ( 0x 05800; RW)
The PME_St at us bit s are cleared in t he following condit ions:
I f t here is VAUX, t hen t he PME St at us bit s should be cleared by:
LAN_RST# or PCI reset
Explicit soft ware clear
I f t here is NO VAUX, t hen t he PME St at us bit s should be cleared by:
LAN_RST# or PCI reset
PCI reset de- assert ion
Explicit soft ware clear
0
RW/
SN
0b
Advance Power Management Enable ( APME) .
1b = APM Wakeup is enabled.
0b = APM Wakeup is disabled.
Loaded from t he NVM word 0x0A.
1 RW/ V 0b
PME_En. This read/ writ e bit is used by t he driver t o access t he PME_En bit of t he
Power Management Cont rol / St at us Regist er ( PMCSR) wit hout writ ing t o PCI
configurat ion space.
2 RWC 0b
PME_St at us. This bit is set when t he MAC receives a wakeup event . I t is t he same
as t he PME_St at us bit in t he PMCSR. Writ ing a 1b t o t his bit clears it , and also
clears t he PME_St at us bit in t he PMCSR.
3 RW 1b
Assert PME On APM Wakeup ( APMPME) . I f set t o 1b, t he MAC set s t he PMCSR and
assert s Host _Wake when APM wake up is enabled and t he MAC receives a
mat ching magic packet .
4
RW/
SN
0b
Link St at us Change Wake Enable ( LSCWE) . Enables wake on link st at us change as
part of APM wake capabilit ies.
5
RW/
SN
0b
Link St at us Change Wake Override ( LSCWO) . I f set t o 1b, wake on link st at us
change does not depend on t he LNKC bit in t he Wake Up Filt er Cont rol ( WUFC)
regist er. I nst ead, it is det ermined by t he APM set t ings in t he WUC regist er.
8
RW/
SN
0b
Phy_Wake. This bit indicat es if t he 82578 connect ed t o t he MAC support s wake up.
This bit is loaded from NVM word 0x13, bit 8.
29: 9 RO 0x0 Reserved. Reads as 0.
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10.2.1.5.2 Wak e Up Fi l t er Cont r ol Regi st er - WUFC ( 0x 05808; RW)
This regist er is used t o enable each of t he predefined and flexible filt ers for wake up
support . A value of 1b means t he filt er is t urned on, and a value of 0b means t he filt er
is t urned off.
10.2.1.5.3 Wak e Up St at us Regi st er - WUS ( 0x 05810; RW)
0 RW 0b LNKC. Link St at us Change Wake Up Enable.
1 RW 0b MAG. Magic Packet Wake Up Enable.
2 RW 0b EX. Direct ed Exact Wake Up Enable.
3 RW 0b MC. Direct ed Mult icast Wake Up Enable.
4 RW 0b BC. Broadcast Wake Up Enable.
5 RW 0b I Pv4. Request Packet Wake Up Enable.
6 RW 0b I PV4. Direct ed I Pv4 Packet Wake Up Enable.
7 RW 0b I PV6. Direct ed I Pv6 Packet Wake Up Enable.
15 RW 0b
NoTCO. I gnore TCO Packet s for TCO. I f t he NoTCO bit is set , t hen any packet t hat
passes t he manageabilit y packet filt ering does not cause a wake up event even if
it passes one of t he wake up filt ers.
16 RW 0b FLX0. Flexible Filt er 0 Enable.
0 RW 0b LNKC. Link St at us Changed.
1 RW 0b MAG. Magic Packet Received.
2 RW 0b
EX. Direct ed Exact Packet Received. The packet s address mat ched one of t he
seven pre- programmed exact values in t he Receive Address regist ers.
3 RW 0b
MC. Direct ed Mult icast Packet Received. The packet was a mult icast packet t hat
hashed t o a value corresponding t o a one bit in t he Mult icast Table Array.
4 RW 0b BC. Broadcast Packet Received.
5 RW 0b I Pv4. Request Packet Received.
6 RW 0b I PV4. Direct ed I Pv4 Packet Received.
7 RW 0b I PV6. Direct ed I Pv6 Packet Received.
15: 8 RO 0x0 Reserved. Read as 0b.
16 RW 0b FLX0. Flexible Filt er 0 Mat ch.

157
This regist er is used t o record st at ist ics about all wakeup packet s received. A packet
t hat mat ches mult iple crit eria might set mult iple bit s. Writ ing a 1b t o any bit clears t hat
bit .
This regist er is not cleared when PCI _RST_N is assert ed. I t is only cleared when
LAN_RST# is de- assert ed or when cleared by t he driver.
10.2.1.5.4 I P Addr ess Val i d - I PAV ( 0x 5838; RW)
The I P address valid indicat es whet her t he I P addresses in t he I P address t able are
valid:
10.2.1.5.5 I Pv4 Addr ess Tabl e - I P4AT ( 0x 05840 + 8* n ( n= 13) ; RW)
The I Pv4 address t able is used t o st ore t he t hree I Pv4 addresses for I Pv4 request
packet and direct ed I Pv4 packet wake up. I t is a 4- ent ry t able wit h t he following
format :
The regist er at address 0x5840 ( n= 0) was used in predecessors and reserved in t he
I nt el
5 Series Express Chipset .

10.2.1.5.6 I Pv6 Addr ess Tabl e - I P6AT ( 0x 05880 + 4* n ( n= 03) ; RW)
The I Pv6 address t able is used t o st ore t he I Pv6 address for direct ed I Pv6 packet wake
up and manageabilit y t raffic filt ering. The I P6AT has t he following format :
0 RO 0b Reserved.
1 RW 0b V41. I Pv4 Address 1 Valid.
16 RW 0b V60. I Pv6 Address Valid.
31: 0 RW X I PADD. I P Address n ( n= 1, 2, 3) .
31: 0 RW X
I PV6 Address. I Pv6 Address byt es n* 4n* 4+ 3 ( n= 0, 1, 2, 3) while byt e 0 is first
on t he wire and byt e 15 is last .
158
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10.2.1.5.7 Fl ex i bl e Fi l t er Lengt h Tabl e - FFLT ( 0x 05F00 + 8* n ( n= 05) ; RW)
There are six flexible filt ers Lengt hs. The flexible filt er lengt h t able st ores t he minimum
packet lengt hs required t o pass each of t he flexible filt ers. Any packet s t hat are short er
t han t he programmed lengt h does not pass t hat filt er. Each flexible filt er considers a
packet t hat does not have any mismat ches up t o t hat point t o have passed t he flexible
filt er when it reaches t he required lengt h. I t does not check any byt es past t hat point .
All reserved fields read as 0bs and ignore writ es.
Not e: Before writ ing t o t he flexible filt er lengt h t able t he driver must first disable t he flexible
filt ers by writ ing 0bs t o t he Flexible Filt er Enable bit s of t he Wake Up Filt er Cont rol
10.2.1.5.8 Fl ex i bl e Fi l t er Mask Tabl e - FFMT ( 0x 09000 + 8* n ( n= 0127) ; RW)
There are 128 mask ent ries. The flexible filt er mask and t able is used t o st ore t he four
1- bit masks for each of t he first 128 dat a byt es in a packet , one for each flexible filt er.
I f t he mask bit is 1b, t he corresponding flexible filt er compares t he incoming dat a byt e
at t he index of t he mask bit t o t he dat a byt e st ored in t he flexible filt er value t able.
Not e: The t able is organized t o permit expansion t o eight ( or more) filt ers and 256 byt es in a
fut ure product wit hout changing t he address map.
Not e: Before writ ing t o t he flexible filt er mask t able t he driver must first disable t he flexible
10.2.1.5.9 Fl ex i bl e Fi l t er Val ue Tabl e - FFVT ( 0x 09800 + 8* n ( n= 0127) ; RW)
1b, t he flexible filt er compares t he incoming dat a byt e t o t he values st ored in t his t able.
10: 0 RW X LEN. Minimum Lengt h for Flexible Filt er n.
0 RW X Mask 0. Mask for filt er 0 byt e n ( n= 0, 1127) .
31: RO X Reserved.
7: 0 RW X Value 0. Value of filt er 0 byt e n ( n= 0, 1127) .

159
Before writ ing t o t he flexible filt er value t able t he driver must first disable t he flexible
10.2.1.5.10 Fl ex i bl e Fi l t er Val ue Tabl e - FFVT2 ( 0x 09804 + 8* n ( n= 0127) ; RW)
1b, t he flexible filt er compares t he incoming dat a byt e t o t he values st ored in t his t able.
Not e: Before writ ing t o t he flexible filt er value t able t he driver must first disable t he flexible
160
I nt el
82578 GbE PHYEl ect r i cal and Ti mi ng Speci f i cat i ons
161
11. 0 El ect r i cal and Ti mi ng Speci f i cat i ons
This sect ion describes t he 82578s recommended operat ing condit ions, power delivery,
DC elect rical charact erist ics, power sequencing and reset requirement s, PCI e
specificat ions, reference clock, and packaging informat ion.
11.2 Oper at i ng Condi t i ons
11.2. 1 Absol ut e Max i mum Rat i ngs
Not es:
1. Rat ings in t his t able are t hose beyond which permanent device damage is likely t o occur. These values
should not be used as t he limit s for normal device operat ion. Exposure t o absolut e maximum rat ing
condit ions for ext ended periods might affect device reliabilit y.
2. Recommended operat ion condit ions require accuracy of power supply of + / - 5% relat ive t o t he nominal
volt age.
3. Maximum rat ings are referenced t o ground ( VSS) .
Sy mbol Par amet er Mi n Max Uni t s
T
case
Case Temperat ure Under Bias 0 85 C
T
st orage
St orage Temperat ure Range - 45 125 C
Vi/ Vo
3. 3 Vdc I / O Volt age
2. 5 Vdc I / O Volt age
1. 2 Analog Vdc I / O Volt age
1. 8 Analog Vdc Volt age
Vss - 0.5
Vss - 0.4
Vss - 0.2
Vss - 0.3
4. 6
3. 5
1. 68
2. 52
Vdc
VCC 3. 3 Vdc Periphery DC Supply Volt age Vss - 0. 5 4. 6 Vdc
VCC 2. 5 Vdc Core DC Supply Volt age Vss - 0. 4 3. 5 Vdc
VCC1p8 1. 8 Vdc Supply Volt age Vss - 0. 3 2. 52 Vdc
VCC1p2 1. 2 Vdc Supply Volt age Vss - 0. 2 1. 68 Vdc
162
El ect r i cal and Ti mi ng Speci f i cat i ons82578 GbE PHY
11. 2. 2 Recommended Oper at i ng Condi t i ons
11. 2. 3 ESD Speci f i cat i ons
11.3 Pow er Del i ver y
The following power opt ions are available for t he 82578:
1. Connect ing t he 82578 t o t wo ext ernal power supplies wit h nominal volt ages of
3. 3 Vdc and 1. 2 Vdc.
2. Powering t he 82578 wit h an ext ernal 3.3 Vdc supply and using an int ernal power
regulat or as follows:
Regulat or mode:
2. 5 Vdc is generat ed from 3. 3 Vdc using an int ernal regulat or.
1. 8 Vdc is generat ed from 3. 3 Vdc using an int ernal regulat or for cent ral t ap
volt age only.
1. 2 Vdc is generat ed ext ernally using an ext ernal PnP.
Sy mbol Par amet er Mi n Max Uni t s
Ta
Operat ing Temperat ure Range
Commercial
( Ambient ; 0 CFS airflow)
0 85
1
1. For normal device operat ion, adhere t o t he limit s in t his t able. Sust ained operat ions of a device at
condit ions exceeding t hese values, even if t hey are wit hin t he absolut e maximum rat ing limit s, can
result in permanent device damage or impaired device reliabilit y. Device funct ionalit y t o st at ed
Vdc and Vac limit s is not guarant eed if condit ions exceed recommended operat ing condit ions.
C
Ti t l e Speci f i cat i on
Human body model JESD22-A114
Charged device model JESD22- C101
Machine model JESD22-A115
Cable discharge event N/ A
163
11. 3. 1 Vol t age Regul at or Pow er Suppl y Speci f i cat i ons
Not e: These requirement s apply when using an ext ernal power source.
11. 3. 1. 1 3.3 Vdc Rai l
11. 3. 1. 2 1.8 Vdc Rai l
Ti t l e Descr i pt i on Mi n Max Uni t s
Rise Time Time from 10% t o 90% mark 0. 1 100 mS
Monot onicit y Volt age dip allowed in ramp N/ A 0 mV
Slope
Ramp rat e at any given t ime bet ween 10% and
90%
Min: 0. 8* V( min) / Rise t ime ( max)
Max: 0. 8* V( max) / Rise t ime ( min)
24 28800 V/ S
Operat ional Range Volt age range for normal operat ing condit ions 3 3. 6 V
Ripple
Maximum volt age ripple ( peak t o peak) @
20 MHz BW
N/ A 70 mV
Overshoot Maximum overshoot allowed N/ A 100 mV
Operat ional Range Volt age range for normal operat ing condit ions 1. 71 2. 25 Vdc
Ripple
20 MHz BW
N/ A 50 mV
164
11. 3. 1. 3 1. 2 Vdc Rai l
11. 3. 1. 4 1. 2 Vdc PNP Regul at or Pow er Del i v er y Schemat i c
Not e: See Figure 4 for t he 1. 2 Vdc PNP regulat or power delivery schemat ic.
11. 3. 1. 5 PNP Speci f i cat i ons
Not e: Maximum current of 1. 2 Vdc is less t hen 350 mA.
Rise Time Time from 10% t o 90% mark 0. 1 40 mS
Monot onicit y Volt age dip allowed in ramp N/ A 0 mV
Slope
Ramp rat e at any given t ime bet ween 10%
and 90%
Min: 0. 8* V( min) / Rise t ime ( max)
Max: 0. 8* V( max) / Rise t ime ( min)
7. 6 8400 V/ S
Operat ional Range
Volt age range for normal operat ing
condit ions
1. 14 1. 26 Vdc
Ripple
20 MHz BW
N/ A 50 mV
Overshoot Maximum overshoot allowed N/ A 100 mV
Decoupling Capacit ance Capacit ance range 10 30 F
Capacit ance ESR
Equivalent series resist ance of out put
capacit ance
5 50 m
VCBO 20 Vdc
VCEO 20 Vdc
I C( max) 1 A
I C( peak) 1. 2 A
Pt ot
Minimum t ot al dissipat ed power @ 25 C ambient
t emperat ure
1. 5 W
hFE DC current gain @ Vce = - 10 Vdc, I c = 500 mA 85
hfe AC current gain @ I c = 50 mA VCE = - 10 Vdc, f = 20 MHz 2. 5
Cc Collect or capacit ance @ VCB= - 5 Vdc, f = 1 MHz 50 pF
fT
Transit ion frequency @ I c = 10 mA, VCE = - 5 Vdc, f =
100 MHz
40 MHz
Recommended t ransist or BCP69
I b 50 A 4 mA
165
11. 3. 1. 6 Ex t er nal Component s
11.3. 2 Pow er On/ Of f Sequence
The 82578 does not require a power on or power off sequence bet ween t he 3.3 Vdc and
1. 2 Vdc power rails.
Tabl e 85. Pow er - On Reset Det ect i on Thr eshol ds
11.4 I / O DC/ AC Par amet er s
11.4. 1 3.3 Vdc DC/ I O
Not e: All t he 3.3 Vdc I / Os are open- drain t ypes.
Descr i pt i on Name Qt y
El ect r i cal
Char act er i st i cs
Recommended
Component s
Pk g
Sour ce Par t #
1. 2 Vdc
Regulat or
PNP
Transist or
Q1 1
Minimum HFE ( Vdc Gain) 85
@ Vce = 2.5 Vdc I= 0.35A
T = 25 C
Rja<60 CW
Philips,
OnSemi,
I nfineon
BCP69 SOT223
Sy mbol Par amet er
Speci f i cat i ons
Uni t s
Mi n Ty p Max
V1a High- t hreshold for 3. 3 Vdc supply 2. 35 2. 5 2. 75 Vdc
V2a Low- t hreshold for 3. 3 Vdc supply 2. 3 2. 5 2. 7 Vdc
V1b High- t hreshold for 1. 2 Vdc supply 0. 8 0. 9 0. 95 Vdc
V2b Low- t hreshold for 1. 2 Vdc supply 0. 75 0. 8 0. 9 Vdc
Par amet er Condi t i ons Mi ni mum Ty pi cal Max i mum Uni t
VI L - 0. 4 0 0. 4 Vdc
VI H 2 3.3 3.6 Vdc
VOL - 0. 4 0 0. 4 Vdc
VOH 2.4 3.3 3.6 Vdc
I pullup 10 20 30 A
I leakage 10 A
Ci 2 4 pF
166
11.4.2 2.5 Vdc/ I O
Si gnal Name
Bus
Si ze
Descr i pt i on
CLK_REQ_N
1
1. I leakage applies only when t he PHY is powered on.
1 Open drain I / O
SMB_CLK 1 Open drain I ( H) / O
SMB_DATA 1 Open drain I ( H) / O
VI L - 0.4 0 0. 4 Vdc
VI H 2 2. 6 3. 3 Vdc
VOL
I
OL
= 10 mA
VCC = Min
- 0.4 0 0. 4 Vdc
VOH
I
OH
= - 8 mA
VCC = Min
2 2. 6 2. 8 Vdc
I pullup 10 20 30 A
I leakage 15 ( pull down) 25 ( pull down) 35 ( pull down) A
Ci 2 4 pF
PU 4. 7 K
PD 4. 7 K
167
11.4. 3 I nput Buf f er Onl y
Si gnal Name
Bus
Si ze
Descr i pt i on
RSVD_VCC3P3 2 I / O, PU
LED[ 2: 0] 3 I / O, PU
JTAG_TDI 1 I / O, PU
JTAG_TMS 1 I / O, PU
JTAG_TDO 1 I / O, PU
JTAG_TCK 1 I / O, PU
VI L - 0. 4 0 0. 4 Vdc
VI H 2 3.3 3.6 Vdc
I pullup 10 20 30 A
I leakage 10 A
Ci 2 4 pF
Si gnal Name
Bus
Si ze
Descr i pt i on
I nt ernal Power On
Reset /
LAN_DI SABLE_N
1 I ( H) , PU
TEST_EN 1 I ( no PU, no PD)
PE_RST_N 1 I ( H) , PU
168
11.4.4 SMBus AC I / O
Refer t o t he Syst em Management Bus ( SMBus) Specificat ion Version 2. 0.
11.4.5 PCI e DC/ AC Speci f i cat i ons
11. 4. 5. 1 PCI e Speci f i cat i ons ( Tr ansmi t t er )
Sy mbol Par amet er
1. 25 GT/ s
Uni t s Comment s
Min Max
UI Unit int erval 799. 92 800. 08 ps
Each UI is 800 pS + / -
100 ppm
V
t x- diff- pp
Different ial peak- t o- peak Tx volt age
swing
0. 8 1. 2 Vdc
T
t x- eye
Transmit t er eye including all j it t er
sources
0. 75 UI
T
t x- eye- median- t o
- max- j it t er
Maximum t ime bet ween t he j it t er
median and maximum deviat ion
from t he median
0. 125 UI
T
t x- rise- fall
Transmit t er rise and fall t ime 0. 125 UI
RL
t x- diff
Tx package plus silicon different ial
ret urn loss
10 db
RL
t x- cm
Tx package plus silicon common
mode ret urn loss
6 db
Z
t x- diff- dc
DC different ial Tx impedance 80 120
V
t x- cm- ac- p
Tx Vac common mode volt age
( 2. 5 GT/ s)
20 mV
I
t x- short
Transmit t er short - circuit current limit 90 mA
V
t x- dc- cm
Transmit t er DC common mode
volt age
0 3. 6 Vdc
V
t x- cm- dc- act ive-
idle- delt a
Absolut e delt a of DC common mode
volt age during L0 and elect rical idle
0 100 mV
V
t x- cm- dc- line-
delt a
Absolut e delt a of DC common mode
volt age bet ween D+ and D-
0 25 mV
V
t x- idle- diff- ac- p
Elect rical idle different ial peak out put
volt age
0 20 mV
T
t x- idle- min
Minimum t ime spent in elect rical idle 20 ns
T
t x- idle- set - t o- idle
Maximum t ime t o t ransit ion t o a valid
elect rical idle aft er sending an EI OS
8 ns
T
t x- idle- t o- diff- dat a
Maximum t ime t o t ransit ion t o valid
different ial signaling aft er leaving
elect rical idle
8 ns
169
Not e: Figure 20 is for informat ional purposes only. Do not use for act ual eye comparisons.
Fi gur e 20. Tr ansmi t t er Ey e Di agr am
11. 4. 5. 2 PCI e Speci f i cat i ons ( Recei v er )
600 mV
400 mV
0 mV
-400 mV
-600 mV
100 175 700 800 0
Time (pS)
D
i
f
f
e
r
e
n
t
i
a
l

A
m
p
l
i
t
u
d
e
625
Note: Not To Scale
Sy mbol Par amet er
1. 25 GT/ s
Uni t s Comment s
Mi n Max
UI Unit int erval 799. 92 800. 08 ps
Each UI is 800 ps + / -
100 ppm
V
rx- diff- pp- cc
Different ial peak- t o- peak Rx volt age
swing for common clock
0. 175 1. 2 Vdc
V
rx- diff- pp- dc
Different ial peak- t o- peak Rx volt age
swing for dat a clock
0. 175 1. 2 Vdc
T
rx- eye
Receiver minimum eye t ime opening 0.4 N/ A UI
T
rx- eye-
median2maxj it t er
Maximum t ime delt a bet ween median
and deviat ion from median
N/ A 0.3 UI
BW
rx- pll- hi
Maximum Rx PLL bandwidt h N/ A 22 MHz
BW
rx- pll- lo- 3db
Minimum Rx PLL bandwidt h for 3 dB
peaking
1. 5 N/ A MHz
RL
rx- diff
Rx different ial ret urn loss 10 N/ A dB
RL
rx- cm
Rx CM ret urn loss 6 N/ A dB
Z
rx- dc
Rx CM DC impedance 40 60
Z
rx- diff- dc
Rx different ial Vdc impedance 80 120
V
rx- cm- ac- p
Rx Vac CM volt age N/ A 150 mVp
170
Not e: Figure 21 is int ent ed t o show t he difference bet ween t he PCI e 1. 0 and PCI e- based
receiver sensit ivit y t emplat es. I t is for informat ional purposes only.
Fi gur e 21. Recei ver Eye Di agr am
Sy mbol Par amet er
1. 25 GT/ s
Uni t s Comment s
Mi n Max
Z
rx- high- imp- dc-
pos
DC input CM impedance for V> 0 50 K N/ A
Z
rx- high- imp- dc-
neg
DC input CM impedance for V< 0 1 K N/ A
V
rx- idle- det - diffp- p
Elect rical idle det ect t hreshold 65 175 mV
T
rx- idle- det - diff-
ent ert ime
Unexpect ed elect rical idle det ect N/ A 10 ms
600 mV
87.5 mV
0 mV
-87.5 mV
-600 mV
240 800 0
Time (pS)
D
i
f
f
e
r
e
n
t
i
a
l

A
m
p
l
i
t
u
d
e
400 560
Note: Not To Scale
171
11.5 Di scr et e/ I nt egr at ed Magnet i cs Speci f i cat i ons
Cr i t er i a Condi t i on Val ues ( Mi n/ Max )
Volt age
I solat ion
At 50 t o 60 Hert z for 60 seconds 1500 Vrms ( min)
For 60 seconds 2250 Vdc ( min)
Open Circuit
I nduct ance
( OCL) or OCL
( alt ernat e)
Wit h 8 mA DC bias at 25 C 400 H ( min)
Wit h 8 mA DC bias at 0 C t o 70 C 350 H ( min)
I nsert ion Loss
100 kHz t hrough 999 kHz
1. 0 MHz t hrough 60 MHz
1 dB ( max)
0. 6 dB ( max)
0. 8 dB ( max)
1. 0 dB ( max)
2. 4 dB ( max)
Ret urn Loss
When reference impedance is 85 ,
100 , and 115 .
Not e t hat ret urn loss values might
vary wit h MDI t race lengt hs. The
LAN magnet ics might need t o be
measured in t he plat form where it
is used.
18 dB ( min)
12 t o 20 * LOG ( frequency in MHz / 80) dB ( min)
Crosst alk
I solat ion
Discret e
Modules
1. 0 MHz t hrough 29. 9 MHz
30 MHz t hrough 250 MHz
- 50. 3+ ( 8. 8* ( freq in MHz / 30) ) dB ( max)
- 26- ( 16. 8* ( LOG( freq in MHz / 250) ) ) ) dB ( max)
- 26 dB ( max)
Crosst alk
I solat ion
I nt egrat ed
Modules
- 50. 8+ ( 8. 8* ( freq in MHz / 10) ) dB ( max)
- 26- ( 16. 8* ( LOG( freq in MHz / 100) ) ) ) dB ( max)
- 26 dB ( max)
Diff t o CMR
1. 0 MHz t hrough 29. 9 MHz
30 MHz t hrough 500 MHz
- 40. 2+ ( 5. 3* ( ( freq in MHz / 30) ) dB ( max)
- 22- ( 14* ( LOG( ( freq in MHz / 250) ) ) ) dB ( max)
CM t o CMR
- 57+ ( 38* ( ( freq in MHz / 270) ) dB ( max)
- 17- 2* ( ( 300- ( freq in MHz) / 30) dB ( max)
- 17 dB ( max)
172
11. 6 Osci l l at or / Cr y st al Speci f i cat i ons
Tabl e 86. Ex t er nal Cr y st al Speci f i cat i ons
Par amet er Name Sy mbol
Recommended
Val ue
Max / Mi n Range Condi t i ons
Frequency f
o
25 [ MHz] @25 [ C]
Vibrat ion Mode Fundament al
Frequency Tolerance @25 C Df/ f
o
@25C 30 [ ppm] @25 [ C]
Temperat ure Tolerance Df/ f
o
30 [ ppm]
Series Resist ance ( ESR) R
s
50 [ ] max @25 [ MHz]
Cryst al Load Capacit ance C
load
18 [ pF]
Shunt Capacit ance C
o
6 [ pF] max
Drive Level
1
1. Cryst al must meet or exceed t he specified drive level ( D
L
) . Refer t o t he cryst al design guidelines in t he I nt el
5 Series Family PDG for more det ails.

D
L
200 [ W] max
Aging Df/ f
o
5 ppm per year 5 ppm per year max
Calibrat ion Mode Parallel
I nsulat ion Resist ance 500 [ M] min @ 100 Vdc
173
Tabl e 87. Cl ock Osci l l at or Speci f i cat i ons
Fi gur e 22. XTAL Ti mi ng Di agr am
Par amet er Name Sy mbol / Par amet er Condi t i ons Mi n Ty p Max Uni t
Frequency f
o
@25 [ C] 25. 0 MHz
Swing Vp- p 3 3.3 3. 6
1
1. Condit ioning circuit required t o limit t he volt age swing of VI H/ VI L t o 1. 2 Vdc.
V
Frequency Tolerance f/ f
o
- 20 t o + 70 50 [ ppm]
Operat ing Temperat ure T
opr
20 t o + 70 [ C]
Aging f/ f
o
5 ppm per year [ ppm]
Coupling Capacit or C coupling 8 10 12 pF
XTAL_X1 swing in - High ViH 1. 0 1. 2 V
XTAL_X1 swing in - Low ViL 0 0. 2 V
TH_XTAL_I N XTAL_I N High Time 13 20 nS
TL_XTAL_I N XTAL_I N Low Time 13 20 nS
TJ_XTAL_I N XTAL_I N Tot al Jit t er 200
2
2. Broadband peak- t o- peak = 200 pS, Broadband rms = 3 pS, 12 KHz t o 20 MHz rms = 1 ps
pS
174
Not e: Peak- t o- peak volt age present ed at t he XTAL1 input cannot exceed 1.8 Vdc.
Fi gur e 23. Cl ock Osci l l at or Schemat i c
3.3 V dc
C1
VDD3p3
1 K ohm
1 K ohm 1000 pF
CLK
OsciIIator PHY
XTAL1
82578 GbE PHYSchemat i c and Boar d Lay out Check l i st s
175
12. 0 Schemat i c and Boar d Lay out Check l i st s
The 82578 Design and Board Layout Checklist s can be found at www.int el. com.

176
Schemat i c and Boar d Layout Check l i st s82578 GbE PHY
82578 GbE PHYRef er ence Schemat i cs
177
13. 0 Ref er ence Schemat i cs
The 82578 reference schemat ics can be found at www. int el. com.

178
Ref er ence Schemat i cs82578 GbE PHY
82578 GbE PHYModel s
179
14. 0 Model s
Cont act your I nt el Represent at ive for access t o t he 82578 I BI S model.

180
Model s82578 GbE PHY

Gbe Phy Datasheet

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June 2010 Order Number: 319440- 016

5 Ser i es Ex pr ess Chi pset .

4 processor support ing HT Technology and a HT Technology enabled

Aut o Connect Bat t ery Saver ( ACBS) . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 28

5 Series Express Chipset / 82578 NVM Cont ent s.. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 106

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace.. . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 107

5 Series Express Chipset int egrat ed Media Access Cont roller

5 Series Express Chipset Family Ext ernal Design Specificat ion ( I nt el

82578 Schemat ic and Layout Checklist s, I nt el Corporat ion

5 Series Express Chipset SMLink0.

5 Series Express Chipset t o configure t he 82578 as well

5 Series Express Chipset .

5 Series Express Chipset SPI st rap set t ing. Choosing

R2 and R5 (0 ohm 0805)

5 Series Express Chipset SMBus address valid.

5 Series Express Chipset

82578 GbE PHYPow er Management and Del i v er y

Aut o Connect Bat t er y Sav er ( ACBS)

5 Series Express Chipset . GPI O12 also needs t o be configured using I nt el

5 Series Express Chipset

5 Series Express Chipset

5 Series Express Chipset would come in as an in- band message over t he

5 Series Express Chipset wakes t he host .

5 Series Express Chipset t o t he APM

5 Series Express Chipset wake up event t hrough an in- band

5 Series Express Chipset wake up event .

5 Series Express Chipset wake up event .

5 Series Express Chipset Family Ext ernal Design

5 Series Express Chipset EDS) and t he I nt el

5 Series Express Chipset

5 Series Express Chipset EDS) . This

5 Series Express Chipset EDS. This process is

Act ive Management Technology OEM Bring- Up

5 Series Express Chipset EDS for more informat ion

5 Series Express Chipset EDS) .

5 Series Family PDG and t he 82578 Reference

5 Series Express Chipset and t he 82578. The following t able

5 Ser i es Ex pr ess Chi pset / 82578 NVM Cont ent s

5 Series Express Chipset and t he

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Series Express Chipset and t he

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Series Express Chipset space. These signals are sampled by

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Series Express Chipset ) .

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace

5 Ser i es Ex pr ess Chi pset MAC Pr ogr ammi ng I nt er f ace