ECE270, HW10; DUE: March 22, 2012

[Name:_____________________________________] Peer Reviewed by: _____________________________

PROBLEM 1: You are given a rising edge triggered D-Flip-Flop (DFF). Using logic gates, design the ASYNCHRONOUS CLEAR and ASYNCHRONOUS SET functions. The CLEAR function has priority (if both SET and CLEAR are high, then the output is cleared. Write the truth table for the new functions: IN CLEAR SET QNS

Show your logic design of the CLEAR and SET functions connected properly to this DFF:

(c) Using the blocks below representing your one-bit circuit in (b), design a 4-bit loadable ARITHMETIC RIGHT shift register, label the inputs: LOAD, D3, D2, D1, D0 (D0 is least significant bit) and the SET, CLEAR, CLK ; finally, label the outputs Q3, Q2, Q1, Q0 ; where Q0 is the least significant bit. (HINT: this is the shifter that propagates the most significant bit. ..also, you have to add some circuit to make it loadable) :

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ECE270, HW10; DUE: March 22, 2012

[Name:_____________________________________] Peer Reviewed by: _____________________________

PROBLEM 2: You are given the VHDL for a rising edge triggered D-Flip-Flop (DFF) below. Using: if then else statements in VHDL, design the ASYNCHRONOUS CLEAR and ASYNCHRONOUS SET VHDL. The CLEAR function has priority (if both SET and CLEAR are high, then the output is cleared.

Modify (cross out and/or add to) the VHDL below to include the new functions of CLEAR and SET:

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ECE270, HW10; DUE: March 22, 2012

[Name:_____________________________________] Peer Reviewed by: _____________________________

PROBLEM3: Flip-flops and counters can be used to implement some useful clocking functions, draw a block diagram containing these components and logic gates to achieve the following: (a) Design a system that will generate a single clock pulse one clock period long each time a push button is pressed (assume you have a clock input given).

(b) Design a system using a counter (as in previous homework, 4-bit up loadable counter with clock, reset and enable) that will assert a signal for exactly 13 clock pulses each time a push-button is pressed (include push-pulse circuit from above).

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ECE270, HW10; DUE: March 22, 2012

PROBLEM4:

[Name:_____________________________________] Peer Reviewed by: _____________________________

Search the web for a good logic problem (logic puzzle or logic word problems) that uses some of the concepts that we have learned in ECE270. Attach the problem and the solution to this homework. The only requirement for the points is that you MUST connect the problem to one of the ECE270 concepts (like the poisoned wine problem, for example, uses binary code to find the right bottle).

Have a fun Spring Break!!

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