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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 4, APRIL 2002

SpeedPowerAccuracy Tradeoff in High-Speed CMOS ADCs


Koen Uyttenhove, Student Member, IEEE, and Michel S. J. Steyaert, Senior Member, IEEE
AbstractIn this article the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metaloxidesemiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends will be discussed and it will be shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison will be made between slew-rate dominated circuits and settling dominated circuits. At the end a comparison with published high-speed ADCs is presented using the figure of merit.

I. INTRODUCTION IGH-SPEED analog-to-digital converters (ADC) are an essential part in a signal processing system. Radar applications and hard disk drive read channels require very high conversion speeds and relatively low resolutions [1][3]. Since several ADCs may be needed in a system-on-chip, the ADC should consume only a small fraction of the total power budget. The technology chosen for communications equipment, however, is dictated by digital circuitry. And so the preferred technology for these mixed-signal chips is complementary metaloxidesemiconductor (CMOS) technology. Shrinking feature size reduces the cost of the overall system, which is a major system parameter. Therefore, analog design is forced to adopt the trend toward smaller feature size and smaller oxide thickness [4]. New challenges arise due to the required lower supply voltage; therefore, it is interesting to analyze or predict the power consumption of future high-speed ADCs. As a test-structure, a flash ADC is chosen because this architecture is used for very high-speed ADCs and its performance is really dominated by matching issues. To analyze the flash ADC, one building block will be used namely the preamplifier. The derived equations are also valid for the comparator, so the predictions can be used for the total flash ADC. The dynamic performance is also very important in the performance of the ADC, but in this paper, only the static performance is tackled. Both static and dynamic aspects are very important in the design of a high-speed ADC.

Fig. 1. ADC front-end, indication of offset voltages.

II. MATCHING IN FLASH ADC The correct operation of a flash ADC depends on the accurate definition of the reference voltages sensed by each comparator. These reference voltages are compared with the input, but due to comparator offset voltages this comparison is not exactly equal to the reference level (see Fig. 1). Since the comparator offset voltage is a random variable (which depends on the matching properties of the used technology [5]), it directly influences the differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics of the ADC [6]. Therefore, the first step in the design of a flash ADC consists in deriving an offset voltage standard deviation that guarantees with a high probability that the design complies with a certain performance specification or high yield [7] or lsb (1)

Manuscript received January 21, 2002; revised May 8, 2002. This paper was recommended by Associate Editor M. Flynn. The authors are with the Katholieke Universiteit Leuven, Department Elektrotechniek, afd. ESAT-MICAS, B-3001 Heverlee, Belgium (e-mail: koen.uyttenhove@esat.kuleuven.ac.be). Publisher Item Identifier 10.1109/TCSII.2002.801191.

with a constant depending on the resolution and the wanted yield percentage and lsb the least significant bit of the converter. As an example, a Monte Carlo simulation has been done in MATLAB1 to calculate the yield of a 6-b flash ADC with an input range of 1.6 V with respect to the offset standard deviation of the comparator. The result of the simulation is shown in Fig. 2. As can be seen on this figure, to have a yield of 99%, the should be smaller than LSB. Section II-A will show models to calculate this offset voltage standard deviation of the comparator. Together with this information the tradeoff between speed, power and accuracy will be shown.
1MATLAB

is a registered trademark of The MathWorks, Natick, MA.

1057-7130/02$17.00 2002 IEEE

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offset voltage can be written in terms of the mismatch parameand of the used technology ters (5) In this calculation, the distance effect has been neglected because of its minor contribution to the overall mismatch. The is defined as the distance for which the corner distance mismatch due to the distance effect is equal to the mismatch due to the size dependence for a minimal size device. The obare very large compared to the typtained critical distances ical size of an analog circuit. Therefore, the distance dependence of the parameter mismatch is being neglected in the following sections. III. SPEED-POWER-ACCURACY TRADEOFF The bit accuracy that can be achieved is proportional to the matching of the transistor. To improve the system accuracy, larger devices are required, but at the same time the capacitive loading of the circuit nodes increases and more power is required to attain a certain speed performance. This tradeoff has been documented by Kinget et al. [8] and is shortly repeated here for a typical input stage of a high-speed ADC (see Fig. 3). The speed performance of such a topology is in first order given by
Fig. 3. ADC front-end differential input pair.

Fig. 2. MonteCarlo simulation of yield of ADC as a function of comparator offset standard deviation.

Speed

(6)

A. Mismatch of Comparator A typical flash ADC consists of an array of preamplifiers (e.g., differential pair structure, see Fig. 3) followed by an array of comparators. To be able to calculate the offset of the comparator, mismatch formulas for a differential pair configuration are deduced. In this deduction, the mismatch formulas from Pelgrom [5] are used2 and are given by (2) (3) , , , and are process-dependent parameters. where is the distance on chip between the matching transistors. and are the width and the length of the input transistors of the differential pair. is the current factor of the technology. The input-referred offset of the differential pair is given by [8] (4) the gate-overdrive voltage of the input transistors. with After substituting the formulas for the mismatch (2) and (3), the
2There exists mismatch models for short and narrow transistors but these formulas will not lead to closed-form equations. In this deduction, no exact calculation will be done but trends will be shown.

In this analysis, the speed is supposed to be determined by the gain-bandwidth. Therefore, the gate-overdrive voltage remains low and constant. Also the drain-bulk capacitance has been neglected here (these parasitic capacitance will be included further on). In this analysis the square-law model has been used; this model is not very accurate for short transistor lengths, but inclusion of extended models would lead to enormous formulas of the that would not be easily understood. The use of the transistor as a speed parameter gives a first indication of the maximum speed achievable in a certain technology (for a certain bias condition). On the other hand, the accuracy that can be achieved in a system is proportional to the matching accuracy of the components. In previous section, a formula was derived for the offset of a differential amplifier, so the inverse of the accuracy squared (maximum input divided by the maximum offset) is given by Accuracy (7)

In this formula, the mismatch has been neglected. Later on mismatch will be taken into account. The power drain in that circuit is a function of the supply voltage and the current consumption or Power (8)

If the equations (6)(8) are combined following formula can be derived: Speed Accuracy Power (9)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 4, APRIL 2002

It has been shown that the relationship given by (9) still holds for more complex circuits [8], such as current processing circuits (current mirrors), voltage processing circuits (differential pairs and opamps) and even multistage circuit designs. The relationship above implies that, for the circuits of today which aim high speed, high performance or accuracy, and low-power drain, a technological limit is encountered, namely the mismatch of the devices. This means that for a given technology, if high speed and high accuracy is required, this can only be achieved by consuming power. For example, if one bit extra accuracy is required in the design of ADC the power drain for the same speed performance will increase with a factor of four. IV. ACTUAL TREND OF MOS PARAMETERS RELEVANT TO ADC DESIGN To determine the impact of scaling on the speedpoweraccuracy tradeoff, three scaling trends are first discussed, namely the mismatch scaling, the supply voltage scaling and the relatively increasing importance of parasitic capacitances. A. Mismatch Scaling To reduce the short channel effects in deep submicron transistors, the oxide thickness is scaled down together with the minimum transistor length. As shown in [9], the threshold mismatch parameter is primarily dependent on the bulk charge fluctuations. To convert this charge fluctuations into a voltage fluctuation at the gate, the oxide gate capacitance plays an important part (10) Together with the expression of the standard deviation of the bulk charges this leads to the following expression for the mismatch parameter [9]: (11) the total implant dose. So, the threshold mismatch with parameter is proportional to the oxide thickness. As a consedecreases as quence, the threshold mismatch parameter technology scales down [10]. In Table I, this trend has been shown by plotting foundry data for different processes. The gate-oxide capacitance, on the other hand, increases when technology scales down (inverse proportional with the decreases as techoxide thickness). Nevertheless, nology scales down and as a result the tradeoff becomes better [(9)]. This means that, e.g., for the same speed and accuracy, less power is needed when technology is scaled down. mismatch is For present-day processes the impact of the (decreases) and dominant. When the scaling trends for (remains constant) are compared (see Table I), it is evident that the mismatch gains in importance for deeper submicron technologies. For some technology in the future (nanotechnology) the mismatch will be at least as important and even more immismatch for the calculation of the accuracy portant as the of circuits in the whole strong inversion region. This will have a drastic impact on the power consumption trend of high-speed ADCs as will be shown later.
Fig. 4.

TABLE I MISMATCH PARAMETERS FOR SEVERAL CMOS TECHNOLOGIES

Supply voltage scaling as function of L

B. Supply Voltage Scaling To reduce the short channel effects in submicron CMOS transistors the maximum supply voltage is scaled down together with the oxide thickness as shown in Fig. 4 (0.25- m technology uses a 2.5-V supply, 0.18 m uses a 1.8-V supply). Usually, the input range of the ADC is made as large as possible. Therefore, the least significant bit of the converter scales down together with the supply voltage, leading to a smaller allowable mismatch. Consequently, the scaling advantage for the tradeoff with smaller technology line-widths is reduced. C. Parasitic Capacitances The miniaturization of CMOS transistors is driven primarily by digital applications. And so, the primary objective is the increase in circuit speed and density, both of which benefit from the reduced channel length. The approaches that different manufacturers employ to scale down the gate length may differ, but they generally require scaling down of the oxide thickness, reducing the junction depths and increasing the channel doping. As a result the parasitic bulk capacitances increase. The trend for this increase is more difficult to establish as compared with the previous trends. The scaling of the gate length is not always accompanied with a scaling of the drain (source) widths that covers one row of contacts. This trend is also illustrated with the plots of the two relevant speed parameters: , the cutoff

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Assuming equal gate-overdrive voltages, the power drain can is proportional to the oxide thickness) be compared ( (16) So, to achieve the same speed and accuracy, the power in the down-scaled technology is smaller, because of the improved matching of this technology. Now, some modifications will be done on these formulas to include the supply-voltage scaling and the relatively increasing importance of the drain-bulk capacitance compared to the gate-oxide capacitance. Reducing the supply voltage leads to a smaller allowable mismatch in the down-scaled technology [see (1)] with (17)

Fig. 5.

F t and F -3 dB as a function of process minimum length.


, the maximum operation frequency (see (12) (13)

The speed formula can be rewritten, now including the drain bulk capacitance [see (11)]

frequency and Fig. 5)

(18) is the gate-overdrive voltage of input pair transistors (Fig. 1). Again assuming equal gate-overdrive voltages, the power drain can be compared5

One can clearly see a gap between the two parameters. This gap is enlarging with every technology generation. In this analysis, nothing is said about the influence of interconnect capacitance which is becoming very important and causes an extra load for the driver-transistors. So as a conclusion, the impact of parasitic capacitances is very important and doesnt scale down with the downscaling of technology. V. IMPACT OF TECHNOLOGY SCALING A. Impact , , and Parasitic Capacitance Scaling

(19)

An example will illustrate the scaling issues which degrade the speedpoweraccuracy tradeoff in high-speed ADC. Consider a 6-b, 500 MSample/s ADC in two technologies, e.g., 0.5- m and 0.25- m CMOS. First, the supply voltages are supposed to be equal, secondly the mismatch is expected to be dominated by the threshold mismatch and the drain-bulk capacitance and other capacitances are neglected. Because the two ADCs have the same resolution, offset demands are equal [see (5)] so3 (14) To achieve the same acquisition speed, the speed requirement [see (6)]4 should be the equal leading to the next formula (again neglecting the drain bulk capacitance)

(15)
3Index 1 is used for the 0.5-m technology, index 2 for the 0.25-m technology. 4These equation also models the exponential time constant of the comparator of the ADC.

Because ground rules do not scale at the same rate as technology minimal length and doping levels increase, the last factor in (19) is smaller than 1. This shows the relatively increasing power consumption when down-scaling the technology ( ). If the drain-bulk capacitances are not important then the power consumption trend would be a straight horizontal line (as indicated on the figure). This trend toward relative increasing power consumption is also shown in Fig. 6 where the powertrend is shown as a function of minimum technology length for three different cases indicated on the figure. Case 1: Supply voltage scaling and Drain-bulk capacitance scaling: because of the increasing matching demands the downscaling of the supply voltage is no longer compensated and so a straight line is the conclusion. Case 2: Id. as case 1 but now the drain-bulk capacitance scaling is not included: the extra load on the driver transistors leads to a slightly increasing straight line.
5The

typical assumption of [t

= L=50] [4] has been used in this formula.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 4, APRIL 2002

Fig. 6. Power consumption as function of scaling. Three different cases are shown and indicated on the figure.

Fig. 7. Power consumption scaling toward nanoelectronics (now mismatch is included). [The x-axis on this figure is only an indication that somewhere in the future power will not scale anymore. Therefore, the point where this trend begins is not strictly pinched on 0.5 m.]

Case 3: No supply voltage scaling and drain-bulk capacitance scaling: the increasing matching properties lead to a decreasing power consumption of the implemented converter. To conclude, the expected power-decrease is counteracted by the more stringent mismatch demand and the relatively increasing drain-bulk capacitance. B. Impact of -Mismatch Scaling factor toWhen technology scales further the constant gether with the gate-overdrive voltage becomes larger than the parameter. For a of 0.12 m and a gate-overdrive voltage of 0.2 V the -mismatch is dominant (this is based on Table I and the mismatch formulas of a differential pair). If the -mismatch becomes dominant, the following [based upon (19)] can be derived:
Fig. 8. Settling and slewing behavior in an analog system.

(20) which makes the case even worse (power increases approximately linearly with downscaling). The reduced signal swing (and thus increased matching demand) is no more compensated by the increased matching of the technology. This trend is indicated on Fig. 7 (which is a zoomed version of Fig. 6) where the power increase in indicated. This clearly illustrates the problems analog designs encounter when digital technology is scaled down. Whereas, the power consumption of the digital blocks is quadratically dependent on the supply voltage and so decreases fast when technology is downscaled. C. Slew-Rate (SR) Dominated Circuits Versus Settling Dominated Circuits In previous derivations and formulas, the chosen speed parameter is equal to the generic small-signal time constant. Other analyzes use only the slew rate (SR) as the speed parameter [10]. Other analog building blocks can also exhibit a SR behavior (together with a small-signal behavior). In this section the influence of SR and settling behavior (SET) together is examined. Fig. 8 shows the SET of an operational amplifier (opamp) in unity feedback when a step function is applied to the input of the opamp, one can clearly distinguish the two speed parameters. First there is a slewing behavior and then a linear SET is observed. To calculate the impact of this slewing time, a simple additive model is proposed where the speed is determined by the linear addition of the two speed parameters: Together with the following formulas: and (21) (22) A parameter can now be defined by taking the ratio of the two speed parameters

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and this parameter decreases when the supply voltage decreases (for a fixed gate-overdrive voltage). The same formulas, as in the previous section, can now be redone, but with both SET and slewing behavior

(23) or with the introduction of the parameter used technology) (index denotes the

(24) and so the power consumption (for equal gate-overdrive voltages) ratio is

Fig. 9. Power consumption as a function of scaling. Slewing and SET are included as also mismatch.

three levels: system level, architectural level, and technology level. A. Technological Modifications Not only do analog circuits have problems with the decreasing power supply voltage and mismatch, digital circuits also suffer from the mismatch between identical devices, e.g., offsets in a SRAM cell. Because of the enormous economical impact of digital circuits, maybe more effort will be spent at extensive research to achieve much better mismatch parameters in future technologies. Here, for once, digital demands go hand-in-hand with analog demands. Another technological adaptation is the use of dual oxide processes which can handle the higher supply voltages necessary to achieve the required dynamic range in data converters. B. System Level Good system level design can substantially decrease the needed performance of the data converter in the system. High level design decisions can have a huge impact on the speedpoweraccuracy of the ADC. This high level design needs behavioral models, including power estimators [14]. C. Architectural Level: Averaging Techniques In this section some possible architecture modifications are presented to break through this tradeoff. Two possibilities will be discussed: analog preprocessing techniques and averaging techniques. Analog preprocessing techniques reduce the input-capacitance of the flash ADC and the number of preamplifiers. Examples are interpolating (voltage/current), folding. These techniques do not really improve the speedpoweraccuracy tradeoff, they only decrease the input capacitance (limiting the highest input frequency) and the number of preamplifiers or comparators. Averaging is a technique which reduces the offset specification for high-speed ADCs without requiring larger transistors areas. Averaging was first presented in 1990 by [11], where the outputs of the differential bipolar preamplifiers

(25) and because (26) The power consumption trend doesnt stay the same (as in the case when only the settling parameter was included) but has a sublinear slope. This is due to the introduction of the slewing behavior. This trend is plotted in Fig. 9 as a function of the technology and for three different gate overdrive voltages (SR, SET, mismatch ,and -mismatch, Ab, are included as shown in the legend.). One can clearly see that for smaller gate-overdrive voltages the power increase turn-point is pushed toward smaller technologies. This is intuitively understood because then the supply voltage scaling is advantageous for the power consumption because the circuit is longer in a slewing behavior. The advantage of using a lower gate-overdrive voltage is a remarkable conclusion. It indicates that for future ADCs a behavior close to the linear behavior is preferable for the implementation and power consumption of high-speed ADCs. VI. SOLUTIONS In the previous sections, the fundamental tradeoff between power, speed and accuracy has been discussed. It has been shown that without extra precautions, technology scaling will increase the power consumption of high-speed ADCs in the future. To circumvent this power-increase, modifications have to be found. From a general point of view, this can be done on

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this tradeoff have been examined. It is shown that without extra modifications to the design or technology, power consumption will become a problem for future high-speed ADCs. Especially for very deep submicron technologies power will go up in order to achieve the same specs as nowadays. This can limit the integration of digital and analog electronics on the same chip. Of course architectural modifications or technological adaptations can circumvent this trend (e.g., averaging techniques [10], dual oxide processes ). Also the trend to lower gate-overdrive voltages has been shown to be preferable for the power consumption of high-speed ADCs which are dominated by matching demands. REFERENCES
Fig. 10. Figure of merit as a function of minimal technology length for different published 6-b converters. [1] M. Flynn and B. Sheahan, A 400 MSample/s 6b CMOS folding/interpolating ADC, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 1998, pp. 150151. [2] K. Nagaraj and T. R. Viswanathan et al., A dual mode 700Ms/s 6-bit, 200MS/s 7-bit converter in 0.25 micron digital CMOS, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2000, pp. 426427. [3] K. Sushihara et al., A 6b 800Ms/s CMOS A/D converter, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2000, pp. 428429. [4] W. Sansen, Analog circuit design in scaled CMOS technology, in Dig. Tech. Papers, Symp. VLSI Circuits, June 1996. [5] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits, vol. SC-24, pp. 14331439, Oct. 1989. [6] B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995. [7] H. Tuinhout, M. Pelgrom, and M. Vertregt, Transistor matching in analog CMOS applications, in Proc. IEEE IEDM Tech. Dig., 1998, pp. 915918. [8] P. Kinget and M. Steyaert, Impact of transistor mismatch on the speedaccuracypower trade-off of analog CMOS circuits, in Proc. Custom Integrated Circuits Conf., May 1996, pp. 333336. [9] J. Bastos, Characterization of MOS transistor mismatch for deep-submicron analog design, Ph.D. dissertation, Dept. Elektrotechniek, K.U. Leuven Univ, Heverlee, Belgium, 1998. [10] K. Bult, Analog design in deep sub-micron CMOS, in Proc. European Solid-State Circuits Conf., Sept. 2000, pp. 1117. [11] K. Kattmann and J. Barrow, A technique for reducing differential nonlinearity errors in flash A/D converters, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 1991. [12] G. Geelen, A 6b 1.1GSample/s CMOS A/D converter, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2001. [13] M. Choi and A. A. Abidi, A 6b 1.3GS/s A/D converter in 0.35 m CMOS, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2001. [14] P. Scholtens and M. Vertregt, A 6b 1.6GS/s CMOS A/D converter, in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2001.

were combined by a resistive network. This technique makes a tradeoff between the improvement in DNL/INL and the gain of the preamplifier. An improved version of this technique is presented in [13] where the improvement in DNL/INL only depends on the number of stages which contribute the averaging. Averaging can be seen as taking the average value of neighboring node-voltages and thereby reducing the offset demand. The offset of the averaged value is equal to the original offset divided by the square root of the number of values one has averaged. The latest published high-speed 6-b converters use this technique to reduce the input referred offset of the preamplifiers and comparators [12][14]. VII. COMPARISON WITH PUBLISHED 6-B ADCS To compare the developed formulas and the published data a figure (see Fig. 10) is presented which shows the figure of merit of several published 6-b converters versus their implementation technology. The figure of merit used here is FOM (27)

Hz

The factor can be omitted in this FOM because only six bitters are being shown. One clearly sees a good agreement between the formulas and the published data: A decrease in power consumption is observed as technology scales down but at a certain technology node this trend is disrupted and no drastic power decrease is seen no more. Than the averaging technique solutions shows to be a good candidate to break through this speedpoweraccuracy tradeoff. VIII. CONCLUSION In this paper, the fundamental tradeoff between speedpoweraccuracy and the impact of technology scaling on

Koen Uyttenhove (S97) was born in Diksmuide, Belgium, in 1975. He received the M.S. degree in microelectronics from the Katholieke Universiteit Leuven (K.U. Leuven), Heverlee, Belgium, in 1998. The subject of his M.S. thesis was the design of low-power techniques for multimedia applications. This thesis was done at the laboratories of Imec, Belgium. He is currently pursuing the Ph.D. degree in the field of analog integrated circuit design with emphasis on the design of high-speed flash/pipelined analog to digital converters, at K.U. Leuven. Since September 1998, he has been a Research Assistant with ESAT-MICAS Laboratories, K.U. Leuven.

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Michel S. J. Steyaert (S85A89SM92) was born in Aalst, Belgium, in 1959. He received the Master degree in electrical-mechanical engineering and the Ph.D. degree in electronics both from the Katholieke Universiteit Leuven (K.U. Leuven), Heverlee, Belgium, in 1983 and 1987, respectively. From 1983 to 1986, he obtained an IWNOL Fellowship (Belgian National Foundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT, K.U. Leuven. In 1987, he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988, he was a Visiting Assistant Professor at the University of California, Los Angeles. The National Fund of Scientific Research (Belgium) appointed him as a Research Associate in 1989, a Senior Research Associate in 1992, and a Research Director in 1996, all at the Laboratory ESAT, K.U. Leuven. Between 1989 and 1996, he was also a part-time Associate Professor. Currently, he is a Full Professor at the K.U. Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Dr. Steyaert received the European Solid-State Circuits Conference Best Paper Award in 1990, the ISSCC Evening Session Award in 1995 and 1997, the IEEE Circuits and Systems Society Guillemin-Cauer Award in 1999, and the NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications in 1991 and 2000.

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