INSTRUCTIONS

Tomi Cederqvist
Niila Rautanen
Pasi Helin

16.9.2005

Debugging Instructions for SF20

1 (17)

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

2 (17)

16.9.2005

Edition history:
Versio
n
0.1

Date

State

Author

15.9.2005

Draft

Tomi
Cederqvist,
Niila Rautanen,
Pasi Helin

Comment

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

3 (17)

16.9.2005

Content:
1. SERVICE TERMINALS.........................................................................................................................4
PIR4ST.....................................................................................................................................................4
UBISTE.....................................................................................................................................................4
2. traffic flow in sf20..................................................................................................................................5
3. ub2g5np................................................................................................................................................6
SSTAT..................................................................................................................................................7
PSTAT..................................................................................................................................................7
4. PI40SAX................................................................................................................................................9
GSTAT................................................................................................................................................10
5. ORT8850.............................................................................................................................................12
6. UXASIC...............................................................................................................................................15
7. Loopbacks...........................................................................................................................................16
8. Tips & Tricks........................................................................................................................................17

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

4 (17)

16.9.2005

Purpose of this document

This document contains unofficial instructions for debugging SF20dev and SF20x functional
units. Purpose is to collect service terminal commands and usefull tricks to help integration
and functional testing. Main focus is in debugging traffic flow inside plug-in unit.
1.

SERVICE TERMINALS

Following picture illustrates service terminal extensions that can be used in debugging.

SF20
PPC7

UX1-A
UTOPIA L1

MPC8280

UX
FPGA

MII

ETH-A
LXT9712

SFB40

P31
P30
P29

P3
G++

(secondary)

P2

PI40SAX

SD4G-A
P3
P2
P1
P0

PIR4ST

SPI-3

QSP_BP

UBISTE

P1
G++

UB2G5NP
2.5 G
CML

MI

(primary)

P0

OR8TST

PIR4ST,UBISTE and OR8TST service terminal extensions are available in official SW build
(from 51.x-x onwards).

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin
2.

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16.9.2005

TRAFFIC FLOW IN SF20

Following picture illustrates typical traffic (internal) flow in SF20 piu. Note that there are 3
different types of SF20 HW layouts (SF20dev,SF20A,SF20L) but debugging principals are
same for all units.
Detailed HW layout pictures can be found from SF20 Implementation Specification (HW
files):
SF
U

Work port
card

SFB4
0
P0
G++
(secon
dary)

PI40SA
X

2 x 622 M
LVDS
2 x 622 M
LVDS

SD
1G

ALP
1-B

P1

MI

SPI-3

P3
P2
P1
P0

UB2G5N
P

2.5 G
CML

QSP_B
P

P2
G++
(primar
y)
P3

Protect port
card

SD
1G

ALP
1-B

NOTE: There are 2 x SD4G-A HW blocks inside SF20dev (2 x UB2G5NP, 4 x ORT8850)

Example: MXU (MX622-B/C) is physically cabled into legacy port 0.
ZWFS:1,1,1,B84-85,2:1,1,9,B76-77,1; //SFU-0 <-> MXU-0
[HWP028GX.XML]
<int_port name="SFPIF" index="0" phys_port="0" location="B84-85"></int_port>
SFPIF
0
SFPIF
1
SFPIF
2
SFPIF
3

SFPI
F
SFPI
F
SFPI
F
SFPIF
7

2x
622M

.
.
.

2x SD4G-A

0
1
2
3

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin
3.

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16.9.2005

UB2G5NP
In previous SF10 PIU the serial port interface is implemented in the separate backplane
drivers (HW block SD4G) and the switch fabric device has parallel interface. As PI40SAX
offers integrated serdes function for 32 ports, the fabric interfaces are changed. The
backwards compatible interfaces, legacy ports, need adaptation to PI40SAX device. The
new HW block SD4G-A makes the adaptation. SD4G-A contains one UB2G5NP and two
ORT8850H (BPD-G++) devices.
UBISTE for UB2G5NP (version Feb 28 2005 09:57:53) command line options:
cap <id>

: capture test cell

dtr <id> <mphy>

: read entry from descriptor table

dtw <id> <mphy> <port> <mc> <class> <rqn> : write entry to descriptor table
fopi <id> <mode>
gstat <id>

: set FOPI switchover mode (0:Disable, 1:Enable)

: dump global statistics

init <id>

: initialize chip

ins <id> <link>

: insert test cell

lb <id> <mode>

: set loopback mode (0:None, 1:SERDES, 2:ILG/OLG)

lbklink <id> <tx> <rx> : execute serdes loopback link test

link <id> <link> <state> : set link state (0:Disable, 1:Enable)
linkrst <id> <link>

: reset link

pre <id> <link> <mode> : set pre-emphasis (mode:0-3)

pstat <id>
re <id> <reg>
regdef <id>
regdump <id>
regrw <id>
sstat <id>

: dump POS3 statistics

: read UB2G5NP register
: execute register default value test
: dump UB2G5NP registers
: execute register read/write test
: dump SERDES statistics

swov <id> <ch>

unload
ver

: execute switchover (0:Work, 1:Protect)

: unload driver
: show API version information

wr <id> <reg> <value>

: write UB2G5NP register

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

16.9.2005

<id> = 0 - 1, <reg> = 0 - 17C

Usefull commands in testing point of viev: PSTAT, GSTAT, SSTAT

P3
P2
P1
P0

SPI-3

UB2G5NP
2.5 G
CML

QSP_BP

GSTAT
SSTAT

PSTAT

PSTAT (POS3 statistics):

000B-$ /mnt/integration/ubi pstat 0
UB2G5NP ID 0 POS3 Statistics----------------------total cells: egress 0x000BDECD ingress 0x000BDECD
Dropped cells: egress 0x00000000 ingress 0x00000000
Errored cells: egress 0x00000000 ingress 0x00000000

GSTAT (UB global statistics):

UB2G5NP ID 0 Global Statistics
-----------------------------Device configuration:
rMPI_CFG0:

0x01014280

Egress Link status:

rMPI_CFG17:

0x0101ffff

rMPI_CFG18:

0x00010000

rMPI_CFG19:

0x0000ff01

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INSTRUCTIONS
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Niila Rautanen
Pasi Helin

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Total ingeress counts:

rINGR_DEQ_CNT: 0x00109a36
rINGR_DROP_CNT: 0x00000000
Explanations:
rINGR_DEQ_CNT = Count of the cell dequeues on the ingress side for all links.
rINGR_DROP_CNT = Count of the number of cells dropped on the ingress side.
Each of Egress Link status has 32 bits, divided to 4 bytes.
Link number is indicated by bit number in byte. Least significant bit is link 0 and most significant bit is
link 7.
rMPI_CFG17 = 1.byte: Link Up, 2.byte: Link Good, 3.byte: Link Down, 4.byte: Link Bad
rMPI_CFG18 = 1.byte: FIFO Overrun, 2.byte: Data Error, 3.byte: BIP Error, 4. byte: Sequence Error
rMPI_CFG19 = 1.byte: Cell BIP8 Error, 2.byte: Excessive Sequence Error, 3.byte: Loss of Clock,
4.byte: Receiver RDI

SSTAT (serdes statistics):

Link rINGR_DEQ_LNK rCH0_ECELL_CNT rCH0_RXDATA_ERR rCH0_B1_ERR
0

0x00109C34

0x000BF24B

0x00000000

0x00001473

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00109C34

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Explanations:
Link = Link number (only 0 - 3 in use in SF20)
rINGR_DEQ_LNK = Count of the cell dequeues on the ingress side.
rCH0_ECELL_CNT = Counts all egress cells received including error cells but excluding idle cells.
rCH0_RXDATA_ERR = Counts all egress cells received that have errors.
rCH0_B1_ERR = Counts all egress cells received that have a frame B1 byte error.

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin
4.

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PI40SAX
Compared to existing SF10 plug-in unit the main new HW is the new Switch fabric device
PI40SAX in HW block SFB40, which replaces the multistage fabric configuration of two PIx
and three PIc devices (HW block SFB10) with one standalone device.
PIR4ST command line options:
cap

: capture cell

cr <counter> : read counter (A:all)

csel <counter> <class> <qpc> <mc> <qp> : set counter selection
debug

: start Agere Debug Monitor

fopi <value> : set FOPI switchover bit

gstat

: dump global statistics

init <state> : initialize PI40SAX (1:HW reset, 2:fabric, 3:regtest, 5:memtest, 6:Agere)
ins <rqn> <dest>

: insert cell

link <link> <state>

: set link state (link 20:all) (0:Disable, 1:Enable)

linkrst <link>

: reset link

loop <rx> <tx> <lb>

lstat

: set SERDES loopback

: dump link statistics

memtest

: execute external SDRAM memory test

mirror <work> <protect> : select ports for mirroring

mirset <state>

: set port mirroring (0:Disable, 1:Enable)

pre <link> <mode>

: set pre-emphasis (0:no, 1:12%, 2:18%, 3:24%, 4:30%)

queue <number>

: initialize queue (FFF:all)

re <reg>

: read PI40SAX register

rate <link> <cps>

: set port rate to cells/sec

serdes <link> : execute SERDES test

setcap <rqn> <state> : set capture match (0:Disable, 1:Enable)
snake <cells> <lb>

: execute snake test

swov <port1> <port2> : port switchover

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

16.9.2005

unload
ver

: unload driver
: show API version information

wr <reg> <value>

: write PI40SAX register

<reg> = 0 - 4E, <link> = 0 - 1F

<lb> = loopback 0:ILG/OLG, 1:SERDES, 2:External

Usefull commands in testing point of viev: GSTAT, LSTAT

SFB40

P31
P30
P29

PI40SAX

P3
P2
P1
P0

GSTAT
LSTAT

GSTAT (PI40SAX global statistics):

Device version

: 0x20

Global Intr Status Low : 0x00048039

Global Intr Status High : 0x00000031
Multicast GBW Count

: 0x00000000

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INSTRUCTIONS
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Niila Rautanen
Pasi Helin

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Multicast BE Count
Unicast GBW Count
Unicast BE Count

: 0x00000000
: 0x000DC037
: 0x00000000

Cell Dequeue Count

: 0x000DC037

Dropped Cell Count

: 0x000003CE

Explanations:
Device version = Version number of PI40SAX chip.
Global Intr Status Low = Status bits for various errors.
Global Intr Status High = Status bits for various errors.
Multicast GBW Count = Counts the total number of multicast guaranteed bandwith cells enqueued.
Multicast BE Count = Counts the total number of multicast best effort bandwith cells enqueued.
Unicast GBW Count = Counts the total number of unicast guaranteed bandwith cells enqueued.
Unicast BE Count = Counts the total number of unicast best effort bandwith cells enqueued.
Cell Dequeue Count = Count of the total number of cells dequeued by the device.
Dropped Cell Count = Counts the total number of cells that are not idle cells and that are dropped due
to invalid cell format or receive data errors

LSTAT (link statistics):

# LINK_CFG

LINK_STAT

CELL_ERR LINK_ERR

00 00:50:42:33 00:00:81:9C 0xFFFF 0x000B

01 00:C0:42:32 00:00:62:00 0x0000 0x0000
02 00:C0:42:32 00:00:62:00 0x0000 0x0000
03 00:C0:42:32 00:00:62:00 0x0000 0x0000
04 00:C0:42:32 00:00:62:00 0x0000 0x0000
05 00:C0:42:32 00:00:62:00 0x0000 0x0000
06 00:C0:42:32 00:00:62:00 0x0000 0x0000
07 00:C0:42:32 00:00:62:00 0x0000 0x0000
08 00:C0:42:32 00:00:62:00 0x0000 0x0000
09 00:C0:42:32 00:00:62:00 0x0000 0x0000
0A 00:C0:42:32 00:00:42:00 0x0000 0x0000
0B 00:C0:42:32 00:00:42:00 0x0000 0x0000
0C 00:C0:42:32 00:00:42:00 0x0000 0x0000

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Niila Rautanen
Pasi Helin

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0D 00:C0:42:32 00:00:42:00 0x0000 0x0000

0E 00:C0:42:32 00:00:42:00 0x0000 0x0000
0F 00:C0:42:32 00:00:42:00 0x0000 0x0000
10 00:C0:42:32 00:00:42:00 0x0000 0x0000
11 00:C0:42:32 00:00:42:00 0x0000 0x0000
12 00:C0:42:32 00:00:42:00 0x0000 0x0000
13 00:C0:42:32 00:00:42:00 0x0000 0x0000
14 00:C0:42:32 00:00:42:00 0x0000 0x0000
15 00:C0:42:32 00:00:42:00 0x0000 0x0000
16 00:C0:42:32 00:00:42:00 0x0000 0x0000
17 00:C0:42:32 00:00:42:00 0x0000 0x0000
18 00:C0:42:32 00:00:42:00 0x0000 0x0000
19 00:C0:42:32 00:00:42:00 0x0000 0x0000
1A 00:C0:42:32 00:00:42:00 0x0000 0x0000
1B 00:C0:42:32 00:00:42:00 0x0000 0x0000
1C 00:C0:42:32 00:00:42:00 0x0000 0x0000
1D 00:C0:42:32 00:00:42:00 0x0000 0x0000
1E 00:C0:42:32 00:00:42:00 0x0000 0x0000
1F 00:C0:42:32 00:00:42:00 0x0000 0x0000
Explanations:
CELL_ERR = Count of cell errors (CELL_BIP_ERR and SEQ_ERR) that have been detected on the
link.
LINK_ERR = Count of link errors (B1_BIP_ERR only) that have been detected on the link.

5.

ORT8850
The OR8DRI driver is a Chorus device driver (supervisor actor) belonging to the feature
50211. It was originally designed for managing the SD4G HW block of former switch fabric
version SF10, in which the backplane driver HW is implemented with ORT8850H devices
having a programmable code called G+.
In new SF20 (and SF20DEV) the SD4G HW block is modified to SD4G-A and the
ORT8850H devices have a modified programmable code called G++.

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

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The service terminal for testing ORT8850H chip is called or8tst and here are current
commands:

or8tst -i [-C <ChipId>]

or8tst -a -A <Activity>
or8tst -r
or8tst -e -P <Port> -F <Interface> -A <Activity>
or8tst -s -P <Port> [-F <Interface>]
or8tst -c -P <Port> -F <Interface>
or8tst -v -P <Port> -F <Interface>
or8tst -d -C <ChipId> -R <RegisterIndex>
or8tst -w -C <ChipId> -R <RegisterIndex> -V <RegisterValue>
or8tst -f [-M <Mode>] -C <ChipId> -D <ChipId> [-f]
or8tst -l -P <Port> -D <Dest port> -c <Class> -A <Activity> [-N]
or8tst -fi -P <Port> [-f|-s]
or8tst -info [-C <ChipId>|-P <Port>]
or8tst -disp -C <ChipId>
or8tst -reg -C <ChipId> [-r <rounds>]
or8tst -intr [-C <ChipId>] -F <0=disable, 1=enable>
or8tst -lo -C <ChipId> -A <Activity>

Main Options:
-i

= initialize the hardware

-a

= set fabric activity

-r

= read fabric activity

-e

= enable interface

-s

= set switch handling

-c

= check test cell arrival

INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin

16.9.2005

-v

= read cable information

-d

= read register

-w

= write register

-f

= load FPGA (from special file)

-l

= set loop back enabled or disabled

-fi

= fifo init

-info

= information about the interfaces

-disp

= display backpressure table

-reg

= perform register default/rw check

-intr

= enable/disable interrupts

-lo

= set loop back enabled on backplane side

Parameter Options:
-A <Activity>

= activity info (1 = active/enabled))

-F <Interface>
-P <Port>

= interface id (0 or 1)
= port number (0 ... 7)

-M <Mode>

= mode 1 (1 GBit Mode, def) or 4 (4 GBit)

-C <ChipId>

= Chip id. First chip to implement the mode

-D <ChipId>

= Second chip to implement the mode

-D <Dest port>
-N

= Loopback destination (0 ... 3F)

= near end loopback (default far end)

-R <RegisterIndex> = register index

-V <RegisterValue> = register value
-f

= operation is forced

-s

= make F_SYNC operation

-c <class>

= Class (0 ... 3)

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INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin
6.

UXASIC
Needs to be updated.

16.9.2005

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INSTRUCTIONS
Tomi Cederqvist
Niila Rautanen
Pasi Helin
7.

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16.9.2005

LOOPBACKS
There are several points where traffic can be looped inside plug-in unit. Following picture
illustrates typical cases needed in integration / testing. There are also other loopback
possibilities which can be found more detailed in SF20 IS document.

SF20
PPC7

UX1-A
UTOPIA L1

MPC8280

UX
FPGA

MII

ETH-A
LXT9712

SFB40

P31
P30
P29

P3
G++

(secondary)

P2

PI40SAX

SD4G-A
P3
P2
P1
P0

SPI-3

QSP_BP

P1
G++

UB2G5NP
2.5 G
CML

MI

(primary)

P0

1. PID (loop) loopback mode:

0:ILG/OLG = Internal loopback mode for looping cells inside PI40SAX.
1:SERDES = External loopback mode for looping ingress cells back to UB2G5NP.
2:External = PI40SAX loopback disabled.
2. UBI (lb) loopback mode:
0:ILG/OLG = Internal loopback mode for looping cells inside PI40SAX.
1:SERDES = External loopback mode for looping ingress cells back to UB2G5NP.

INSTRUCTIONS
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Niila Rautanen
Pasi Helin

16.9.2005

2:External = PI40SAX loopback disabled.

3. ORT backplane loopback mode:

ort8tst lo C <chip> -A <1 = enabled, 0 = disabled>

8.

TIPS & TRICKS

To be updated:

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