SEE1223: Digital Electronics

6 Counters and Registers

Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The Faculty of Electrical Engineering Universiti Teknologi Malaysia

Counter and Registers

Counters
Asynchronous Counters Synchronous Counters Design of Synchronous Counters 74163 devices

Registers
Shift Registers
SISO, SIPO, PISO, PIPO

Shift Register Counters

Johnson and Ring

74164, 74165, 74194, and 74195 devices

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Introduction to Counters
Counters Circuit that performs the operation of counting at every clock edge
3-bit Counter
Q2 Q1 Q0 CLR

Clear output If CLR = 0 Q2Q1Q0 = 000 Increment by 1 at every Else if CLR = 1 Negative edge of clk if clk = Q2Q1Q0 = Q2Q1Q0 + 001 else Q2Q1Q0 = Q2Q1Q0 Maintain previous value

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A.A.H Ab-Rahman, Z.Md-Yusof

Introduction to Counters (cont.)

Draw the output waveforms Q2, Q1 and Q0 for a negative edge triggered 3-bit counter with active low clear
clk

CLR

Q2

Q1

Q0
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Introduction to Counters (cont.)

Counter are designed using flip-flops, typically the negative edge triggered Counters can be designed as asynchronous or synchronous Asynchronous counters The clock is applied on the first stage. Subsequent stages derive the clock from the previous stage Synchronous counters The clock is applied to all stages using a common clock signal Synchronous counters perform better than asynchronous counters, therefore, are widely used in digital systems
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Asynchronous Counters
3-bit asynchronous counter using T Flip-flops
Q0 Q1 Q2 1 clk T Q Q 1 T Q Q 1 T Q Q

CLR CLR

CLR

CLR

Stage 1

Stage 2

Stage 3

In asynchronous counters, the clk signal is fed to the 1st stage only. Subsequent stages takes the Q from the previous stage for clk Can you draw the waveform for Q2, Q1 and Q0 for 8 clock cycles? Can you identify the problem with asynchronous counters? 2/18/2012 A.A.H Ab-Rahman, Z.Md-Yusof

Synchronous Counters
3-bit Synchronous Counter using T Flip-flops
Q1 Q0 Q2

1 clk

Q Q

Q Q

Q Q

CLR CLR

CLR

CLR

In synchronous counters, a common clk signal is used to clock all flip-flops Can you draw the waveform for Q2, Q1 and Q0 for 8 clock cycles? Why is the synchronous counter superior to asynchronous counters? 2/18/2012 A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

How to design the 3-bit synchronous counter?
There is a systematic procedure of designing synchronous counters
Step 1: Derive the state transition diagram Step 2: Derive the next state and state transition table Step 3: Using K-Maps, derive the logic expressions Step 4: Implement the circuit

2/18/2012

A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

The design of negative edge triggered 3-bit synchronous counter using T Flip-flops
Step 1: Derive the state diagram
CLR=0

State 001 goes to state 010 at negative edge of clk

000 001

State 110 goes to state 111 at negative edge of clk

111

010

110

011

101
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100
9

A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

Step 2: Derive the next state and state transition Using T flip-flops table 3-bit counter, we need 3 flip-flops
Present State Next State Q2 Q1 Q0
0 0 0 0 1 1 1 1
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Output Transition Q2 Q1 Q0
00 0 0 0 1 00 0 1 1 0 00 1 1 0 1 01 1 0 1 0 11 0 0 0 1 11 0 1 1 0 11 1 1 0 1 10 1 0 1 0

Flip-flop Inputs T2 T1 T0
0 0 0 1 1 1

Q2 Q1 Q0
0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0
1 0 0

0
1 0 1

1
1 1 1

0
1

0
1

1
1
10

A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

Step 3: Using K-Maps, derive the logic expressions
Q1Q0 00 Q2

Present state
01 11 10

K-Map for T2

0 0

0 0
01

1 1
11

0 0
10

T2 Q1 Q0

Q1Q0 00 Q2

K-Map for T1

0 1

0 0

1 1
01

1 1
11

0 0
10

T1 Q0

Q1Q0 00 Q2

K-Map for T0
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0 1

1 1

1 1

1 1

1 1

T0 1
11

A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

Step 4: Implement the circuit
Q1 Q0 Q2

1 clk

Q Q

Q Q

Q Q

CLR CLR

CLR

CLR

T0 1
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T1 Q0
Which is the same Z.Md-Yusofas before circuit A.A.H Ab-Rahman,

T2 Q1 Q0
12

Design of Synchronous Counters

Implement the following counter using D Flipflops and basic gates
0000

The counter starts at 0, at next edge of clk goes to 3

0011

The counter counts with the Sequence of 3-9-5-1

1001

0001

0101

How many D Flip-flops do we need? => 4

Next step: Derive the next state and state transition table
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Design of Synchronous Counters

Next state and state transition table
Present State Next State Q3 Q 2 Q1 Q0 Q3 Q2 Q 1 Q0
0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1

Output Transition Q3 Q2 Q1
0-0 0-0 0-1 0-1 0-0 0-0 0-1 1-1 0-1 0-0 1-0 1-1 0-0 1-0 0-0 1-1 1-0 0-1 0-0 1-1

Flip-flop Inputs
0 0 0 0 1 1 1 1

Q0 D 3 D 2 D 1 D 0

1
0 0

0
0 1

0
0 0

1
1 1

Taking the present state as inputs, use K-Maps to find D3, D2, D1, and D0 Use dont care conditions when necessary
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Design of Synchronous Counters

Q1Q0 00 Q3 Q2

Present state
01
11 10

00
01

Q1Q0 00 Q3 Q2 00 01 11 10

01

11

10

0 0 x 0
01

1 x x x
11

0 x x x

0 0 x 1

0 x x x
11

x x x x
10

x
x x

x
x x
10

K-Map for D3

11
10

D3 Q1

K-Map for D2

D2 Q3

Q1Q0 00 Q3 Q2 00 01 11 10
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1 x x x

x x x x K-Map for D1

Q1Q0 00 01 Q3 Q2 00 1 1 01

1 x x x

x x x x
15

0
x 0

x
x x

x
x x

1 x 1

D1 Q3 Q2 Q1

11

K-Map for D0

D0 1

Q3 Q2 Q110
A.A.H Ab-Rahman, Z.Md-Yusof

Design of Synchronous Counters

Final step: Circuit implementation

Q0

Q1

Q2

Q3

Q Q

Q Q

Q Q

Q Q

clk

CLR CLR

CLR

CLR

CLR

D0 1
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D1 Q3 Q2 Q1

D2 Q3

D3 Q1
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A.A.H Ab-Rahman, Z.Md-Yusof

Counter IC (cont.)
The 74163 device: 4-bit Synchronous counter
Counts from 0 to 15
reset
clk Data input enable Terminal count Counter output enable enable Refer to datasheet for details
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