1 - Determination of Pull-up to Pull-down ratio for nMOS Inverter driven by another nMOS Inverter.

Assume equal margins around inverter; Vinv = 0.5 Vdd Assume both transistors in saturation, therefore: Ids = K (W/L) (Vgs Vt)2/2 Depletion mode transistor has gate connected to source, i.e. Vgs = 0 Ids = K (Wpu/Lpu) (-Vtd)2/2 Enhancement mode device Vgs = Vinv, therefore Ids = K (Wpd/Lpd) (Vinv Vt)2/2 Assume currents are equal through both channels (no current drawn by load) (Wpd/Lpd) (Vinv Vt)2 = (Wpu/Lpu) (-Vtd)2 Convention Z = L/W Vinv = Vt Vtd / (Zpu/Zpd)1/2 Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inverter

2 - BiCMOS Inverters
Simplified BiCMOS Inverter

Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-type devices, OFF at Vin=0V). The MOS switches perform the logic function & bipolar transistors drive output loads.

Basic Operation: When Vin = 0 : T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to Vdd - Vbe (of T4) Note : Vbe (of T4) is base-emitter voltage of T4. (pullup bipolar transistor turns off as the output approaches 5V - Vbe (of T4)) When Vin = Vdd : T2 is off.Therefore T4 is non-conducting. T1 is on and supplies current to the base of T3 T3 conducts & acts as a current sink to discharge load CL towards 0V. Vout falls to 0V+ VCEsat (of T3) Note : VCEsat (of T3) is saturation V from T3 collector to emitter

Conventional BiCMOS Inverter: Two additional enhancement-type nMOS devices have been added (T5 and T6). These transistors provide discharge paths for transistor base currents during turnoff. Without T5, the output low voltage cannot fall below the base to emitter voltage VBE of T3.

Basic Operation:

When Vin = 0 : T1 is off. Therefore T3 is non-conducting T2 ON - supplies current to base of T4 T4 base voltage set to Vdd. T5 is turned on & clamps base of T3 to GND. T3 is turned off. T4 conducts & acts as current source to charge load CL towards Vdd. Vout rises to Vdd - Vbe (of T4) When Vin = Vdd : T2 is off T1 is on and supplies current to the base of T3 T6 is turned on and clamps the base of T4 to GND. T4 is turned off. T3 conducts & acts as a current sink to discharge load CL towards 0V Vout falls to 0V+ VCEsat (of T3)

3 - Scaling of MOS Circuits

What is Scaling? Proportional adjustment of the dimensions of an electronic device while maintaining the electrical properties of the device

Impact of scaling is characterized in terms of several indicators: Minimum feature size Number of gates on one chip Power dissipation Maximum operational frequency Die size Production cost

Scaling Models: 1) Full Scaling (Constant Electrical Field) Ideal model dimensions and voltage scale together by the same scale factor 2) Fixed Voltage Scaling Most common model until recently only the dimensions scale, voltages remain constant 3) General Scaling Most realistic for todays situation voltages and dimensions scale with different factors.

4 - CAD Tools for VLSI Design and Simulation:

Evolution Of CAD Tools Digital circuit design evolved over last three decades SSI Small Scale Integration (Tens of transistors) MSI Medium Scale Integration (Hundreds of transistors) LSI Large Scale Integration (Thousands of Transistors) demanded automation of design process CAD started evolving VLSI Very Large Scale Integration Tens of Thousands of Transistors CAD Tools are inevitable VLSI chip design forced Automation of process Automation of Simulation based verification - replacing breadboard techniques HDL development Modular and Hierarchical techniques of design a natural object orientation approach CAD Terminologies HDL Hardware Description Language Describing a circuit to the computer A programming language by all means Concurrency constructs to simulate circuit behavior Verilog and VHDL Simulation for verification and Synthesis Synthesizable constructs - RTL RTL Register Transfer Level Specifying how the data flows between registers and how the design processes data Registers store intermediate results Logic between any two registers in a data flow determines the speed of the circuit Synthesis Converting RTL to a set of gates and wires connecting them Ambit of Cadence, Design Compiler of Synopsys, Precision of Mentor, Blast Fusion from Magma are some of the commercially available synthesis tools.

5 - Gallium Arsenide (GaAs) Fabrication

Although there are various approaches that are currently used, high-pressure liquidencapsulated Czochralski (LEC) growth of gallium arsenide crystals from high purity pyrolytic boron nitride (PBN) The sequence for GaAs wafer preparation is very similar to that of silicon wafer preparation technique. The first step involves mechanically grinding the As-grown boules to a precise diameter and incorporating orientation flats. This is followed by Wafering using a diamond ID saw Edge rounding Lapping Polishing Wafer Scrubbing