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m00 m02 m04 m05 m10 m08 m12 m13 m35 m43
1 x x x 0 0 0 0 0 x
0 x 0 0 1 1 1 1 1 1
0 x x x 0 0 0 0 1 x
1 0 0 0 1 1 1 1 1 0
0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 1
0 1 1 1 0 0 0 0 0 0
0 x 0 0 0 0 1 1 0 0
1 x 0 0 0 0 1 0 0 0
0 x 1 1 1 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0
Each of the bits is read vertically to derive the actual composition expression: RegDst ALUSrc MemToReg RegWrite MemRead MemWrite Branch ALUOP2 ALUOP1 ALUOP0 (Op5 + Op4 + Op3 + Op2 + Op1 + Op0) Op3 + Op1 Op5.Op4.Op3.Op2.Op1.Op0 (Op5+Op4+Op3+Op2+Op1+Op0).(Op5+Op4+Op3+Op2+Op1).(Op5+Op4+Op3+Op2+Op1+Op0) Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1 (Op5.Op4.Op3.Op2.Op1.Op0) + (Op5.Op4.Op3.Op2.Op1.Op0) (Op5.Op4.Op3.Op2.Op1.Op0) + (Op5.Op4.Op3.Op2.Op1.Op0)
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CS2100: Assignment 2 Gan Soon Bing A0073817Y BranchNE Jump SLTI Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0 Op5.Op4.Op3.Op2.Op1.Op0
The diagram below describes the logical layout of the Control Unit:
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Each of the outputs: E, S, AND/OR, NOT/PASSTHROUGH, ARITHMETIC/LOGIC are expressed in terms of the inputs ALUOP and Funct. E S AND/OR NOT/PASS ARITHMETIC/LOGIC 0 (Op2+Op1+Op0+F5+F4+F3+F2+F1+F0).(Op2+Op1+Op0) (Op2+Op1+Op0+F5+F4+F3+F2+F1+F0).(Op2+Op1+Op0) Op2+Op1+Op0+F5+F4+F3+F2+F1+F0 (Op2.Op1.Op0.F5.F4.F3.F2) + (Op5.Op3)
The ALU Control Unit is then created as per the following diagram:
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To mimic the original MIPS processing of word addressing, the addresses of the RAM already address 32-bits of data. Thus each increment of 1 in the address will automatically address 4 bytes of data; Hence in this implementation, the PC counter is incremented by 1, instead of by the usual 4.
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Thus, if it so happens that the Branch flag is on, and the result of the operation in the ALU raises the Zero flag (i.e. the 2 input values to the ALU are equal), then the selector will assert, and the output of the multiplexer will be from the PC + 1 + sign-extended Instr[15-0]. Similarly, if the BranchNE flag is on, and the result of the operation fails to raise the Zero flag, the multiplexer will assert, and the output of the multiplexer will be from the PC + 1 + sign-extended Instr[15-0]. The output from the multiplexer then goes to another multiplexer, which chooses between the output mentioned in the paragraph above, and the zero-extended value of the jump immediate. The selector is linked to the Jump flag output from the Control Unit. If this is asserted, the value of the jump immediate is passed through instead of the output from the previous paragraph, such that at
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CS2100: Assignment 2 Gan Soon Bing A0073817Y the next clock cycle, the RAM will access the instruction at the address listed in the jump immediate.
The instructions that are output from the Instruction Memory are 32-bits, of which the first 6 bits (31-26) constitute the OpCode. This is passed as an input to the Control Unit so that the flags for the rest of the circuit are set accordingly. Page | 10
CS2100: Assignment 2 Gan Soon Bing A0073817Y The next 5 bits (25-21) consist of the rs portion of the instruction. This indicates which register to read the data from, and is connected directly to the first multiplexer in the register file. Similarly, the 5 bits after that (20-16) is rt portion of the instruction, and also indicates which register to read the data from. This is connected directly to the second multiplexer in the register file. Coincidentally, the 5-bits (20-16) is also connected to a multiplexer that controls which register would be written to. The other input to the multiplexer comes from 5-bits of the instruction (15-11). A selector for the multiplexer is connected to RegDST output of the Control Unit, which would raise the flag to select from the rd field of the instruction as the destination for register-type operations. If RegDST is not asserted, then the destination comes from the rt field of the instruction. Externally, the register file is connected to the 3 inputs listed in the previous 2 paragraphs. In addition to that, a special RegWrite flag form the Control Unit decides whether the register file is written to or not. The bottom right side of the register file contains the 2 32-bit outputs from the registers that have been requested to be read from. The bottom left contains the input data (32-bits) to be written to the register. The Funct field applies only for register type instructions, and is extracted from the last 5-bits of the instruction (5-0). This is connected to the ALU Control unit as part of its input to determine the final operation for the ALU unit. In addition, the last 16-bits of the instruction contain the immediate values for immediate operations, and are extended to 32-bits. Sign-extension is used for immediates used for arithmetic processing, while zero-extension is used for immediates that would be used for logic processing in the ALU. The multiplexer that controls this is selected by the ARITHMETIC-LOGIC output from the ALU Control Unit. The jump immediate is the last 26 bits of the instruction (25-0), and is extracted to be used in determining which instruction should be executed in the next clock cycle.
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CS2100: Assignment 2 Gan Soon Bing A0073817Y On the Data Memory unit, the data port is connected to the first output from the register file, effectively retrieving the 32-bit value stored in the register number specified by the rs field of the instruction. The MemWrite flag controlled by the Control Unit decides whether the Data Memory is to be written to. The MemRead flag is similarly controlled by the Control Unit to decide whether the Data Memory should operate.
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A0073817Y.circ
This file contains the adder/subtractor/negator as built in Assignment 1, and is used as a library in the main circuit file.
ALU.circ
This file contains the combination of the original adder/subtractor/negator, added with logic operations to create a semi-complete ALU. Shifting is not within the scope of this assignment, and hence will not be included.
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Test Case 1:
The following test case attempts to test the proper functionality for the following implemented instructions: addi/add/sub/and/andi/or/ori/slt/bne. The state of the first 10 registers after each instruction has been executed is also listed in the table. Instruction addi $1, $0, 1 addi $2, $0, 3673 add $3, $1, $2 addi $4, $1, 7 sub $5, $3, $4 addi $4, $4, -1 and $6, $5, $4 andi $7, $5, 255 or $8, $5, $1 ori $9, $8, $9 slt $10, $8, $9 nor $10, $1, $10 bne $8, $9, -12 Encoded 20010001 20020E59 00221820 20240007 00642822 2084FFFF 00A43024 30A700FF 00A14025 3509000C 0109502A 002A5027 1509FFF3 $1 1 1 1 1 1 1 1 1 1 1 1 1 1 $2 0 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 3673 $3 0 0 3674 3674 3674 3674 3674 3674 3674 3674 3674 3674 3674 $4 0 0 0 8 8 7 7 7 7 7 7 7 7 $5 0 0 0 0 3666 3666 3666 3666 3666 3666 3666 3666 3666 $6 0 0 0 0 0 0 2 2 2 2 2 2 2 $7 0 0 0 0 0 0 0 82 82 82 82 82 82 $8 0 0 0 0 0 0 0 0 3667 3667 3667 3667 3667 $9 $10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3679 3679 1 3679 -2 3679 -2
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Test Case 2:
The following test case attempts to test the proper functionality for the following implemented instructions: sw/slt/lw/beq/j. j7 addi $1, $0, 100 addi $4, $0, 16 sw $1, -4($4) lw $2, -4($4) add $3, $1, $2 slt $5, $2, $3 slti $6, $2, 101 beq $4, $1, -7 08000008 20010064 20040010 AC81FFFC 8C82FFFC 00221820 0043282A 28460064 1022FFF8 Jump to instruction at address 8 $1 = 100 $4 = 16 M[12] = 100 $2 = 100 $3 = 200 $5 = 1 $6 = 1 Jump to instruction at address 9 8 = 1 0 1 2 3 4 5 6 7 8
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