1. INTRODUCTION 1.

1General Our project deals with the requirements for the design of digital companding technique for audio signal. By the use of companding, the dynamic range can be extended. Since pulse-code modulation is a digital method, it is well suited to the use of digital companding techniques. The binary transmitted signal normally contains a measure of the system performance. By observing certain patterns in this binary signal and using the occurrence or nonoccurrence of these patterns to discard the least significant bits syllabic companding can be obtained. The selection of the binary pattern and the rate of change of gain of the modulator and demodulator, determines both the point at which the companding operates and the attack and decay times. 1.2Companding The data rate is important in telecommunication because it is directly proportional to the cost of transmitting the signal. Companding is a common technique for reducing the data rate of audio signals by making the quantization levels unequal. As previously mentioned, the loudest sound that can be tolerated (120 dB SPL) is about one-million times the amplitude of the weakest sound that can be detected (0 dB SPL). However, the ear cannot distinguish between sounds that are closer than about 1 dB (12% in amplitude) apart. In other words, there are only about

120 different loudness levels that can be detected, spaced logarithmically over an amplitude range of one-million. This is important for digitizing audio signals. If the quantization levels are equally spaced, 12 bits must be used to obtain telephone quality speech. However, only 8 bits are required if the quantization levels are made unequal, matching the characteristics of human hearing. This is quite intuitive: if the signal is small, the levels need to be very close together; if the signal is large, a larger spacing can be used. Companding can be carried out in three ways:
1. Run the analog signal through a nonlinear circuit before reaching a

linear 8 bit ADC,

2. Use an 8 bit ADC that internally has unequally spaced steps 3. Use a linear 12 bit ADC followed by a digital look-up table (12 bits

in, 8 bits out). 1.3 Human Acoustics and the Telephone Network By classifying according to the mode of excitation, speech sounds can be broken into three distinct classes of phonemes, where a phoneme is defined as the smallest unit of speech that distinguishes one utterance from another. The three classes of phonemes are voiced, unvoiced, and plosives. Voiced phonemes are considered deterministic in nature. They are produced by forcing air through the glottis with the tension of the vocal cords adjusted so that they vibrate in a relaxed oscillation. This produces quasi-periodic pulses of air which excite the vocal tract.

Examples of voiced phonemes are the vowels, fricatives /v/, and /z/, and stop consonants /b/, /d/, and /g/. Unvoiced phonemes are generated by forming a constriction at some point in the vocal tract and forcing air through the constriction at a high enough velocity to produce turbulence. As a result, unvoiced phonemes are considered random in nature. Examples of unvoiced phonemes are the nasal consonants /m/, and /n/, fricatives /f/, and /s/, and stop consonants /p/, /t/, and /k/. Similar in nature to unvoiced sounds, plosive sounds result from making a complete closure of the vocal tract, building up pressure behind the closure, and abruptly releasing it, such as the /ch/ phoneme. Naturally occurring speech signals are composed of combinations of voiced, unvoiced and plosive phonemes. For example, contained in Figure 1.1 is the speech signal goat, which contains two voiced phonemes /g/ and /oa/, followed by a partial closure of the vocal tract, and then an unvoiced phoneme, /t/. The /g/, /oa/, and /t/ occur approximately at samples 3400-3900, 3900-5400, and 6300-6900, respectively.

Figure 1.1: Sample Speech Signal Each phoneme class brings its own stress to the telephone system. In general, the peak to peak amplitude of voiced phonemes is approximately ten times that of unvoiced and plosive phonemes, as clearly illustrated in Figure 1. As a result, the telephone system must provide for a large range of signal amplitudes. Although lower in amplitude, unvoiced and plosive phonemes contain more information and thus, higher entropy then voiced phonemes. Thus, the telephone system must provide higher resolution for lower amplitude signals. In addition to the tasks presented by the speech signal, the telephone network is also subject to bandwidth restrictions with respect to the human speech and auditory ranges. The speech bandwidth for most adults is approximately 10 kHz. In contrast, the maximum auditory range of humans is 20 kHz. This maximum auditory range is usually limited to young children; instead, the typical hearing bandwidth for most adults is 15 kHz.
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Of the speech and auditory bandwidths, the telephone network restricts transmission to a 3 kHz portion, from .3 to 3.3 kHz. This frequency range is believed to coincide with the region of greatest intelligible speech, retaining only the first three formant frequencies of the sampled speech signal. This reduced bandwidth is then surrounded by unused space from 0 to .3 kHz and from 3.3 to 4 kHz. This unused space, known as the guard band, provides a buffer against conversation interference. Summing the transmission and guard bands, the telephone network has a total bandwidth of 4 kHz. In summary, the telephone system must provide adequate quality for small amplitude signals consisting of unvoiced phonemes. Concurrently, the telephone system must provide for transmission of a wide range of signal amplitudes, due to the occasional occurrence of high energy voiced phonemes. The accomplishment of these concurrent tasks, within a limited bandwidth, may be achieved via Pulse Code Modulation and companding, as discussed in the following section. 1.4. Pulse Code Modulation and Companding At the telephone transmitter, human speech is converted to analog signals. For digital transmission, this analog signal is converted to a digital signal, which has a fixed precision. To provide higher voice quality at a lower cost, the analog signals may be converted to digital signals using Pulse Code Modulation (PCM). PCM is composed of three successive steps: sampling, quantizing and coding. Sampling is the
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determination of a signals amplitude at regular time intervals. Since the telephone network has a bandwidth of 4 kHz, for accurate reproduction, a voice signal must be sampled at a rate of at least 8 kHz, according to Nyquists theorem. That is, the amplitude of the signal is sampled every 125 s. Once the signals amplitude is obtained, it is quantized into a discrete set of amplitude levels for representation as a digital signal. Quantization is achieved by dividing the bandwidth of the system into quantization intervals, also known as bins. All signal amplitudes falling within a bin are represented by the midpoint of that quantization interval. The quantization process introduces quantization error into the digital signal; however, the introduced error may be minimized by minimizing the width of the bins with respect to the number of bits needed to uniquely identify the quantization bins. Finally, coding of the signal is performed by converting the midpoint of each quantization level to a codeword. In general, speech signals are composed of relatively fewer voiced phonemes than unvoiced phonemes. Unfortunately, the uniform quantizer, which has equally spaced zones, provides unneeded quality for large signals which are least likely to occur, and pronounced truncation effects for the more frequent small amplitude signals. As a result, uniform quantization does not perform as well as a quantizer with wider zones at high amplitudes and narrower zones at lower amplitudes. Instead of employing uniform quantization, a natural non-uniform substitute is observed in the human auditory system. It is believed that the human auditory system is a logarithmic process in which high amplitude sound does not require the same resolution as low amplitude sound.
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Conversion to a logarithmic scale allows quantization intervals to increase with amplitude, and it insures that low-amplitude signals are digitized with a minimal loss of fidelity. Fewer bits per sample are necessary to provide a specified signal-to-noise ratio (SNR) for small signals and an adequate dynamic range for large signals. Non-uniform quantization may be achieved by first passing the message through a compressor, a nonlinear device which compresses the peak amplitudes. This is followed by a uniform quantizer, such that uniform zones at the output correspond to non-uniform zones at the input. At the receiving end, the compressed signal is passed through an expander, another nonlinear device used to cancel the nonlinear effect of the compressor. The combined process is known as companding. In addition to reducing quantization error, companding decreases the required bandwidth of the system. That is, systems solely employing uniform quantization require 13-bit code words for equivalent performance requirements of the telephone system. However, while increasing performance, systems using nonlinear companding may reduce the required codeword length to 8-bits or less. Companding is simply a system in which information is compressed, flowed through a channel and then expanded on the other side. Companding may be accomplished in hardware via a CODEC, or in software using a look-up table approach or a realtime direct calculation. However, if hardware companding is implemented and intermediate processing of the signal is necessary, then reverse companding is required. Two international companding standards that retain up to 5 bits of precision by encoding signal data into 8 bits are -law and A-law. law is the accepted standard of the U.S. and Japan, while A-law is the
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European accepted standard. Both international standards are discussed further in the following sections. 1.5 Speech Companding The human auditory system is believed to be a logarithmic process in which high amplitude sounds do not require the same resolution as low amplitude sounds. The human ear is more sensitive to quantization noise in small signals than large signals. A-law and m-law coding apply a logarithmic quantization function to adjust the data resolution in proportion to the level of the input signal. Smaller signals are represented with greater precision more data bits than larger signals. The result is fewer bits per sample to maintain an audible signal-to-noise ratio (SNR). Rather than taking the logarithm of the linear input data directly, which can be computationally difficult, Alaw/ m-law PCM matches the logarithmic curve with a piece-wise linear approximation. Eight straightline segments along the curve produce a close approximation to the logarithm function. Each segment is known as a chord. Within each chord, the piece-wise linear approximation is divided into equally size quantization intervals called steps. The step size between adjacent code words is doubled in each succeeding chord. Also encoded is the sign bit for the original integer. The result is an 8-bit logarithmic code composed of a 1-bit sign bit, a 3-bit chord, and a 4-bit step.

1.6 ARM Processor The ARM architecture a 32-bit RISC processor architecture developed by ARM Limited that is widely used in embedded designs. Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal.

ARM processor features include: -Load/store architecture -An orthogonal instruction set -Mostly single-cycle execution -A 16x32-bit register -Enhanced power-saving design 2. LITERATURE REVIEW

Charles W. Brokish, MTS, Michele Lewis, MTSA, SC Group Technical Marketing presented a paper in the topic A-Law and mu-Law Companding Implementations Using the TMS320C54x. In their paper they use TMS320C54x processor for companding process. We use ARM processor instead of TMS320C54x for the companding process because of its less power consumption and its powerful instruction sets.

In the book Addition Wesley- ARM SOC architectures, second edition the architecture and features of the ARM processor are clearly given. We refer in that book that ARM processor consumes less power compared to other processor. So we choose ARM processor for the companding process.

Kikkert,C. from James Cook Univ. of North Queensland, Townsville, Australia (1974) proposed a method of companding. According to him companding can be done by using delta modulation or pulse code modulation. In our project we choose pulse code modulation for companding process

3. MATHEMATICAL MODEL Two nearly identical standards are used for companding curves: 255 law (also called mu law), used in North America, and "A" law, used in Europe. Both use a logarithmic nonlinearity, since this is what converts the spacing detectable by the human ear into a linear spacing.

3.1 -Law Companding

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The U.S. and Japan use -law companding. The dynamic range of a compander may be defined as the difference in signal power between the lowest amplitude occupying the entire range of the first chord and the highest occurring amplitude. Using this definition, the dynamic range of -law companding is calculated by the following equation

Where 8159 is the largest amplitude possible and 31 is the lowest amplitude spanning the first chord. In figure 3.1 the curve for Law companding is shown.

Figure 3.1. -law Companding Curve 3.1.1 -Law Compression

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Limiting sample values to 13 magnitude bits, the -law compression portion of this standard is defined mathematically by the continuous equation.

where is the compression parameter (=255 for the U.S. and Japan), and x is the normalized integer to be compressed. During compression, the least significant bits of large amplitude values are discarded. The number of insignificant bits deleted is encoded into a special field of the compressed code format, called the chord. Each chord of the piece-wise linear approximation is divided into equally sized quantization intervals called steps. The step size between adjacent code words is doubled in each succeeding chord. Also encoded is the sign of the original integer. The polarity bit is set to 1 for positive integer values. Thus, an 8 bit -255 codeword is composed of 1 polarity bit concatenated with a 3-bit chord concatenated with a 4-bit step. Before chord determination, the sign of the original integer is removed and a bias of 33 is added to the absolute value of the integer. Due to the bias, the magnitude of the largest valid sample is reduced to 8159 and the minimum step size is reduced to 2/8159. The added bias enables the endpoints of each chord to become powers of two, which in turn simplifies the determination of the chord and step. Chord
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determination may be reduced to finding the most significant 1 bit of the binary representation of the biased integer value, while the step equals the four bits following the most significant 1. Illustrated in Table 3.1 is the translation from linear to m-law compressed data. Of the compressed codeword, bits 4-6 represent the chord and bits 0-3 represent the step. The polarity bit of the compressed codeword is not shown in this table. Finally, before transmission, the entire -law code is inverted. The codeword is inverted since low amplitude signals tend to be more numerous than large amplitude signals. Consequently, inverting the bits increases the density of positive pulses on the transmission line, which improves the hardware performance.

Table3.1 -law Binary Encoding Table

3.1.2 -Law Expansion

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-Law expansion is defined by the continuous inverse equation

Before expansion, the -law code is inverted again to restore the original code. During expansion, the discarded least significant bits are approximated by the median of the interval, to reduce the loss in accuracy. That is, if six of the least significant bits of the original binary integer were discarded during compression, these six least significant bits will be approximated by 1000002 during expansion. The -law binary decoding table used for expansion is given in Table 2. Again, the polarity bit is not shown in this table. After decoding the -law code, the bias is removed and the sign of the binary integer is restored according to the polarity bit.

Table3.2 -law Binary Decoding Table

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3.2 A-Law Companding A-law is the CCITT recommended companding standard used across Europe. A-law companding has the same basic features and implementation advantages as -law companding. A-law companding is approximated by linear segments, with the first chord defined to be exactly linear. A zero-level output for the first quantization interval is not defined. Although biasing of the integer is not required before conversion, the maximum integer value is reduced to 4096. Due to the larger minimum step size of 2/4096, which yields higher quantization error, A-law companding produces small amplitude signals of lower quality than m-law companding. However, the dynamic range of A-law companding is slightly higher than -law, as shown by following equation,

Where 15 is the lowest amplitude spanning the first chord.

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Figure 3.2. -law Companding Curve The two companding standards may also be compared with respect to precision of their binary integer representations. As stated previously, retained during companding are up to 5 bits of precision: the 4-bit step, and the leading 1 (with the exception of values within chord 0). Thus, for m-law companding, up to 8 bits of precision are lost, while a maximum of 7 bits of precision are lost for A-law companding. Upon initial consideration, two procedures may be necessary for A-law chord determination, due to the linear definition of the first chord. For binary integers of magnitude greater than 1F16, the procedure employed in chord and step determination for m -law compression may be implemented. For binary integers of magnitude less than or equal to 1F16, the chord is equal to 000 and the step is equal to the resulting 4 least significant bits after dividing the integer magnitude by 2.
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3.2.1 A-Law Compression Limiting sample values to 12 magnitude bits, the compression portion of this standard is defined in the following continuous equation.

Where A is the compression parameter (A=87.6 in Europe), and x is the normalized integer to be compressed. A piece-wise linear approximation to this compression equation is illustrated in Figure 3.2. Illustrated in Table 3.3 is the translation from linear to A-law compressed data. Of the compressed codeword, bits 4-6 represent the chord and bits 0-3 represent the step. Only the magnitudes of the input values and compressed codewords are shown; the sign extensions of the input value and the polarity bit of the compressed codeword have been omitted. Once the chord and step have been determined, the polarity of the original integer is determined. That is, if the original integer value is negative, the polarity bit 7 is set to 1; otherwise, the polarity bit 7 is cleared to 0.
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Table3.3 -law Binary Encoding Table Again, to improve hardware performance, an inversion pattern is applied to the codeword before transmission. For A-law companding, the pattern is every other bit starting with bit 0, where bit 0 is the rightmost bit as illustrated in Table 3.4. 3.2.2 A-law expansion A-law expansion is defined by the continuous inverse equation

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Before expansion, the inversion pattern is reapplied to the A-law code to restore the original code. As in -law expansion, the least significant bits discarded during compression are approximated by the median of the interval, to reduce loss in accuracy. The A-law binary decoding table used for expansion is given in Table 3.4. The polarity bit is not shown in this table. After decoding the A-law code, the sign of the integer is restored according to the polarity bit.

Table3.4 -law Binary Decoding Table

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Figure-3.3. Graph of -law & A-law algorithms: 4. METHODOLOGY The experimental setup for our project is illustrated through the block diagram shown in figure 4.1.

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Fig 4.1 Experimental setup 4.1 Algorithm The flow process for the above block diagram shown in fig 4.1 is explained as below. At first the speech signal is converted into analog electrical signal using microphone. Then that analog electrical signal is fed into microphone in port of the personal computer. In the computer the analog electrical signal is converted into digital format using pulse code modulation. Then the digital signal is converted into a wave format using the recording software. The next step is to convert the wave file into a
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text file. This is done using matlab processing and after a text file is generated it is saved in a separate folder which can be accessed by the ARM processor kit. Using the serial communication and UART the text file is transferred from the computer to the ARM kit. Here the text file is converted into a compressed file and this file is saved in the computer i.e. the original 13 bit STREAM OF BITS ARE converted into a 8 bit STREAM DATA. Again the saved file is accessed using the ARM for decompression purpose. After decompression the file generated from the ARM will be a 13 bit signal and using serial communication this file is transferred to the computer and saved as a folder. This saved file will be in a text format and again this has to be converted into a wave format. So the text file is converted into a wave file using matlab processing and the output from the matlab processing will be the required wave signal. Then the companded audio signal can be played using any playback software. 5. ARM processor In our project companding of voice signal is done using ARM processor. ARM is the todays most widely used processor in battery hold devices such as mobile phones and ipod because of its low power consumption. On 26 April 1985, the first ARM prototypes arrived at Acorn Computers Limited in Cambridge, England, having been fabricated by VLSI Technology, Inc., in San Jose,California. For the remainder of the
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1980s the ARM was quietly developed to underpin Acorn's desktop products which form the basis of educational computing in the UK; over the 1990s, in the care of ARM Limited, the ARM has sprung onto the world stage and has established a market-leading position in highperformance low-power and low-cost embedded applications. 5.1 Introduction ARM stands for Advanced Risc Machine. The ARM processor is a Reduced Instuction Set Computer(RISC). It was the first RISC microprocessor developed for commercial use and has some significant differences from other RISC architectures. The ARM architecture has a number of features such as a loadstore architecture; fixed-length 32-bit instructions; 3-address instruction formats 5.2 Architectural inheritance At the time the first ARM chip was designed, the only examples of RISC architectures were the Berkeley RISC I and II and the Stanford MIPS (which stands for Microprocessor without Interlocking Pipeline Stages), although some earlier machines such as the Digital PDP-8, the Cray-1 and the IBM 801, which predated the RISC concept, shared many of the characteristics which later came to be associated with RISCs.

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5.2.1Features used The ARM architecture incorporated a number of features from the Berkeley RISC design, but a number of other features were rejected. Those that were used were A load-store architecture Fixed-length 32-bit instructions 3-address instruction formats 5.2.2 Features rejected The features that were employed on the Berkeley RISC designs which were rejected by the ARM designers were Register windows Delayed branches

5.3 ARM Architecture ARM employs load-store architecture. This means that the instruction set will only process values which are in registers and will always place the results of such processing into a register.

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Apart from the loadstore architecture ARM has certain other features. They are described as follows: 32-bit RISC-processor core (32-bit instructions) 37 pieces of 32-bit integer registers (16 available) Cached (depending on the implementation) Von Neuman-type bus structure (ARM7), Harvard (ARM9) 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)

ARM does not support memory-to-memory' operations. All ARM instructions fall into one of the following three categories: 1. Data processing instructions. These use and change only register values. For example, an instruction can add two registers and place the result in a register. 2. Data transfer instructions. These copy memory values into registers (load Instructions) or copy register values into memory (store instructions). An additional form, useful only in systems code, exchanges a memory value with a register value.

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3. Control flow instructions. Normal instruction execution uses instructions stored at consecutive memory addresses. Control flow instructions cause execution to switch to a different address, either permanently (branch instructions) or saving a return address to resume the original sequence (branch and link instructions)or trapping into system code (supervisor calls).

5.4 ARM Instruction Set All ARM instructions are 32 bits wide (except the compressed 16bit Thumb instructions) and are aligned on 4-byte boundaries in memory. The most notable features of the ARM instruction set are:

3-address data processing instructions (that is, the two source operand registers and the result register are all independently specified);

conditional execution of every instruction; the inclusion of very powerful load and store multiple register instructions;

the ability to perform a general shift operation and a general ALU operation in a single instruction that executes in a single clock cycle;

open instruction set extension through the coprocessor instruction set, including adding new registers and data types to the programmer's model;

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a very dense 16-bit compressed representation of the instruction set in the Thumb architecture.

ARM instructions are all 32-bit words and must be word-aligned. Internally all ARM operations are on 32-bit operands; the shorter data types areonly supported by data transfer instructions. When a byte is loaded from memoryit is zero- or sign-extended to 32 bits and then treated as a 32-bit value for internal processing. ARM coprocessors may support other data types, and in particular there is a defined set of types to represent floating-point values.

ARM processors support six data types: 8-bit signed and unsigned bytes. 16-bit signed and unsigned half-words; these are aligned on 2-byte boundaries.

32-bit signed and unsigned words; these are aligned on 4byte boundaries.

5.5 The ARM programmer's model A processor's instruction set defines the operations that the programmer can use to change the state of the system incorporating the processor. This state usually comprises the values of the data items in the processor's visible registers and the system's memory. Each instruction can be viewed as performing a defined transformation from the state
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before the instruction is executed to the state after it has completed. Note that although a processor will typically have many invisible registers involved in executing an instruction, the values of these registers before and after the instruction is executed are not significant; only the values in the visible registers have any significance. The visible registers in an ARM processor are shown in Figure 5.1 When writing user-level programs, only the 15 general-purpose 32-bit registers (r0 to r14), the program counter (r15) and the current program status register (CPSR) need be considered. The remaining registers are used only for system-level programming and for handling exceptions (for example, interrupt).

Figure 5.1 ARM's visible registers.

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5.5.1 The Current Program Status Register (CPSR) The CPSR is used in user-level programs to store the condition code bits. These bits are used, for example, to record the result of a comparison operation and to control whether or not a conditional branch is taken. The user-level programmer need not usually be concerned with how this register is configured, but for completeness the register is illustrated in Figure 5.2. The bits at the bottom of the register control the processor instruction set and interrupt enables and are protected from change by the user-level program. The condition code flags are in the top four bits of the register and have the following meanings. N: Negative; the last ALU operation which changed the flags produced a negative of the 32-bit result was a one). Z: Zero; the last ALU operation which changed the flags produced a zero result (every bit of the 32-bit result was zero). C: Carry; the last ALU operation which changed the flags generated a carry-out, either as a result of an arithmetic operation in the ALU or from the shifter. V: overflow; the last arithmetic ALU operation which changed the flags generated an overflow into the sign bit. result (the top bit

Figure 5.2 ARM CPSR format.

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Note that although the above definitions for C and V look quite complex, their use do not require a detailed understanding of their operation. In most cases there is a simple condition test which gives the desired result without the programmer having to work out the precise values of the condition code bits. 5.6 ARM Thumb The Thumb instruction set addresses the issue of code density. It may be viewed as a compressed form of a subset of the ARM instruction set. Thumb instructions map onto ARM instructions, and the Thumb programmer's model maps onto the ARM programmer's model. Implementations of Thumb use dynamic decompression in an ARM instruction pipeline and then instructions execute as standard ARM instructions within the processor. Thumb is not a complete architecture; it is not anticipated that a processor would execute Thumb instructions without also supporting the ARM instruction set. Thumb is fully supported by ARM development tools, and an application can mix ARM and Thumb subroutines flexibly to optimize performance or code density on a routine-by-routine basis. T (Thumb)-extension shrinks the ARM instruction set to 16-bit word length -> 35-40% saving in amount of memory compared to 32-bit instruction set Extension enables simpler and significantly cheaper realization of processor system.
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Instructions take only

half of memory than with 32-bit instruction set without significant decrease in performance or increase in code size. Extension is made to instruction decoder at the processor pipeline 5.6.1 Thumb instruction set The thumb instruction set of ARM is shown in the figure 5.3

Figure 5.3 Thumb instruction set

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The main features of Thumb instruction set are Instruction word length shrunk to 16-bits Instructions follow their own syntax but each instruction has its native ARM instruction counterpart Due to shrinking some functionality is lost 19 different Thumb instruction formats 5.7 ARM7TDMI The ARM7TDMI is the current low-end ARM core and is widely used across a range of applications, most notably in many digital mobile telephones. And in our project we use the ARM7TDMI processor. It evolved from the first ARM core to implement the 32-bit address space programming model, the ARM6, which it now supersedes. The ARM6 used circuit techniques that prevented it from operating reliably with a power supply of less than 5 volts. The ARM? corrected this deficiency, and then 64-bit multiply instructions, on-chip debug support, the Thumb instruction set and the EmbeddedlCE watchpoint hardware were all added over a fairly short period of time to give the ARM7TDMI. The origins of the name are as follows: The ARM7, a 3 volt compatible rework of the ARM6 32bit integer core, with: the Thumb 16-bit compressed instruction set; on-chip Debug support, enabling the processor to halt in response to a debug request;
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 an enhanced Multiplier, with higher performance than its predecessors and yielding a full 64-bit result; and EmbeddedlCE hardware to give on-chip breakpoint and watchpoint support. 5.7.1 ARM7TDMI organization The organization of the ARM7TDMI is illustrated in Figure 9.1 on page 249. The ARM7TDMI core is a basic ARM integer core using a 3stage pipeline (see Section 4.1 on page 75) with a number of important features and extensions: It implements ARM architecture version 4T, with support for 64-bit result multiplies, half-word and signed byte loads and stores and the Thumb instruction set. It includes the EmbeddedlCE module to support embedded system debugging. As the debug hardware is accessed via the JTAG test access port, the JTAG control logic is considered part of the processor macrocell. The block diagram of ARM7 TDMI organization is shown in figure 5.4

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Figure 5.4 ARM7TDMI organization. 5.8 Applications Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs, making it one of the most widely used 32bit architectures. ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, media players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers); however it no longer has significant penetration as the main processor in the desktop computer market and has never been used in a supercomputer or cluster. Important branches in this family include Marvell's XScale and the Texas Instruments OMAP series. 6. POWER CONSUMPTION
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ARM processor is known for its less power consumption. Due to its less power consumption it is used in most of the battery hold devices such as mobile phones, ipods etc. Due to this feature we choose ARM processor in our project. Since the introduction of digital computers 50 years ago there has been sustained improvement in their cost-effectiveness at a rate unparalleled in any other technical endeavor. As a side-effect of the route taken to increased performance, the power consumption of the machines has reduced equally dramatically. Only very recently, however, has the drive for minimum power consumption become as important as, and in some application areas more important than, the drive for increased performance. This change has come about as a result of the growing market for battery-powered portable equipment, such as digital mobile telephones and lap-top computers, which incorporate high-performance computing components. Following the introduction of the integrated circuit the computer business has been driven by the win-win scenario whereby smaller transistors yield lower cost, higher performance and lower power consumption. Now, though, designers are beginning to design specifically for low power, even, in some cases, sacrificing performance to achieve it. The ARM processor is at the centre of this drive for powerefficient processing. It therefore seems appropriate to consider the issues around design for low power.
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6.1 CMOS power components The total power consumption of a CMOS circuit comprises three components: Switching power Short-circuit power Leakage current. 6.1.1Switching power This is the power dissipated by charging and discharging the gate output capacitance CL, and represents the useful work performed by the gate. The energy per output transition is CMOS circuit power. 6.1.2 Short-circuit power When the gate inputs are at an intermediate level both the p- and ntype networks can conduct. This results in a transitory conducting path from Vdd to Vss. With a correctly designed circuit (which generally means one that avoids slow signal transitions) the short-circuit power should be a small fraction of the switching power. 6.1.3 Leakage current

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The transistor networks do conduct a very small current when they are in their 'off' state; though on a conventional process this current is very small (a small fraction of a nanoamp per gate), it is the only dissipation in a circuit that is powered but inactive, and can drain a supply battery over a long period of time. It is generally negligible in an active circuit. 6.2 Low-power circuit design The total power dissipation, Pc, of a CMOS circuit, neglecting the short-circuit and leakage components, is therefore given by summing the dissipation of every gate g in the circuit.

Where f is the clock frequency, Ag is the gate activity factor (reflecting the fact that not all gates switch every clock cycle) and C/ is the gate load capacitance. Note that within this summation clock lines, which make two transitions per clock cycle, have an activity factor of 2. The remaining parameters in Equation 3 suggest various approaches to low-power design. These are listed below with the most important first:

1. Minimize the power supply voltage, Vdd.

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The quadratic contribution of the supply voltage to the power dissipation makes this an obvious target. This is discussed further below. 2. Minimize the circuit activity, A. Techniques such as clock gating fall under this heading. Whenever a circuit function is not needed, activity should be eliminated. 3. Minimize the number of gates. Simple circuits use less power than complex ones, all other things being equal, since the sum is over a smaller number of gate contributions. 4. Minimize the clock frequency, f. Avoiding unnecessarily high clock rates is clearly desirable, but although a lower clock rate reduces the power consumption it also reduces performance, having a neutral effect on power-efficiency (measured, for example, in MIPS - Millions of Instructions per Second per watt). If, however, a reduced clock frequency allows operation at a reduced Vdd, this will be highly beneficial to the power-efficiency.

7. PHILIPS LPC 2129

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7.1 General descriptions

The LPC2129 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty. With their comapct 64 and 144 pin packages, low power consumption, various 32-bit timers, combination of 4-channel 10-bit ADC and 2/4 advanced CAN channels or 8-channel 10-bit ADC and 2/4 advanced CAN channels (64 and 144 pin packages respectively), and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and point-of-sale. Number of available GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of available GPIOs tops 76 (with external memory in use) through 112 (single-chip application). Being equipped wide range of serial communications interfaces, they are also very well suited for communication gateways , protocol converters and embedded soft modems as well as many other general-purpose applications.

7.2 Features
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 16/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package. 16 kB on-chip Static RAM

128/256 kB on-chip Flash Program Memory (at least 10,000 erate/write cycles over the whole temperature range). 128-bit wide interface/accelerator enables high speed 60 MHz operation.

External 8, 16 or 32-bit bus (144 pin package only)

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms.

EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software.

Embedded Trace Macrocell enables non-intrusive high speed realtime tracing of instruction execution. Two/four interconnected CAN interfaces with advanced acceptance filters. Four/eight channel (64/144 pin package) 10-bit A/D converter with conversion time as low as 2.44 ms. Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog. Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s) and two SPIs.
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 60 MHz maximum CPU clock available from programmable onchip Phase-Locked Loop. Vectored Interrupt Controller with configurable priorities and vector addresses.

Up to forty-six (64 pin) and hundred-twelve (144 pin package) 5 V tolerant general purpose I/O pins. Up to 12 independent external interrupt pins available (EIN and CAP functions).

On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz. Two low power modes, Idle and Power-down. Processor wake-up from Power-down mode via external interrupt. Individual enable/disable of peripheral functions for power optimization. Dual power supply. * CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%). * I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%). 7.3 ON-CHIP Flash memory system LPC2129 incorporate a 256 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP)
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functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.

7.4 ON-CHIP Static RAM The LPC2119/2129/2194/2292/2294 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses. The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.

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7.5 Block Diagram of LPC2129 The block diagram of LPC2129 is shown in figure 7.1

Figure 7.1 Block Diagram of LPC2129 8. RESULTS AND DISCUSSIONS The memory size of the sectors needs an additional care in

allocating the bit size values. The internal PLL of the arm controller supports up to 40 MHZ. When enabled the simultaneous operation of the memory allocation and the serial interference are to be in the same
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frequency and timing operation, which leads to an creation of the additional sectoring which multiples the sizes of the Memory in even values , if there is an additional engine which manages the serial data transmissions and receptions . Managing the data which at the rate which we require, so that the internal PLL will not be enabled, that memory allocation will not be an problem in data sector registries. An additional serial engine is added externally which is directly interconnected to the parallel ports of the ARM, a handshaking as general purpose I/O. The data is been transferred as the parallel Form which is stored in the memory sectors, which reduces the looping of ARM in serial interrupt managing and doubling the frequency of the PLL. 9. CONCLUSION As we know that ARM processor can be operated in a low power environment it can be used in devices in which power consumption is an important criterion. Usually ARM can be operated in the range of 2.3V to 3.7V. ARM 7 TDMA operates in 3.23V. So the life time of the battery of the device which uses ARM processor can be increased. As the speed of transmission of data in serial communication from the computer to the arm processor does not match each other, we have to reduce the sector size from 8k to 4k. Different standards of companding can be achieved by changing the sector identification. Thumb architecture operation of the ARM makes very fast execution in time critical application such as telephone networks. The result of our project is verified for the various voice signals and expected results are achieved.
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10. REFERENCES 1. Addison Wesley - ARM SoC Architecture, 2nd Edition 2. Philips LPC2129 preliminary user manual
3. "ITU-T Recommendation G.711". 4. 5.

Dept. of Phys. Electron., Tokyo Inst. of Technol www.keil.com

6. "Wikipedia on sound". 7. "Cisco - Waveform Coding Techniques"

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