Hi Friends, Pls. make a note that HOLD violations are dangerous than SETUP.

To keep it simpl e way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here. T = Frequency of operation (can be variable) Tcq = Flop clock to Flop output delay (fixed/constant) Tcomb = Delay od the combinational logic between the Flops (can be variable) Tsetup = Setup time of a Flop (fixed/constant) Thold = Hold time of a Flop (fixed/constant) Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable) For SETUP, T >= Tcq + Tcomb + Tsetup - Tskew If you have setup time means u r violating the above rule. i.e some how the equa tion becomes T < Tcq + Tcomb + Tsetup - Tskew Now let us consider two cases. Case1: During the Design development phase itself. Now, you have three variables (T, Tcomb, Tskew.) to avoid the setup violation. T : Reduce the frequency such that u saticify T >= Tcq + Tcomb + Tsetup - Tskew. But do u think it is the correct solution. Obviously, NO. This is because we ha ve other options to avoid setup violations right. Tcomb : If you reduce the combinational delay (between the Flops of violated pat h) such a way that T < Tcq + Tcomb + Tsetup - Tskew will become T >= Tcq + Tcomb + Tsetup - Tskew. So, the SETUP violation is avoided. How do u reduce the combi national delay??? Try different logic structure without effecting the functional ity. or try to reduce the more fanout nets within the logic. Or upsize or downsi ze the cells. If it worked out thats fine. Tskew: If u increase the skew, u can change T < Tcq + Tcomb + Tsetup - Tskew to T >= Tcq + Tcomb + Tsetup - Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing. Case2: After the CHIP is manufatured and is in your hand. In this case, one cannot access the Tcomb and Tskew. Only the variable that can handle is T. So, Just reduce the frequency (T) such that the violated equation, T < Tcq + Tco mb + Tsetup - Tskew becomes violation free equation T >= Tcq + Tcomb + Tsetup Tskew. So, if u have setup violations on a manufatured chip, u can make it work by redu cing the frequency. For HOLD, Thold + Tskew <= Tcq + Tcomb If you have setup time means u r violating the above rule. i.e some how the equa tion becomes Thold + Tskew > Tcq + Tcomb and ur aim is to make Thold + Tskew <= Tcq + Tcomb Now let us consider two cases. Case1: During the Design development phase itself.

You have two variables in hand (Tcomb, Tskew) to avoid HOLD violations. Tcomb: Increase the Tcomb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew > Tcq + Tcomb to Thold + Tskew <= Tcq + Tcomb. But this might effect the SETUP time as you are increasing the delay of combinat ional path. So this may not be the perfect solution always. Tskew : Reduce the clock skew so that you will land on Thold + Tskew <= Tcq + Tc omb. To reduce the clock skew, the best solution is to take the help of your PNR engineer. Case2: After the CHIP is manufatured and is in your hand. Do you see any variables that will fix the hold violations after manufaturing??? ??!!!!!! NO right. So, its time to DUMP the chip as we dont deliver malfunctioni ng chips to the customers. So becareful with the HOLD violations. Note: One can get those equations if u put the those scenarios on a paper and de velop the timing diagrams. Hope I've explained it properly. Regards, Sunil Budumuru. Added after 46 minutes: Hi koggestone, It is nice information. Could you please give us more information on " u will need a new metal fix tapeout . ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease ho ld time violation)" It may give us more information on this topic. Thanks in advance. Regards, Sunil Budumuru.