PRESENTED BY NISHIYA VIJAYAN S1MTech R#12 SNGCE

ABSTRACT
In this paper, a set of CMOS differential logic circuits

are introduced for use in low-power application. Perform a conditional operation for statistical power reduction during logic operation. The self-precharged version provides additional power saving by allowing the use of a small-swing clock. Bidirectional shift registers were to assess the performance of the proposed technique. shift registers with the proposed technique achieve 44%63% power reduction at a typical switching activity of 0.25.

CONTENTS
INTRODUCTION CONVENTIONAL DCVS

- OPERATION
PROPOSED LOGIC FAMILY-CELL -PRECHARGED DIFFERENTIAL STAGE

-SYMMETRIC LATCHING
SP-CELL CONCLUSION REFERENCES

INTRODUCTION
WHY WE REQUIRE LOW POWER DESIGN? Increasing demand for power-efficient computation of laptops and mobile communication systems . Cost of cooling method. Low power SoC

CONVENTIONAL DCVS

OPERATION
Overcome the speed degradation of

static CMOS logic by eliminating bulky PMOS n replacing them with a single precharge transistor with an appropriate clock signal. This dynamic gate is precharged high at a specific phase of the clock and may evaluate low through an nMOS stack at the other clock phase. DCVS presents a much lower input capacitance for the same output current and provides a lower switching

Cont
Improves performance when there are

interdependencies among the minterms of a logical expression. Natural choice for the implementation of timing-critical logic functions in SoCs. DCVS charges and discharges one of the dual precharge nodes repeatedly even when the gate is evaluating the same logic value switching power consumption becomes a dominant portion in overall power

Cont
In

the static CMOS logic, the gate transitions only when it needs to change its output value, minimizing the power when data switching activity is low. DCVS cannot be used with a global clock having its voltage swing less than the supply voltage This paper describes a circuit technique to avoid the drawbacks of the conventional circuit

PRECHARGED DIFFERENTIAL STAGE

SYMMETRIC LATCHING

Cont
by

Conditional-evaluating latched CMOS differential logic-CELL Consists of a precharged differential stage and a symmetric latching stage. M1 and M2 driven by CK in differential stage precharge SB and CB Transistors M3 and M4 driven by FDB and FD-delayed versions of F and FB using a pair of optional delay elements-connect logic tree to SB/RB

Cont
The differential logic tree implements logic function, and is activated by bottom transistor M9. Transistors M5 to M8 are weak devices to increase the noise immunity of precharge nodes. M5 and M6 are used to make a floating high value on SB or RB fully static. M7 and M8 do the same function for a floating low value on SB or RB.

Cont
They do not fight against pull-up precharge operation since their source terminal is connected to M9, becomes fully off during the precharge period. The symmetric latching stage captures the evaluated data in the first stage and holds the outputs until the next evaluation occurs. Transistors M10 to M13 receive new data the cross-coupled circuit consisting of M14 M17 holds the output statically. When CK is low, SB and RB are precharged to the supply voltage with the differential logic tree deactivated.

Cont
They do not fight against pull-up precharge operation since their source terminal is connected to M9, which becomes fully off during the precharge period. The symmetric latching stage captures the evaluated data in the first stage and holds the outputs until the next evaluation occurs. Transistors M10 to M13 receive new data the cross-coupled circuit consisting of M14M17 holds the output statically. When CK is low, SB and RB are precharged to the supply voltage with the differential

Cont
Cell can be operated in pipelined fashion 2 pipeline stage The falling transition time<The propagation

delay from SB/RB to FD/FDB

SELF-PRECHARGED CELL

SYMMETRIC LATCHING STAGE.

Cont
Ml and M2 as well as M3 and M4 are

driven by FDB and FD instead of the external clock. External clock CK driving only M9 has a voltage swing smaller than the supply voltage. Transistors Ml8 and Ml9 driven by INTB are added for the initialization of precharge nodes. SP-CELL has the disable phase and the evaluate/reset phase.(CK is low )

Cont
When outputs are changed by a pull-down of

SB or RB during the evaluate/reset phase, the operating regions of M1 and M2 as well as M3 and M4 are changed. ,SP-CELL is driven by a small swing clock instead of a full-swing clock which external clock CK is low to prevent a direct current flow from VDD to VSS. SP-CELL can be operated as a pipelined configuration as CELL does. I no intermediate latching stages -latched internally

COMPARISON
The precharge nodes are discharged

only when the output states are required to be changed Conditional evaluation leads to a substantial reduction of the switching component of the power consumption when the incoming data has a low switching activity. Further power saving due to the use of global clock with a small voltage swing.

Cont
there occurs a short-circuit current

through precharge pMOS transistors during the evaluation period. Clock load reduction of SP-CELL also helps minimize the power consumption To assess the performance of the proposed logic family, 16-bit bidirectional shift registers were designed with DCVS, CELL, and SPCELL. The delay element for obtaining FD or

MULTIPLEXER SPCELL

Cont
The clock swing for this circuit was

chosen to be half of the supply voltage (0 n 0.9 V) That the shift register with CELL achieves up to 57% power reduction as compared with that of DCVS. SP-CELL achieves up to 75% power reduction power consumption for all of the switching activity values compared mainly due to clock power reduction. The power consumption is measured


MEASURED PERFORMANCE OF 16-b BIDIRECTIONAL SHIFT REGISTERS

CONCLUSION
In this paper, a set of latched CMOS differential logic

family with conditional evaluation has been proposed. The precharged nodes in the circuit are discharged conditionally to eliminate unnecessary transitions during evaluation operations, leading to statistical power reduction. The proposed logic family also provides reduced clock power due to the use of a clock with small swing. The operation of the proposed logic family was verified by t shift registers indicates that it is suitable for use in low-power SoC design.

REFERENCES
IEEE transactions on circuits and systemsvol.

55, no. 5, may 2008 Minimizing power consumption in digital CMOS circuits, IEEE, vol. 83 www.google.com www.ieeexplore.com CMOS digital integrated circuits-Sung Mo Kang,Yusuf Leblebici