Multivibrator Circuits

Bistable Multivibrator (Flip-Flops) Astable Multivibrator (Clocks or Oscillators) Schmitt-Trigger Inverter (7414) 555 Timer Crystal Oscillator Monostable Multivibrator (One-Shots) Non-Retriggerable (74121) Retriggerable (74123) VHDL Coding
ECE 3450 M. A. Jupina, VU, 2010

Some Key Lecture Objectives

To learn how timing signals are generated at low frequencies (< 1 MHz) and high frequencies (>1 MHz). To learn how clock and pulse signals are generated either through the use of ICs or VHDL coding. To gain a better understanding of how to apply timing signals in a digital design.

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Schmitt-Trigger Inverter

(a) If input transition times are too long, a standard logic device-output might oscillate or change erratically; (b) a logic device with a Schmitttrigger type of input will produce clean, fast output transitions.
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Schmitt-Trigger Inverter Operation

VOUT VOH

VOL VTL VTH

VIN

As VIN increases, VOUT = VOH until VIN > VTH then VOUT = VOL When VIN begins to decrease, VOUT = VOL until VIN < VTL then VOUT = VOH
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Schmitt-Trigger Oscillator

IIN

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Analysis of a Schmitt-Trigger Oscillator

VC(t) VTH VTL t VOH VOUT(t) VOL

TL

TH
t

t=0 t = 0' Assume Iin = 0, thus IR(t) = IC(t) Capacitor Charging Capacitor Discharging
VOL
VC(t)

VOH

VC(t)

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Analysis of a Schmitt-Trigger Oscillator Continued

Capacitor Discharging
Capacitor Charging

I.C. VC (0) VTH VC (TL ) VTL VOL VC (t ) dVC (t ) C R dt t RC VC (t ) VOL (VOL VTH )e VTL VOL (VOL VTH )e
OL TL RC ln( VTH VOL ) TL

I.C. VC (0) VTL VC (TH ) VTH VOH VC (t ) dVC (t ) C R dt t RC VC (t ) VOH (VOH VTL )e VTH VOH (VOH VTL )e TH RC ln(
1 T 1 TL TH

TL RC

TH RC

VOH VTL VOH VTH

TH T

fOSC
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, Duty Cycle

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Example: Show how to use a 74LS14 Schmitt-trigger inverter to produce an approximate square wave with a frequency of 10 KHz.

Solution:

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PSPICE Simulation of a Schmitt-Trigger Oscillator (7414)

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555 Timer as an Astable Multivibrator

1 Ground 2 Trigger 3 Output 4 Reset (Set HIGH for normal operation)

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5 FM Input (Tie to gnd via bypass cap) 6 Threshold 7 Discharge 8 Voltage Supply (+5 to +15 V)
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Block Diagram of a 555 Timer Configured as an Oscillator

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555 Timer Block Diagram Contents

Resistive voltage divider (equal resistors) sets threshold voltages for comparators

V1 = VTH = 2/3 VCC

Two Voltage Comparators - For A1, if V+ > VTH - For A2, if V- < VTL RS FF

V2 = VTL = 1/3 VCC

then R =HIGH then S = HIGH

- If S = HIGH, then FF is SET, Q = LOW, Q1 OFF, VOUT = HIGH - If R = HIGH, then FF is RESET, Q = HIGH, Q1 ON, VOUT = LOW

Transistor Q1 is used as a Switch

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Timing Diagram of a 555 Oscillator

VC(t) VTH VTL

t
VCC VOUT(t)

TL

TH
t
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t = 0 t = 0'
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Operation of a 555 Oscillator

1) Assume initially that the capacitor is discharged. a) For A1, V+ = VC = 0V and for A2, V- = VC = 0V, so R=LOW, S=HIGH, Q = LOW , Q1 OFF, VOUT = VCC b) Now as the capacitor charges through RA & RB, eventually VC > VTL so R=LOW & S=LOW. FF does not change state.

RA
VCC

RB
VC(t)

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Operation of a 555 Oscillator Continued

2) Once VC VTH a) R=HIGH, S=LOW, Q = HIGH ,Q1 ON, VOUT = 0 b) Capacitor is now discharging through RB and Q1 to ground. c) Meanwhile at FF, R=LOW & S=LOW since VC < VTH. RB
VC(t)

Q1

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Operation of a 555 Oscillator Continued

3) Once VC < VTL a) R=LOW, S=HIGH, Q = LOW , Q1 OFF, VOUT = VCC b) Capacitor is now charging through RA & RB again.

RA
VCC

RB
VC(t)

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Analysis of a 555 Oscillator

Capacitor Discharging Capacitor Charging

I.C. VC (0) VTH 2 VCC 3 VC (TL ) VTL 1 VCC 3 VC (t ) dVC (t ) C RB dt VC (t ) VTH e

1 3
t RBC

I.C. VC (0) VTL VC (TH ) VTH VCC VC (t ) dVC (t ) C RA RB dt VC (t ) VCC (VCC VTL )e

t ( R A RB ) C

2 VCC 3 VCC e

TL R

BC

2 3

VCC VCC (VCC 1 VCC )e 3

TH ( RA RB ) C

TL RB C ln(2) 0.69 RB C

TH 0.69( RA RB )C
TH T

fOSC
1 T
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1 0.69C ( RA 2 RB )

, Duty Cycle

RA RB RA 2 RB

0.5 or 50%
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Example: Design a 555 Oscillator to produce an approximate square-wave at 40 KHz. Let C > 470 pF.

Examples

One Possible F=40KHz; T=25s; t1=t2=12.5s Solution: For a square-wave RA<<RB; Let RA=1K and RB=10K

t1=0.693(RB)(C); 12.5s=0.693(10K)(C); C=1800pF T=0.693(RA+2RB)C: T=0.693(1K+20K)1800pF T=26.2s; F=1/T; F=38KHz (almost square-wave). Example: A 555 oscillator can be combined with a J-K FF to produce a 50% duty-cycle signal. Modify the above circuit to achieve a 50% duty-cycle, 40 KHz signal.
One Possible Reduce by half the 1800pF. This will create a T=13.1s or F=76.35 KHz Solution: (almost square-wave). Now, take the output of the 555 Timer and connect
it to the CLK input of a J-K FF wired in the toggle mode (J and K inputs connected to +5V). The result at the Q output of the J-K FF is a perfect 38.17 KHz square-wave.
ECE 3450 M. A. Jupina, VU, 2010

Problem 10.24 - The 555 Programmable Timer Chip

5V

4 Clock (output) 3

8 Ra 555 Timer 7 Rb

2
1

6
C1 5

0.01m F

(a) For 50% duty cycle and 500 KHz frequency, C1 = 100 pF, then Ra = 1 k and Rb = 14 k (b) For 75% duty cycle and 500 KHz frequency, C1 = 1000 pF, then Ra = 1.42 k and Rb = 0.71 k
ECE 3450 M. A. Jupina, VU, 2010

PSPICE Simulation of a 555 Oscillator

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R1=R2, duty cycle = 66% and f =16 KHz

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Crystal Oscillator
An oscillator circuit that uses a piezoelectric crystal. Piezoelectric materials support an exchange of energy between mechanical compression and applied electric field. If a potential is applied between the electrodes, forces will be exerted on the bound charges within the crystal. Deformations take place within the crystal and an electromechanical system is formed which will vibrate when properly excited.

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Crystal Oscillator, Continued

The oscillation frequency (10 KHz 80 MHz) is very precisely determined by the physical dimensions of the crystal. High Q (1000 10,000) resonators are usually built using quartz single crystal or ceramic materials. These resonators are extremely stable (ppms) with respect to time and temperature. To generate clock frequencies into the GHz range, DPLL (Digital Phase Lock Loops) are used for frequency multiplication.
XTAL OSC

fo

DPLL

Nfo
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ECE 3450

Crystal Oscillator Circuit Example

crystal oscillator symbol and equivalent circuit

Pierce oscillator circuit

Steady-state oscillation occurs at the frequency where

Yi YN 0
equivalent circuit of Pierce oscillator
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Example: 50 MHz Oscillator on the Altera DE2 Board

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Clock Divider

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Non-Retriggerable One-Shot (OS)

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Comparison of Non-Retriggerable and Retriggerable OS responses for tPULSE = 2 ms

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Example: Refer to the waveforms in (a) on previous page. Change the OS pulse duration to 0.5 ms and determine the Q output for both types of OS. Then repeat using a pulse duration of 1.5 ms.

Example

Solution:

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74121 Non-Retriggerable OS

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Example: (a) Show how a 74121 can be connected to produce a negative-going pulse with a 5 ms duration whenever A1 or A2 is connected to a negative-going trigger. (b) Modify the circuit so that when a signal G goes low it can be used to disable the 74121.

Example

Solution:

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74123 Dual One Shot PSPICE Simulation

tw = 0.33 RT Cext

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VHDL Nonretriggerable One-Shot

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Simulation of the Nonretriggerable One-Shots

Comparison of this VHDL OS to an IC OS

VHDL OS output does not change state until a rising edge clock signal occurs whereas an IC OS output changes immediately when triggered. The trigger signal for the VHDL OS must be active during a rising clock edge so as to be recognized (the IC OS trigger is an asynchronous signal, i.e., it can occur whenever). The VHDL OS is level-triggered whereas the IC OS is edge-triggered.

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Detecting Edges

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VHDL Retriggerable One-Shot with Edge Trigger

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Simulation of the Edge-Triggered Retriggerable One-Shot

Comparison to Previous VHDL OS

Just as the case before, the output of this OS does not change state until a rising edge clock signal occurs. Unlike the previous OS, this OS is edge-triggered. Just as the case before, the trigger signal for this OS must be active during a rising clock edge so as to be recognized.

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Final Notes on VHDL OS

To minimize the effects of a delayed output pulse with respect to a rising edge trigger, the clock frequency and the initial value of the count can be increased so that an output pulse of the same width is produced. An asynchronously triggered OS can be created in VHDL but the output pulse generated will fluctuate in width by up to one clock period.

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Example of a Dual One Shot Circuit

trigger (10 KHz) clock (100 KHz)

Q1
Q2

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-- retriggerable edge-triggered one-shot -- time delay = delay * clock period LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY os1 IS PORT ( clock, trigger, reset delay q END os1; : IN BIT; : IN INTEGER RANGE 0 TO 15; : OUT BIT);

OS1 VHDL

ARCHITECTURE a OF os1 IS BEGIN PROCESS (clock, reset) VARIABLE count : INTEGER RANGE 0 TO 15; VARIABLE trig_was : BIT; BEGIN IF reset = '0' THEN count := 0; ELSIF (clock'EVENT AND clock = '0' ) THEN IF trigger = '0' AND trig_was = '1' THEN count := delay; trig_was := '0'; ELSIF count = 0 THEN count := 0; ELSE count := count - 1; END IF; IF trigger = '1' THEN trig_was := '1'; END IF; END IF; IF count /= 0 THEN q <= '1'; ELSE q <= '0'; END IF; END PROCESS; END a;

-- load counter -- "remember" edge detected -- hold @ 0 -- decrement

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