PIC1

PIC
INTRODUCTION
The high performance of PIC can be attributed to a number of architectural features found in RISC microprocessor.
Harvard architecture
Long word instruction Single word instruction
Single cycle instruction

Instruction pipelining Reduced instruction set
Register file architecture

Orthogonal instructions
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INTRODUCTION
Long word instruction-These instructions have a wider instruction bus than the 8 bit Data memory bus.This is possible because the two busses are separate .This allows instructions to be sized differently that 8 bit wide data word, which allows a more efficient use f the program memory, since program memory width is optimized to the architectural requirements. Single word instruction-Single word instructions are 14 bit wide.A 14bit wide program memory access bus fetches a 14 bit instruction in a single cycle.with single word instruction ,the no.of words of program memory location equals the number of instructions for the device,hence all locations are valid instructions.
INTRODUCTION
Instruction pipeline-The instruction pipeline is two stage pipeline,which overlaps the fetch and execution of instructions.The fetch takes one TCY and execution takes on TCY,but due to overlap the fetch of one instruction and execution of previous instruction is done in one TCY. Single cycle instruction-with the program memory bus being 14 bits wide the entire instruction is fetched in a single TCY.the instruction contains all the information required and is executed in a single cycle.There may be one cycle delay if the results of the instruction modifies the contents of the program counter.This requires the pipelined to be fetched and a new instruction to be fetched.
INTRODUCTION
Reduced instruction set-When the instruction set is well designed and highly symmetric fewer instructions are required to perform all needed tasks. Register file architecture-The register files/data memory can be directly or indirectly addressed.All special functions registers,including program counter are mapped in the data memory. Orthogonal(Symmetric)instructions-Orthogonal instructions make it possible to carry out any operation on any register using addressing mode.This makes programming simpler yet efficient.
INTRODUCTION
The mid range instruction set uses only two nonregister oriented instruction,which are used for two of the cores feature.one is SLEEP instruction ,which places the device into the lowest power use mode and the other is CLRWDT which verifies the chip is operating properly by preventing the on-chip WDT from overflowing and resetting the device.
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Accel Software &Technologies Limited
INTRODUCTION
PIC-Peripheral interface controller Why PIC? PIC is very popular micro controller worldwide. Microchip(2nd largest chip manufacture) is one of the manufactures of 8 bit RISC processor. Focus on high performance cost effective,field programmable embedded control solutions Variety of end user application specific standard product(ASSP)& application specific integrated circuit(ASIC) Global network of manufacturing and customer support facilities.
FEATURES
High performance RISC CPU Only 35 single word instructions. All single cycle instructions except for program branches which are two cycles. Operating speed DC- 20MHz clock input; DC-200ns instruction cycle. 2Kx14 words of flash program memory 128x8 bytes of data memory(RAM) 68x8 bytes of EEPROM Data memory No of pins ranges from 28 to 40 Interrupt capabilities (upto 11 sources).
FEATURE
Eight level deep hardware stack Direct ,indirect and relative addressing modes Power on reset(POR) Power up timer(PWRT) and oscillator start up timer(OST) WDT with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving sleep modes Selector oscillator options Low power high speed CMOS FLASH/EEPROM technologies
FEATURES
Fully static design In circuit serial programming(ICSP) through two pins. Single 5V ICSP capabilities In circuit debugging through two pins Processor read /write access to program memory. Wide operating range 2.0V to 5.5V High sink/source current:25mA Low power consumption
PERIPHERIAL FEATURES
Timer0:8 bit timer/counter with 8 bit prescaler Timer1:16 bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock Timer2:8bit timer/counter with 8 bit period register, prescaler and postscaler. One capture, compare, PWM module 10 bit multi channel ADC USART/SCI with 9 bit address detection Parallel slave port with 8 bit wide, with external RD,WR and CS controls (40/44 pins) Brown out circuitry detection for brown out reset (BOR).
INSTRUCTION FLOW/ PIPELINING

An instruction cycle consists of 4 Q cycles (Q1,Q2,Q3,Q4). Fetch takes one instruction cycle While decode and execute takes another instruction cycle. Due to pipelining each instruction effectively executes in one cycle. On change in program counter due to an Instruction extra cycle is required. Instruction fetch begins with the program counter incrementing in Q1.
INSTRUCTION FLOW/ PIPELINING

The fetched instruction is latched into the instruction register in Q1 during execution Cycle.This instruction is then decoded and executed during Q2, Q3 & Q4.Data is read during Q2(operand read) and written during Q4(destination write)
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Dig
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BLOCK DIAGRAM
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CENTRAL PROCESSING UNIT

The CPU is responsible for fetching the correct instruction for execution, decoding that instruction and executing that instruction. The CPU sometimes works in conjunction with the ALU to complete execution of the instruction. The CPU controls the program memory Address bus, the data memory bus and accesses to the stack.
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ALU
PIC contains 8 bit ALU and 8-bit working register. Arithmetic operation are twos compliment in nature. In two operands instruction, one operand is the Working register (W register an 8 bit working register used for ALU operation, it is not a addressable register). The other operand is a file register or an immediate constant. In Single operand instruction, the operand is either the W register or a File register.
STATUS REGISTER
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for Data memory. Since the selection of the data Memory bank is controlled by this register, it is required to be present in every bank. This register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C bits, then write to these bits is disabled.TO & PD bits are not writeable.
STATUS REGISTER
IRP
7 IRP
RP1
RP0
TO
PD
DC
Register select bank bit( indirect addressing)

1=Bank 2,3(10h-1ffh) 0=bank 0,1(00h-ffh)
6, RP1,R Register bank select bits(direct addressing) 5 P0 11=Bank 3(180h-1ffh) 10=Bank 2(100-17fh)
01=Bank 1(80h-ffh) 4 TO 00=Bank 0(00-7fh)
Time to live 1=After power up,CLRWDT or SLEEPinstruction 0=A WDT time out occurred
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STATUS REGISTER
3 PD Power down bit 1=After power up or by CLRWDT instruction 0=By execution of the SLEEP instruction Zero bit 1=if arithmetic and logical instruction result is zero Digit carry/borrow (polarity is reverse) bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) 1=carry out from the 4th LSB of the result occurred.
2 1
Z DC
Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instruction) 1=A carry out from the MSB of the result occurred.
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OPTION REGISTER
RBUP INTEDG TOCS TOSE PSA PS2 PS1 PS0
Bit 7
Symbol Function RBPU PORTB pull-up enable bit 1=PORTB pull ups are disabled 0=PORTB pull ups are enabled by individual port latch values
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OPTION REGISTER
Bit 6 Symbol Function INTEDG Interrupt edge select bit 1=Interrupt on rising edge of INT pin 0= Interrupt on falling edge of INT pin 5 TOCS TMR0 clock source select bit 1=Transition on TOCKL pin 0=Internal instruction cycle clock(CLKOUT) 4 TOSE TMR0 source edge select bit 1=Increment on High to low transition on TOCKL pin 0=Increment on low to high transition on TOCKL pin
OPTION REGISTER
Bit 3 Symbol Function PSA Prescalar assignment bit 1=prescalar is assigned to the WDT 0=prescalar is assigned to the Timer 0 module 2-0 PS2:PS0 Prescalar rate select bits
Bit value 000 001 010 011 100 101 110 111
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TMR0 rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
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PCON REGISTER
MPEEN
7
6 3 2 PER
MPEEN
PER
POR
BOR
memory parity error circuitry status bit

unimplemented :read as 0 memory parity error reset status bit 1=no error occurred 0=A program memory fetch parity error power on reset status bit 1=no power on reset occurred 0=A power on reset occurred Brown on reset status bit 1=No brown on reset status bit 0=A brown on reset occurred
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POR
BOR
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MEMORY ORGANIZATION
Three memory blocks
Program memory Data memory - general purpose RAM - Special function Register(SFR) control the peripheral modules. EEPROM data memory
which is used to
The program and data memory have separate buses so that access to each block can occur During the same oscillator cycle.
PROGRAM MEMORY
The PIC devices have a 13 bit program counter capable of addressing an 8Kx14 program memory space. The PIC16F870/71 devices has 2K x 14 words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h.Since all instruction are a single word, a device with an 8Kx14 program memory has space for 8K of instructions. This makes it much easier to determine if a device has sufficient program memory for the desired application. The program memory is divided into four pages of 2K words each (0h-7ffh, 800h-fffh,1000h -17ffh, 1800h-1fffh).
PROGRAM MEMORY(dig)
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PROGRAM COUNTER
The program counter (PC) specifies the Address of the instruction to fetch for execution. PC is 13 Bit wide. The lower byte is called the PCL Register which is readable and writeable. The high Byte is called PCH and is not directly readable or writeable. All updates to the PCH register goes through the PCLATH register.
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PROGRAM COUNTER(dig)
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DATA MEMORY
The data memory is made up of the general purpose register GPR (upper location) area and the special function register SFR (lower location) area. The SFRs control the operation of the device while the GPRs are the general area of the data storage and scratch pad operation. The data memory is banked for both the GPRs and SFRs areas.The GPR area is banked to allow greater than 96 bytes of general purpose RAM to be addressed. SFRs are for the registers that control the peripheral and core functions. The entire data memory can be accessed either directly or indirectly.
GENERAL PURPOSE REGISTER-GPR

GPRs are not initialized by a power on reset and are unchanged on all other times. The register file can be accessed either directly or using the FSR (File Select Register) indirectly. Some devices have areas that are Shared across the data memory banks, so a read/write to that area will appear as the same Location regardless of the current bank.
SPECIAL FUNCTION REGISTER-SFR

The SFRs are used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The SFRs can be classified into two sets those associated with the core function and those related to the peripheral function. Some SFRs are initialized by a power on reset and other resets, while other are unaffected. The register file can be accessed either directly or using the FSR indirectly.
BANKING
The data memory is partitioned into four banks. Each bank contains GPRs and SFRs. Switching between these tasks requires the RP0 and RP1 bits in the status register to be configured for the desired bank when using direct addressing. The IRP bit in the status register is used for Indirect addressing. Each bank Extends up to 7Fh (128bytes).
Accessed Banks RP<1:0> Indirect(IRP) 0 00 0
1
2 3
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10 11
0
1 1
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Direct and Indirect Addressing
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I/O PORTS-INTRODUCTION
General purpose I/O pins can be considered the simplest of peripherals. They allow PIC to monitor and control other devices. To add flexibility and functionality to a device, some pins are multiplexed with an alternate functions that depend on which peripheral features are on the device. In general when a peripheral is functioning that pin may not be used as a general purpose I/O pin.
I/O PORT
For most ports, the I/O pins direction is controlled by the data direction register called the TRIS register. A1 in the TRIS bit corresponds to the port being an input while a 0 corresponds to that pin being output. The port register is the latch for the data to be output. when port is read the device reads the level present on the I/O pins (not the latch). Reading the port register reads the status of the pins whereas writing to it will write to the port latch.all write operation are read modify write operations. Therefore a write to a port implies that the port pins are read ,this value is modified and then written to the port data latch.
Dig-gen
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PORTA and TRISA register

PORTA is a 6 bit wide bi-directional port and its data direction register is TRISA. The RA4 pin is a Schmitt trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Setting a TRISA register bit puts the corresponding output driver in a high impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pins Reading the PORTA register reads the status of the pins,whereas writing to it will write to the port latch.All write operations are read modify operations.
PORTA and TRISA register

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0clk1 pin is a Schmitt trigger input and an open drain output.All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog Vref input.The operation of each pins is selected by clearing/setting the control bits in the ADCON1 register. The TRISA register controls the direction of the RA pins even when they are being used as analog inputs.The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
Adig
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PORTB and TRISB register

PORTB is a 8 bit wide Bi-directional port and its data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a high impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pins. Four of PORTBs pins RB7:RB4 have an interrupt on change feature and only pins configured as inputs can cause this interrupt to occur. Each of the PORTB pins has a weak internal pull-up.A single control bit can turn on all the pull-ups.This is performed by clearing bit RBPU.The weak pull up is automatically turned off when the port pin is configured as an output.The pull-ups are disabled on a Power on Reset.

The input pins (RB7:RB4) are compared with the old values latched on the last read of PORTB. The mismatch outputs of RB7:RB4 are ORed together to generate the RB port change interrupt with flag bit RBIF.This interrupt can awake the device from SLEEP. The user in the interrupt service routine can clear the interrupt in the following manner:
1) Any read or write of PORTB. This will end the mismatch condition. 2) Clear flag bit RBIF

A mismatch condition will continue to set the flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software pull-ups on these four pins allow easy interface to a keypad and make it possible for wake up on key depression Polling of PORTB is not recommended while using the interrupt on change feature.
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Bdig
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PORTC and TRISC register

PORTC is an 8 bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions and have Schmitt trigger input buffers. When enabling peripherals functions, care should be taken in defining
TRIS bits for each PORTC pins as some peripherals

override the TRIS bit to make a pin an input.
Cdig
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PORTD/PORTE
PORTD, PORTE and its registers TRISD, TRISE register are made up of an 8 bit port with Schmitt trigger input buffers.Each pin is individually configurable as an input or output
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Dig
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PORTF and PORTG

PORTF, PORTG and its registers TRISF, TRISG register are a digital input only port.Each pin is multiplexed with an LCD segment driver.These pins have Schmitt trigger input buffers.
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dig
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dig
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GPIO and TRISGP register

GPIO is an 8 bit I/O register. Only the low order six bits are implemented (GP5:GP0). Bits 7 and 6 are unimplemented and read as 0s any GPIO pin(expect GP3) can be programmed individually as input or output. The GP3 pin is an input only pin . The TRISGP register controls the data direction for GPIO pins.A 1 in the TRISGP register bit puts the corresponding output driver in a high impedance mode.A 0 puts the content of the output data latch on the selected pins enabling the output buffer.
GPIO and TRISGP register

A read of the GPIO port reads the pins not the output data latches.Any input must be present until read by an input.The output are latched and remain unchanged until the output latch is rewritten. The configuration word can be set several I/O to alternate functions the pins will read as 0 during port read .The GP0 ,GP1 and GP3 pins can be configured with weak pullups and also with interrupt on change.The interrupts on change and weak pullups functions are not pin selectable.
dig
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Successive operation on an I/O port

The actual write to an I/O port happened at the end of an instruction cycle whereas for reading the data must be valid at the beginning of the instruction cycle.
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Dig
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Successive operation on an I/O port

As the effective capacitance (C) becomes larger, the rise/fall time of the I/O pin increases. As the device frequency increases or the effective capacitance, the possibility of the subsequent PORTx read modify write instruction issue increases.
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INTERRUPTS
PIC can have many sources of interrupt. These sources generally include one interrupt source for each peripheral module, though some module may generate multiple interrupts (USART). The interrupts are
-INT pin interrupt (external interrupt) -TMR0 overflow interrupt -PORTB change interrupt (pins RB7:RB4)
INTERRUPTS
Comparator change interrupt Parallel slave port interrupt USART interrupt Receive interrupt Transmit interrupt A/D conversion complete interrupt LCD interrupt Data EEPROM write complete interrupt Timer1 overflow interrupt Timer2 Overflow interrupt CCP interrupt SSP interrupt
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INTERRUPTS
There is one register used in the control and status of the interrupt. The register is INTCON If the device has peripheral interrupt, then it will have registers to enable the peripheral interrupts and registers to hold the interrupt flag bits.
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INTERRUPTS
Depending on the devices, the registers are:
PIE1 PIR1 PIE2 PIR2 (PIR3,PIE3 could be used for future use)
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Control Registers
Generally devices have a minimum of three registers associated with interrupts.The INTCON register which contains GIE bit, PEIE bit and the PIE/PIR register pair which enable the peripheral interrupts and display the interrupt flag status. INTCON register
The INTCON register is readable and writeable register which contains various enable and flag bits
INTCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE
7 GIE
PEIE(3) TOIE
INTE(2) RBIE(1,2) TOIF
INTF(2)
RBIF(1,2)
Global Interrupt Enable Bit 1=Enable all unmasked interrupt 0=Disable all interrupts
6 PEIE
Peripheral interrupt enable bit 1=Enable all un-masked peripheral interrupts 0=Disables all peripheral interrupts
TMR0 overflow interrupt enable bit 1=Enable the TMR0 overflow interrupt 0=Disable the TMR0 overflow interrupt
5 TOIE
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INTCON REGISTER
4 INTE INT External interrupt enable bit 1=Enable the INT external interrupt 0=Disable the INT external interrupt RB Port change interrupt Enable bit 1=Enable the RB port change interrupt 0=Disable the RB port change interrupt TMR0 overflow interrupt flag bit 1=TMR0 register has overflowed(cleared In s/w) 0=TMR0 register did not overflow INT External Interrupt Flag bit 1=The INT external interrupt occurred(cleared in S/W) 0=The INT external interrupt did not occur RB port change interrupt flag bit 1=At least one of the RB7:RB4 pins changed state 0=None of theRB7:RB4 pins have changed state
3 RBIE(1)
2 T0IF
1 INTF
0 RBIF(1)
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PIE REGISTER
Depending on the number of peripheral interrupt sources,there may be multiple PIE registers (PIE1,PIE2) which contains the individual enable bits for the peripheral interrupts. If the device has a PIE register, the PEIE bit must be set to enable any of these peripheral interrupts.
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PIE1 REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 PSPIE ADIE
7
6 5 4 3 2 1 0
R/W-0
R/W-0 TMR1IE
RCIE
TXIE
CCP1IE TMR2IE
PSPIE
ADIE RCIE TXIE Un-impl CCP1IE TMR2IE TMR1IE
Parallel Slave Port Read/write interrupt enable bit 1=Enable the PSP read/write interrupt
A/D converter interrupt enable bit 1=Enable the A/D interrupt USART Receive interrupt enable bit 1=Enable the USART receive interrupt USART Transmit interrupt enable bit 1=Enable the USART transmit interrupt Read as 0 CCP1 interrupt enable bit 1=Enable the CCP1 interrupt TMR2 to PR2 match interrupt enable bit 1=Enable the TMR2 to PR2 match interrupt TMR1 Overflow interrupt enable bit 1=Enable the TMR1 overflow interrupt Accel Software &Technologies Limited
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PIE2 REGISTER
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
EEIE
7-5,3-0 Un-impl Read as 0 4 EEIE EEPROM Write operation Interrupt Enable 1=Enable EE write Interrupt
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PIR1 REGISTER
R/W-0 R/W-0 R-0 PSPIF ADIF
7 PSPIF
R-0
U-0 R/W-0
R/W-0
R/W-0
RCIF TXIF -
CCP1IF TMR2IF TMR1IF
Parallel slave port read/write interrupt flag bit 1=A read or a write operation has taken place 0=No read or write occurred
A/D converter Interrupt flag 1=An A/D conversion completed 0=An A/D conversion is not complete USART Receive interrupt enable bit 1=Enable the USART receive interrupt USART Transmit interrupt enable bit 1=Enable the USART transmit interrupt
ADIF
5 4
RCIE TXIE
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PIR1 REGISTER
3 Un-impl Read as 0 CCP1 Interrupt Flag bit Capture mode 1=A TMR1 Register capture occurred Compare Mode 1=A TMR1 register compare match occurred PWM mode Unused in this mode 2 CCP1IF
1 TMR2I F
TMR2 To PR2 match interrupt flag bit 1=TMR2 to PR2 match occurred
0 TMR!IF TMR1 overflow interrupt flag bit 1=TMR1 register overflowed
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PIR2 REGISTER
U-0 7-5,3-0 4 U-0 U-0 Un-impl EEIF R/W-0 EEIF U-0 U-0 U-0 U-0 -
Read as 0 EEPROM Write operation Interrupt Flag bit 1=The write operation is completed
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INTERRUPT LATENCY
Interrupt latency is defined as the time from the interrupt event (the interrupt flag bit gets set) to the time that the instruction at address 0004h starts execution (when that interrupt is enabled). For synchronous interrupts (internal), the latency is 3TCY and for asynchronous (external) such as the INT or PORT RB change interrupt,the latency is 3-3.75 TCY. The exact latency depends upon when the interrupt event occurs in relation to the instruction cycle.The latency is the same for both 1 and 2 instruction cycle. CONTEXT SAVING DURING INTERRUPT During the interrupt only the return PC value is saved on the stack. POP and PUSH are not instruction mnemonics, but are conceptual actions.
INT and EXTERNAL INTERRUPTSdig
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TIMER 0
Features:
8
bit timer/counter Readable and writeable 8 bit software programmable prescaler Clock source selectable to be external or internal Interrupt on overflow from FFh to 00h Edge select for external clock for incrementing the timer. 0-Rising edge.
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TIMER0
Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, Timer0 module will increment every instruction cycle. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CK1. The incrementing edge is determined by Timer0 source edge select bit T0SE(OPTION_REG<4>). Clearing bit T0SE selects the rising edge.
TIMER0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared by Timer0 interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut of during SLEEP.
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TIMER0 with an External clock

When no prescalar is used, the external clock input is the same as the prescalar output. The synchronization of T0CK with internal phase clocks is done by sampling the prescalar output on the Q2 and Q4 cycles of the internal phase clocks. It is necessary for T0CKI to be high for at least 2Tosc and low for 2Tosc.
Prescaler
A prescaler assignment for Timer0 module means that there is no prescaler for watchdog timer and vice versa. This prescaler is not readable or writeable. The PSA and PS2-PS0 bits (OPTION_REG<3:0) determine the prescaler assignment and prescaler ratio. When assigned to timer0 module, all instructions writing to TMR0 register will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear prescaler along with watchdog timer.
CONTROL REGISTER OPTION_REG register

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG
7 RBPU(1)
T0CS
T0SE
PSA
PS2
PS1
PS0
Weak pull up enable bit 1=Weak pull-ups are disabled 0=Weak pull ups are enabled by individual port latch values
Interrupt Edge Select Bit 1= Interrupt on rising edge of INT pin 0=Interrupt on Falling Edge of INT pin TMR0 Clock source Select bit 1=Transition on T0CK1 pin 0=Internal instruction cycle clock(CLKOUT) TMR0 source edge select bit 1=increment on high to low transition on T0CK1 pin 0=increment on low to high transition on T0CK1 pin Prescaler assignment bit 1=Prescaler is assigned to the WDT 0=Prescaler is Accel Software &Technologies assigned to the TIMER0 module
Limited
6 INTEDG
5 T0CS
4 T0SE
3 PSA
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CONTROL REGISTER
Bit 2:0 Symbol Function PS2:PS0 Prescaler rate select bits Bit value 000 001 010 011 100 101 110 111
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TMR0 rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
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TIMER1
The Timer1 is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H & TMR1L), which are readable and writeable. The TMR1 register pair increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt if enabled is generated on overflow latched in interrupt flag bit TMR1F (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1E (PIE1<0>).
TIMER1
Timer1 can operate in two modes: As a timer. As a counter. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, Timer1 increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal reset input.
T1CON Register
U-0 7-6 5-4 3 2 1
U-0 -
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T10SCEN T1SYNC TMR1CS TMR1ON

Read as 0 Timer 1 input clock prescaler select bits 11 1:8; 10 1:4; 01 - 1:2; 00 1:1 Timer 1 osc. Enable control bit 1 osc. is enabled Timer 1 ext. clock input synchronisation control bit 0 syn ext. clock input Timer 1 clock source select bit 1 extl. Clk 0 intl. Clk Timer 1 on bit 1 enable
Unimplemented T1CKPS1/0 T1OSCEN T1SYNC TMR1CS
TMR1ON
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TIMER1
Timer mode: Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to timer is Fosc/4. Counter mode: Timer1may operate in asynchronous or synchronous mode depending on the setting of TMR1CS bit.After Timer1 is enabled in counter mode, the module must have a falling edge before the counter begins to increment. Synchronized counter mode: Counter mode is selected by setting bit TMR1CS. In this mode,the timer increments on every rising edge of clock input on pin RC1/T1OSI.If T1SYNC is cleared,then external clock input is synchronized with internal phase clocks.
TIMER1
Synchronization is done after the prescaler stage.The prescaler stage is an asynchronous ripple counter. A synchronized counter mode: If control bit T1Sync is set,the external clock input is not synchronized.the timer continues to increment asynchronous to the internal phase clocks.the timer will continue to run during SLEEP and can generate an interrupt on overflow,which will wake up the processor.Reading TMR1H or TMR1L while the timer is running from external asynchronous clock will guarantee a valid read.for writes,it is recommended that the user simply stop the timer and write the desired values.
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TIMER1
Timer1 Oscillator: A crystal oscillator circuit is built in between pins T1OSI and T1OSO.it is enabled by setting control bit T1OSCEN.the oscillator is a low power oscillator rated up to 200khz.It will continue to run during SLEEP.It is primarily intended for use with a 32 kHz crystal.The Timer1 oscillator is identical to the LP oscillator. Resetting timer 1 using CCP1 Trigger Output: If the CCP1 module is configured in compare mode to generate a special event trigger,that will reset Timer1.Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature.If running in asynchronous counter mode,reset will not work.
TIMER1
Resetting of Timer1 register pair(TMR1H,TMR1L): TMR1H and TMR1L register are not reset to 00h on a POR or any other reset except by the CCP1 special event trigger.T1CON register is reset to 00h on a POR or a BOR,which shuts off the timer and leaves a 1:1 prescaler.In all other resets,the register is unaffected.
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TIMER2
Timer2 is an 8-bit timer with a prescaler and a postscaler .it can be used as the PWM time-base for the PWM mode of the CCP modules.The TMR2 register is readable and writable,and is cleared on any device reset.The input clock has a prescale option of 1:1,1:4or 1:16 selected by control bits T2CKPS1:T2CKPS0. The Timer2 module has an 8 bit period register PR2.Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increments cycle.PR2 is a readable and writable register.
T2CON register
U-0 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0
7-6 6-3
Unimplemented TOUTPS3-0
Read as 0 Timer 2 output post scale select bits 0000 1:1; 0001 1:2;0010- 1:3..1111-1:16 post scale Timer 2 on bit 0 Timer2 off Timer 2 clock Prescale select bits source select bit 00=Prescaler is 1;01-prescaler is 4,1x=prescaler is 16
T1SYNC
1-0
T2CKPS1-0
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TIMER2
Timer2 Prescaler and Postscaler: The prescaler and postscaler counter are cleared when any of the following occurs: A write to the TMR2 register A write to the T2COn register Any device reset TMr2 is not cleared when T2CON is written Output of TMR2 The output of TMR2 is fed to the SSPort module,which is optionally used it to generate shift clock.
dig
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97
CAPTURE/COMPARE/PWM MODULE
The capture/compare/PWM module(CCP) contains a 16 bit register which can operate as a : 16 bit Capture register 16 bit compare register PWM master/slave duty cycle register CCP1 module: The CCPR1 is comprised of two 8 bit registers:CCPR1L and CCPR1H.The CCP1CON register controls the operation of CCP1.The special event trigger is generated by a compare match and will reset Timer1 and start A/d conversion
CCP1CON register
U-0 U-0 R/W-0 7-6 5-4
R/W-0 CCP1Y
R/W-0 CCP1M3
R/W-0 CCP1M2
R/W-0 CCP1M1
R/W-0 CCP1M0
CCP1X
Unimplemented CCP1<X:Y>
Read as 0 PWM least significant bits Capture mode &Compare mode-unused PWM mode-These bits are the two LSBs of the PWM duty cycle.the eight MSBs are found in CCPR1L CCPx mode select bits 0000-CCP off 0100-capture mode,every falling edge 0101- capture mode,every rising edge 0110- capture mode,every 4th rising edge 0111- capture mode,every 16th rising edge 1000-CCP1IF bit is set 1001-CCP1IF bit is set 1010-CCP1IF bit is set,CCP pin is unaffected 1011-CCP1IF bit is set,CCP pin is unaffected(A/D module is enabled) 11xx-PWM mode Accel Software &Technologies 99 Limited
3-0
CCP1M<3:0>
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CCP MODE-TIMER RESOURCE REQUIRED

CCP mode Timer Resource Capture Timer1 Compare Timer1 PWM timer2 CAPTURE MODE In capture mode CCPR1H:CCPR1L captures the 16 bit value of the TMR1 register when an event occurs on pin RC2/CCP1.An event is defined as:
Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge
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An event is selected by control bits CCP1M<3:0>.when a capture is made the interrupt request flag bit CCP1F is set.The interrupt flag must be cleared in software.If another capture occurs before the value in register CCPR1 is read ,the old capture value will be lost. CCP pin configuration In capture mode the RC2/CCP1pin should be configured as an input by setting the TRISC<2> bit. dig
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Timer1 mode selection Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature.In asynchronous counter mode the capture mode doesnt work. Software interrupt When the capture mode is changed a false capture interrupt may be generated.the user should keep CCP1E(PIE<2>) bit clear to avoid false interrupts and should clear the flag bit CCP1F following any such change in operating mode.
CCP prescaler
There are 4 prescaler Settings (CCP1M<3:0>).Whenever the CCP module is turned off or the CCP module is not in capture mode,the prescaler counter is cleared.Switching between capture prescaler generates interrupts.
Compare mode
In compare mode the 16 bit CCPR1 register value is constantly compared against the TMR1 register pair value.when a match occurs the RC2/CCp1 pins are:
Driver high Driven Low Remains unchanged
CCP pin configuration The user must configure the RC2/CCp1 pin as an output byclearing the TRISC<2>bit. Timer1 mode selection Timer1 must be running in timer mode or synchronized counter mode. Software interrupt mode When generate software interrupt mode is chosen,the CCp1 pin is not affected.The CCP1F bit is set causing a CCP interrupt. Special event trigger Here internal hardware trigger is generated.special event trigger output of CCP1 resets the TMR1 register pair and starts A/D conversion.
PWM mode In pulse width modulation the CCP1 pin produces upto a 10bit resolution PWM output.Since the CCP1 pin is multiplexed with the PORTC data latch,the TRISC<2> bit must be cleared to make CCP1 pin an output. PWM output PR2=Fosc /4*Fpwm*TMR2Prescale value 1 PWM duty cycle =(CCPR1L:CCP1CON<5:4>*Tosc*(TMR2 prescale value) Resolution=Log(Fosc/Fpwm)/Log(2) bits
dig
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106
dig
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107
USART
The USART is one of the two serial I/O module and is also know n as serial communication interface or SCI. The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs.
USART
The USART can be configured in the following modes: -Asynchronous(full duplex) -Synchronous-master(half duplex) -Synchronous-slave(half duplex) The USART module also has a multiprocessor communication capabilities using 9-bit address detection.
CONTROL REGISTERS
RCSTA-Receive status and control registers(add-98h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
SPEN
7 SPEN 6 RX9
RX9
SREN
CREN ADDEN
FERR
OERR
RX9D
Serial port Enable bit 1=Serial port enabled 9-bit Receive Enable bit 1=Select 9-bit reception 0=Select 8-bit reception
5 SREN
Single receive Enable bit Asynchronous mode,dont care, Synchronous master 1=Enable single receiver This bit is cleared after reception is complete Synchronous mode-slave unused in this mode
4 CREN Continuous Receive enable bit Asynchronous mode 1=Enable continuous receive Synchronous mode 1=Enable continuous receive until enable bit CREN iscleared
CONTROL REGISTERS
3
ADDEN Address detect enable bit Asynchronous mode 9-bit (RX9=1) 1=Enable address detection,enable interrupt and load of the receive buffer when RSR<8> is set 0=Disable address detection,all the bytes are received and 9th bit can be used as parity bit FERR Framing Error bit 1=Framing error 0=NoFraming error 0=No overrun error
2 1
0
OERR
RX9D
Overrun error bit 1=overrun error
9th bit of receive data,can be a parity bit
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CONTROL REGISTERS
TXSTA-Transmit status and control registers(add 98h) R/W-0 R/W-0 R/W-0 R/W-0 R-0 CSRC
7 CSRC
R-0 TRMT
R-X TX9D
TX9
TXEN
SYNC
BRGH
Clock source select bit Asynchronous mode dont care Synchronous 1=Master mode(clock generated internally from BRG) 0=Slave mode(Clock from external source)
6
5 4 3 2 1 0
TX9
TXEN SYNC Unimpl BRGH TRMT 13/12/04 TX9D
9-bit transmit Enable bit 1=Select 9-bit transmission

Transmit Enable bit 1=Transmit enable USART mode select bit 1=Synchronous mode read as 0 High Baud Rate select bit 1=High speed
0=Select 8-bit transition 0=Transmit Disable 0=Asynchronous mode
0=Low speed
Transmit shift register status bit 1=TSR empty 0=TSR full Accel Software &Technologies 9th bit of transmit data,can be a parity bit Limited
112
USART BAUD RATE GENERATOR(BGR)

The BGR is a dedicated 8 bit baud rate generator and this supports both asynchronous and synchronous modes of USART The SPBRG register controls the period of free running 8 bit timer. In asynchronous mode BRGH (TXSTA<2>) controls the baud rate generator, but in synchronous mode the bit is ignored. Formula:
SYNC BRGH=0(LOW) BRGH=1(HIGH)
0 1
(ASYN)BR=Fosc/64(X+1)) (SYN)BR=Fosc/4(X+1))
BR=Fosc/16(X+1)) NA
X value in SPBRG ( 0-255)

USART ASYNCHRONOUS MODE

In this mode,the USART uses the standard NRZ format(1 start bit,8-9 data bits and 1-stop bit) The USARTs transmits and receives the LSB first.the transmitter and receiver are functionally independent,but use the same data format and baud rate. Asynchronous mode is selected by clearing the sync (TXSTA<4>) bit The USART asynchronous module consists of the following important elements
Baud rate generator sampling circuit Asynchronous transmitter Asynchronous receiver
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USART ASYNCHRONOUS TRANSMITTER

Steps: Initialize the SPBRG register for the appropriate baud rate.If a high speed baud rate is desired set bit BRGH Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN If interrupt are desired,the set enable bit TXIE. If 9 bit transmission is desired,then set transmit bit TX9 Enable the transmission by setting TXEN bit which will also set bit TXIF If 9 bit transmission is selected,the 9th bit should be loaded in bit TX9D Load data to the TXREG register (starts transmission)
dig
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116
dig
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117
USART ASYNCHRONOUS RECIEVER

Initialize the SPBRG register for the appropriate baud rate.If a high speed baud rate is desired,set bit BRGH Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN If interrupts are desired,then set enable bit RCIE If 9 bit reception is desired the set bit RX9 . Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. Read the RCSTA register to get the 9th bit(if enabled) and determine if any error occurred during reception. Read the 8 bit received data by reading the RCREG register If any error occurred,clear the error by clearing enable bit CREN
dig
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119
Dig
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120
SETTING UP 9 BIT MODE

Initialize the SPBRG register for the appropriate baud rate.If a high speed baud rate is desired, set bit BRGH. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired,then set enable bit RCIE Set bit RX9 to enable 9-bit reception Set ADDEN to enable address detect Enable the reception by setting enable bit CREN.

Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the 9th bit and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register,to determine if the device is being addressed. If any error occurred,clear the error by clearing enable bit CREN.
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If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer,and interrupt the CPU.
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123
Dig
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124
dig
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125
dig
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126
USART SYNCHRONOUS MASTER MODE

Steps when setting up a synchronous master Transmission: Initialize the SPBRG register for the appropriate baud rate Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired,set enable bit TXIE If 9-bit transmission is desired, set bit TX9 Enable the transmission by setting bit TXEN If 9-bit transmission is selected,the 9th bit should be loaded in bit TX9D Start transmission by loading data to the TXREG register.
dig
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128
dig
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129
USART synchronous master reception

Initialize the SPBRG register for the appropriate baud rate Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC Ensure bits CREN and SREN are clear. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, set bit RX9 If a single reception is required, set bit SREN and for continuous reception set bit CREN. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the 9th bit(if enabled)and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred clear the error by clearing bit CREN.
dig
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131
USART SYNCHRONOUS SLAVE MODE

Slave mode transmission: Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired,then set enable bit TXIE If 9-bit transmission is desired ,the set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected the 9th bit should be loaded in bit TX9D. Start transmission by loading data to the TXREF register.
USART SYNCHRONOUS SLAVE MODE

Slave mode reception: Enable the synchronous master serial port by setting bits SYNC and SPEN and CLEARING bit CSRC. If interrupts are desired,set enable bit RCIE If 9-bit reception is desired,set bit RX9. To enable reception,set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated,if enable bit RCIE was set. Read the RCSTA register to get the 9th bit(if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred ,clear the error by clearing bit CREN.
A/D module
The A/D converter module has five to eight inputs depending on the PIC. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode The A/D module has four registers are: A/D Result High Register(ADRESH) A/D Result Low Register(ADRESL) A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1) The ADCON0 register controls the operation of A/D module. The ADCON1 register configures the functions of port pins. The ADRESH/ADRESL registers contain the 10-bit result of A/D conversion. When the conversion is complete the result is loaded in A/D result register pair, the GO/DONE bit is cleared and the A/D interrupt flag is set.
ADCON0 Register
R/W-0 ADCS1 7-6 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 R/W-0 ADON ADCS1-ADCS0 A/D conversion clock selection bits 00=Fosc/2 01=Fosc/8 10=Fosc/32 11=FRC(clock derived from an RC oscillation) 5-3 2 CHS2-CHS0 GO/DONE Analog Channel select bits A/D conversion status bit 1=A/D conversion in progress 0=A/D conversion not in progress Read as 0 A/D On bit 1=A/D converter module is operating 0=A/D converter module is shutoff and consumes no operating current.
1 0
Unimpl ADON
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ADCON1 REGISTER
U-0 ADFM U-0 R/W-0 U-0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0
ADFM
A/D Result format select 1=Right justified.6 most significant bits of ADRESH are read as 0.
6- Unimpl Read as 0 4 3- PCFG3:PC A/D Port configuration control bits 0 FG0
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A/D conversion
Configure the A/D module Configure analog pins / voltage reference / and digital I/O (ADCON1). Select A/D input channel(ADCON0). Select A/D conversion clock(ADCON0) Turn on A/D module(if desired). Configure A/D interrupt(if desired) Clear ADIF bit Set ADIE bit Set GIE bit Wait the required acquisition time
A/D conversion
Start conversion: -Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete , by either -Polling for the GO/DONE bit to be cleared Or Waiting for the A/D interrupt. Read A/D result register pair (ADRESH - ADRESL), clear bit ADIF if required. For next conversion, go to step1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAB is required before next acquisition starts.
SPECIAL FEATURES OF THE CPU

These devices have a host of features intended to maximize system reliability, minimize cost through eliminating of external components, provide power saving operating modes and offer code protection.These are: OSC Selection Reset Power on Reset (POR) Power up Timer (PWRT) Oscillator Start up timer (OST) Brown out Reset (BOR). Interrupts Watch Dog Timer SLEEP Code protection ID locations In circuit Serial Programming In circuit Debugger
SPECIAL FEATURES OF THE CPU

These devices have a watch dog timer, which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power up. One is the OST. Intended to keep the chip in reset until the crystal oscillator is stable. The other is PWRT which provides a fixed delay of 72 ms on power up only. SLEEP mode is designed to offer a very low current powerdown mode.The user can wake from SLEEP through external reset.Watchdog Timer wake-up or through an interrupt.The RC oscillator option saves power.A set of configuration bits are used to select various option.
CONFIGURATION WORD
CP1 CP0 DEBUG WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
13-12 5-4 CP1:0 Flash Program Memory code protection 11-Code protection off 10-Not Supported 01-Not supported 00-Code Protection In circuit Debugger mode 1-In circuit debugger disabled,RB6 and RB7 are general purpose I/O pins 0-In circuit debugger disabled,RB6 and RB7 are general purpose I/O pins Read as 1 Flash Program Memory Write Write Enable 1=Unprotected program memory may be written to by EECON control
11
DEBUG
10 9
Unimple WRT
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CONFIGURATION WORD
8 CPD Data EE Memory Code protection 1=Code protection off 0=Data EEPROM memory code protected. Low voltage in circuit serial programming enable bit 1=RB3/PGM pin has PGM function ,low voltage program enabled 0=RB3 is digital I/O,HV on MCLR must be used for programming Brown out reset enable bit 1= BOR enabled 0= BOR disabled Power up timer enable bit 1= PWRT disabled 0=PWRT Enabled
LVP
6 3 2
BODEN PWRTE
WDTE
watch dog timer enable bit 1=WDT enabled 0=WDT disabled 11-RC oscillator 01=XT oscillator 10=HS oscillator 00=LP oscillator
142
1-0 FOSC1:FOSC0 Oscillator selection bit
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OSCILLATOR CONFIGURATION
Oscillator types: It can be operated in four different oscillator Modes. The user can program two configuration bits (FOSC1, FOSC0), to Select one of these modes.
LP- low power crystal XT-Crystal /resonator HS-High speed crystal/resonator RC-Resistor/Capacitor
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation.
Dig
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RC OSCILLATOR
RC oscillator frequency is a function of supply voltage, the resistor (REXT) and Capacitor (CEXT) values and the operating temperature. The user need to take account variation due to tolerance of external R and C components used.
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145
dig
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146
RESET
Kinds of RESET:
Power on reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT reset (during normal operation) WDT wakeup (during SLEEP) Brown out reset (BOR)
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RESET
Some registers are not affected in any reset conditions. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a reset state on POR, on the MCLR and WDT reset, on MCLR reset during SLEEP, and BOR. They are not affected by a WDT wakeup which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different resets. These devices have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. WDT reset does not drive MCLR pin low.
POR
A POR pulse is generated on-chip when VDD rise is detected. POR pin ties MCLR directly to VDD that would eliminate external RC components usually needed to create a POR. When the device starts normal
operations, device operating parameters must be met to

ensure operation. If conditions are not met the device must be held in reset until operating conditions are met. BOR can be used to meet the start up conditions.
PWRT
The PWRT provides a fixed 72ms nominal timeout on power up only from POR The chip is kept active as long as the PWRT is active. A configuration bit is provides to enable/disable the PWRT. The PWRT time delay will vary from chip to chip due to VDD, temperature and process variation.
OST
The OST provides 1024 oscillator cycle delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is involved only for XT, LP and HS modes and only on power on reset or wake up from SLEEP.
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BOR
The configuration bit BODEN can enable or disable the BOR.
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DATA EEPROM
The data EEPROM and FLASH program memory are readable and writeable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space.
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DATA EEPROM
There are six SFRs used to read and write the program and data EEPROM memory.
EECON1 EECON2 EEDATA EEDATH EEADR EEADRH
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DATA EEPROM
The EEPROM data memory allows bytes read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EPROM location being accessed. The registers EEDATH and EEADRH are not used for data EEPROM access. These devices have 64bytes of data EEPROM with an address range from 0h to 3Fh.
DATA EEPROM & FLASH PROGRAM MEMORY

The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip to chip. Program memory access allows for checksum calculation and calibration table storage. A Byte or word write automatically erases the location and writes the new data. The program memory cannot be accessed during the write, therefore code cannot execute.
DATA EEPROM & FLASH PROGRAM MEMORY

During the write operation, the oscillator continues to clock the peripherals, and they continue to operate. Interrupt events will be detected and queued until the write is completed. When write is completed the next instruction in the pipeline is executed. When interfacing to program memory block, the EEDATH:EEDATA registers form a two byte word which holds the 14-bit data for read/write. The EEADRH:EEADR registers form a two byte word which holds the 13-bit address of the FLASH location being accessed.
DATA EEPROM & FLASH PROGRAM MEMORY The PIC16F870/871 devices have 2K words of program FLASH with an address range from 0h to 7FFh. The unused upper bits in both the EEDATH and EEDATA registers all read as 0s. The value written to program memory does not need to be a valid instruction.
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EEADR
The address registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 8K words of program FLASH. When selecting a program address value, the MSB byte of the address is in EEADRH register and LSB byte register is in EEADR register. When selecting a data address value, only the LSByte of the address is written to the EEADR register
EECON1 And EECON2 REGISTER

EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all 0. The EECON2 register is used exclusively in the memory write sequence. Control bits EEPGD determines if the access will be a program or a data memory access. Control bits RD and WR initiate read and write operations
EECON1 And EECON2 REGISTER

The WREN bit when set will allow a write operations. On power up the WREN bit is cleared. The WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time out reset during normal operation. Interrupt flag bit EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.
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EECON1 REGISTER
R/W-X U-0 U-0 U-0 R/W-X R/W-0 R/W-0 R/W-0 RD EEPGD 7 EEPGD
WRERR WREN WR
Program/ Data EEPROM select bit 1=Accesses Program memory 0=Accesses data memory EEPROM Error Flag Bit 1=A write operation is prematurely terminated 0=The write operation is complete EEPROM write enable bit 1=Allow write cycle 0= Inhibits write to the EEPROM Write control bit 1=Initialize a write cycle0=Write cycle to the EEPROM is complete Read control bit 1=Initialize an EEPROM read RD is cleared in H/W.The RD bit can only be set in S/W 0=Does not initialize an EEPROM read
6-4 Unimplemented Read as 0

3 WRERR
2 1 0
WREN WR RD
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Reading the data EEPROM memory

To read a data memory location, the user must write the address to the EEADR register, clear The EEPGD control bit and then set control bit RD. The data is available in the very next instruction cycle of the EEDATA register, therefore it can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user.
Writing to the data EEPROM memory

To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The WREN bit in EECON1 must be set to enable writes. The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN is not cleared by H/W. At the completion of write cycle, the WR bit is cleared in H/W and EEPROM write complete Interrupt Flag bit(EEIF) is set. EEIF must be cleared by software.
Reading the FLASH Program memory

A program memory location may be read by writing two bytes of the address to the EEADR and EEADRH register, setting the EEPGD control bit and then setting control bit RD. The data is available in the EEDATA and EEDATH register after the second NOP instruction. It is read as 2 bytes in the following instruction. The EEDATA and EEDATH registers will hold this value until another read operation or it is written to by the user.
Writing to the FLASH Program memory

When PIC are fully protected or not code protected, a word of the FLASH program memory may be written provided the WRT configuration bit is set. If PIC are partially code protected, then a word is in a non-code protected segment of memory and the WRT configuration bit is set. To write a FLASH program location, the first two bytes of the address must be written to the EEADR and EEADRH register and two bytes of the data to the EEDATA and EEDATH register,set the EEPGD control bit and then set control bit WR.
INSTRUCTIONS
ADDLW add literal and W Syntax [label] ADDLW K Operands: 0<=k<=255 Operation: (w)+k->(w) Status affected: C,DC,Z Description: The contents of the W register are added to the eight bit literal k and the result is placed in the w register. ADDWF add W and F Syntax [label] ADDWF f,d Operands: 0<=f<=127 ; d[0,1] Operation: w+f->destination Status affected: C,DC,Z Description: The contents of the W register are added to register f.If d is 0 the result is stored in W register else in F register.
INSTRUCTIONS
ANDLW and literal and W Syntax [label] ANDLW K Operands: 0<=k<=255 Operation: (w) AND k->(w) Status affected: C,DC,Z Description: The contents of the W register are ANDed to the eight bit literal k and the result is placed in the w register. ANDWF and W and F Syntax [label] ANDWF f,d Operands: 0<=f<=127 ; d[0,1] Operation: w AND f->destination Status affected: C,DC,Z Description: The contents of the W register are ANDed to register f.If d is 0 the result is stored in W register else in F register.
INSTRUCTIONS
BCF Bit clear F Syntax [label]BCF f,b Operands 0<=f<=127 ;0<=b<=7 Operation: 0->(f<b>) Status affected none Description: bit b in register f is cleared BSF Bit set F Syntax [label]BSF f,b Operands 0<=f<=127 ;0<=b<=7 Operation: 0->(f<b>) Status affected none Description: bit b in register f is set
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INSTRUCTIONS
BTFSS bit test f,Skip if Set Syntax: [label]BTFSS f,b Operands: 0<=f<=127 ;0<=b<7 Operation: skip if (f<b>)=1 Status affected none Description: If b in register f is 0,next instruction is executed.if b is 1 the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction. BTFSC bit test f,Skip if Clear Syntax: [label]BTFSC f,b Operands: 0<=f<=127 ;0<=b<7 Operation: skip if (f<b>)=1 Status affected none Description: If b in register f is 0,next instruction is executed.if b is 1 the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction
INSTRUCTIONS
CALL Syntax: operands Operation: Status affected Description: the stack. CLRF Syntax: Operands: Operation: Status affected: Description:
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call subroutine [label] call k 0<=k<=2047 (PC)+1->TOS;k->PC<10:0>;(PCLATH<4:3>)>PC<12:11> none call subroutine,First return address(PC+1) is pushed onto clear F [label]CLRF f 0<=f<=127 00h->f 1->Z Z the contents of register f are cleared and the Z bit is set.
INSTRUCTIONS
CLRW clear W Syntax: [label]CLRW Operands: 0<=f<=127 Operation: 00h->f 1->Z Status affected: Z Description: the contents of register W are cleared and the Z bit is set. CLRWDT clear Watch dog timer Syntax: [label]CLRWDT Operands: none Operation: 00h->WDT,0->WDT prescaler,1->TO,1->PD Status affected: TO,PD Description: this resets the WDT and its prescaler of the WDT.Status bits TO & PD are set.
INSTRUCTIONS
COMF Complement f Syntax [label] COMF f Operands: 0<=f<=127 ; d[0,1] Operation: f->destination Status affected: Z Description: The contents of the f register are complemented.If d is 0 the result is stored in W register else in F register. DECF Decrement f Syntax [label] DECF f,d Operands: 0<=f<=127 ; d[0,1] Operation: f 1 ->destination Status affected: Z Description: The contents of the f register are decremented.If d is 0 the result is stored in W register else in F register.
INSTRUCTIONS
DECFSZ Decrement f,skip if 0 Syntax [label] DECFSZ f,d Operands: 0<=f<=127 ; d[0,1] Operation: f 1 ->destination;skip if result=0 Status affected: none Description: The contents of the f register are decremented.If d is 0 the result is stored in W register else in F register.If the result is 1 the next instruction is executed,if 0 and a NOP is executed instead making this a 2TCY instruction. GOTO Unconditional branch Syntax: [label] GOTO k operands 0<=k<=2047 Operation: k->PC<10:0>;(PCLATH<4:3>)>PC<12:11> Status affected none Description: The eleven bit immediate value is loaded into PC bits<10:0>The upper bits of PC are loaded from PCLATH <4:3>.GOTO is a two cycle instruction.
INSTRUCTIONS
INCF increment f, Syntax [label] INCF f,d Operands: 0<=f<=127 ; d[0,1] Operation: f 1 ->destination Status affected: Z Description: The contents of the f register are incremented.If d is 0 the result is stored in W register else in F register. INCFSZ Increment f,skip if 0 Syntax [label] INCFSZ f,d Operands: 0<=f<=127 ; d[0,1] Operation: f 1 ->destination;skip if result=0 Status affected: none Description: The contents of the f register are incremented.If d is 0 the result is stored in W register else in F register.If the result is 1 the next instruction is executed,if 0 and a NOP is executed instead making this a 2TCY instruction.
INSTRUCTIONS
IORLW Inclusive OR literal with W Syntax [label] IORLW K Operands: 0<=k<=255 Operation: (w) OR k->(w) Status affected: Z Description: The contents of the W register are ORed to the eight bit literal k and the result is placed in the w register. IORWF Inclusive OR W with F Syntax [label] IORWF f,d Operands: 0<=f<=127 ; d[0,1] Operation: w OR f->destination Status affected: Z Description: The contents of the W register are ORed to register f.If d is 0 the result is stored in W register else in F register
INSTRUCTIONS
MOVF move f Syntax [label] MOVF f,d Operands: 0<=f<=127 ; d[0,1] Operation: f->destination Status affected: Z Description: The contents of the f register are moved to destination dependent upon the status of d. If d is 0 the result is stored in W register else in F register.
MOVLW move literal and W Syntax [label] MOVLW K Operands: 0<=k<=255 Operation: k->(w) Status affected: C,DC,Z Description: the eight bit literal k is loaded into W register .Dont cares are treated as zero.
INSTRUCTIONS
MOVWF move W to F Syntax [label] MOVWF f Operands: 0<=f<=127 Operation: (w)->f Status affected: none Description: move data from W register to register f. NOP NO operation Syntax [label] NOP Operands: none Operation: none Status affected: none Description: NO operation
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INSTRUCTIONS
RETFIE Return from interrupt Syntax [label] RETFIE Operands: none Operation: TOS->PC,1->GIE Status affected: none RETLW Return with literal in W Syntax [label] RETLW k Operands: 0<=k<=255 Operation: k->W; TOS->PC Status affected: None Description: The W register is loaded with the eight bit literal k.The program counter is loaded from the top of the stack(the return address ) this is two cycle instruction.
INSTRUCTIONS
RETURN Return from subroutine Syntax [label] RETURN Operands: None Operation: TOS->PC Status affected: None Description: Return from subroutine.the stack is POPed and the top of the stack (TOS) is loaded into the program counter.this is two cycle instruction. RLF Rotate left through carry Syntax [label] RLF f,d Operands: 0<=f<=127 ;d[0,1] Status affected: C Description: the contents of register f are rotated one bit to the left through the carry Flag.If d is 0 the result is placed in W register or in f register
INSTRUCTIONS
RRF Rotate right through carry Syntax [label] RRF f,d Operands: 0<=f<=127 ;d[0,1] Status affected: C Description: The contents of register f are rotated one bit to the right through the carry Flag.If d is 0 the result is placed in W register or in f Register. SLEEP Return from subroutine Syntax [label] SLEEP Operands: None Operation: 00h->WDT;0->WDT prescaler;1->TO;0->PD; Status affected: TO,PD Description: The power down status bit,PD is cleared.Time out status bit TO Is set.WDT and its prescaler are cleared.The processor is put into SLEEP mode with the oscillator stopped.
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INSTRUCTIONS
SUBLW subtract literal and W Syntax [label] SUBLW K Operands: 0<=k<=255 Operation: k-w->(w) Status affected: C,DC,Z Description: The contents of the W register are subtracted to the eight bit literal k and the result is placed in the w register. SUBWF Subtract W and F Syntax [label]SUBWF f,d Operands: 0<=f<=127 ; d[0,1] Operation: f-W->destination Status affected: C,DC,Z Description: The contents of the W register are subtracted to register f.If d is 0 the result is stored in W register else in F register.
INSTRUCTIONS
XORLW Exclusive OR literal with W Syntax [label] XORLW K Operands: 0<=k<=255 Operation: (w) XOR k->(w) Status affected: Z Description: The contents of the W register are XORed to the eight bit literal k and the result is placed in the w register. XORWF Exclusive OR W with F Syntax [label] XORWF f,d Operands: 0<=f<=127 ; d[0,1] Operation: w XOR f->destination Status affected: Z Description: The contents of the W register are XORed to register f.If d is 0 the result is stored in W register else in F register.
INSTRUCTIONS
SWAPF Swap Nibbles in f Syntax [label] SWAPF f,d Operands: 0<=k<=127; d[0,1] Operation: (f<3:0>->(destination<7:4>);(f<7:4>)->(destination<3:0>) Status affected: none Description: The upper and lower nibbles of register f are exchanged. If d is 0 the result is stored in W register else in F register.
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PIC1

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Single cycle instruction

Register file architecture

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INSTRUCTION FLOW/ PIPELINING

INSTRUCTION FLOW/ PIPELINING

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CENTRAL PROCESSING UNIT

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Register select bank bit( indirect addressing)

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memory parity error circuitry status bit

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GENERAL PURPOSE REGISTER-GPR

SPECIAL FUNCTION REGISTER-SFR

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Direct and Indirect Addressing

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PORTA and TRISA register

PORTA and TRISA register

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PORTB and TRISB register

PORTB and TRISB register

PORTB and TRISB register

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PORTC and TRISC register

TRIS bits for each PORTC pins as some peripherals

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PORTF and PORTG

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GPIO and TRISGP register

GPIO and TRISGP register

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Successive operation on an I/O port

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Successive operation on an I/O port

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INTE(2) RBIE(1,2) TOIF

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CCP1IF TMR2IF TMR1IF

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