Topics
MOS Structure MOS IV Characteristics Second Order Effects MOS Device Models
NMOS Structure
Substrate contact--to reverse bias the pn junction Connect to most negative supply voltage in most circuits.
Source: the terminal that provides charge carriers. (electrons in NMOS) Drain: the terminal that collects charge carriers.
CMOS Structure
Connect to most positive supply voltage in most circuits. Reverse bias the pn junction Reverse bias the pn junction
NMOS
PMOS
Symbols
This textbook
In Digital Circuits
MOS IV Characteristics
Threshold Voltage Derivation of I/V Characteristics
I-V curve Transconductance Resistance in the linear region
Threshold Voltage
1. Holes are expelled from the gate area 2. Depletion region (negative ions) is created underneath the gate. 3. No current flows because no charge carriers are available.
Threshold (2)
Two capacitors in series: Cox: capacitance between the gate and oxide/silicon interface Cdep: capacitance of the depletion region As VG increases, the potential at the oxide/silicon increases.
Body Effect
The n-type inversion layer connects the source to the drain. The source terminal is connected to channel. Therefore, A nonzero VSB introduces charges to the Cdep. The math is shown in the next slide. A nonzero VSB for NFET or VBS for PFET has the net effect Of increasing the |VTH|
W/L=12 um/0.12um CMOS: 0.13 um process VDS=50 mV Simulator: 433 mV Alternative method: 376 mV
Subthreshold current
Subtreshold region As VG increases, the surface potential will increase. There is very little majority carriers underneath the gate. There are two pn junctions. (B-S and B-D) The density of the minority carrier depends on the difference in the voltage across the two pn junction diode. A diffusion current will result the electron densities
Threshold Voltage
VG=0.6 V VD=1.2 V CMOS: 0.13 um W/L=12um/0.12 um NFET
Threshold voltage can be adjusted by implanting Dopants into the channel area during fabrication. E.g. Implant p+ material to increase threshold voltage.
The VGS must be sufficient negative to produce an inversion layer underneath the gate.
I-V Characteristics
Channel Charge
A channel is formed when VG is increased to the point that the voltage difference between the gate and the channel exceeds VTH.
The conductive channel between S and D can be viewed as resistor, which is voltage dependent.
Application of VDS
Pinch Off
Linear Region
Small VDS
Saturation Region
Large VDS Electrons reaches the D via the electric field in the depletion region
No channel
PMOS
1. Take derivative of ID with respect to VDS 2. For small VDS, the drain resistance is
Example
Ron=233.625 Ohms VS=100/(100+233.625) *100 mV=29.97 mV
Transconductance
IDS vs VGS
0.13 um NMOS VDS=0.6 V W/L=12um/0.12 um VB=VS=0 Y axis: ids X axis: Vgs
(Triode region)
gm as function of region
0.13 um NMOS VGS=0.6 V W/L=12um/0.12 um VB=VS=0 Y axis: gm X axis: vds saturation linear
As VDS increases, L1 will move towards the source, since a larger VDS will increase VX .
L is really L1
ID will increase as VDS increases. The modulation of L due to VDS is called channel length modulation.
For a longer channel length, the relative change in L and Hence ID for a given change in VDS is smaller. Therefore, to minimize channel length modulation, minimum length transistors should be avoided.
gds
0.13 um NMOS VGS=0.6 V W/L=12um/0.12 um VB=VS=0 Y axis: gm X axis: vds saturation linear
constant
(chain rule)
MOS Capacitances