FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression

H.SRI HARSHA 09PR1A0472, IV-B.Tech, E.C.E.

M.ROHIT XAVIER 09PR1A0448, IV-B.Tech, E.C.E.

 Digital imaging has an enormous effect on scientific and industrial applications.

Uncompressed image require considerable storage capacity and bandwidth.

The solution to this problem is to compress image. the

The process of making the image to be stored in less memory is called Image Compression.

 Due to this , image retrieving /downloading time will be greatly reduced .

Websites without compression lakes more time to load than with compression.
Hence compression is done now a days. This is not only confined to images but also for music as well as for videos.

Block Diagram and working :

The steps involved in image compression are : 1) Color Space conversion 2) Down Sampling 3) 2D-DCT 4) Quantization 5) Entropy coding

 For Gray scale image , only last three stages are used. First the image is divided into blocks of 8x8

 Now 2-D DCT is applied for each block. The result is a matrix of size 8x8.

 Then this is rounded off to nearest values. This is called as quantization. After coding we get another matrix. This is given to FPGA as input .

This can be fed in serial or pipelined. But in this, pipelined process is used.
The image can be retrieved by applying inverse DCT i.e., I-DCT.

Applications : 1) In webservers to store the images. 2) In computers. 3) In digital photo frames.

Advantages :
1) Occupies less memory 2) Faster data retrieval

3) Increased efficiency. 4) Less immune to noise.