8086

Intel 8086 Microprocessors

8086 consists of two internal units
The execution unit (EU) - executes the instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results

The 8086 has a 6B prefetch queue

The 8088 has a 4B prefetch queue

8086 Internal Organisation

EU BIU Address Bus 20 bits AH BH CH DH SP SS BP ES DI IP BI Internal Communications Registers Bus Control AL BL CL CS DL DS SUMMATION Data Bus

8086

8086 Bus

Temporary Registers Instruction Queue ALU

EU Control

Flags

8086

8086 20-bit Addresses

CS 16-bit Segnment Base Address 0000

IP 16-bit Offset Address

20-bit Physical Address

8086

8086 Addressing Modes

Implied Addressing Modes Register and Immediate Addressing Modes

Memory Modes
I/O Addressing Modes Relative Addressing Modes

8086

Addressing modes
Implied - the data value/data address is associated with the instruction. Ex: HLT, CLC implicitly

Register - references the data in a register or in a register pair. Ex: MOV AX, CX Immediate - the data is provided in the instruction. Ex: MOV AL, 08H Direct - the instruction operand specifies the memory address where data is located. Ex: MOV CL, SS:12

Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Ex: MOV BX, SS[BP]

8086

Addressing modes
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.

8086

Addressing modes
I/O Addressing Mode Used for I/O operations. 65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports. Ex: OUT PORT_ADD, AL or OUT AL, PORT_ADD Relative Addressing Mode Jumps and CALL instructions. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Ex: JMP level_name

8086

Instructions (list)
ADD AND CALL CBW CLC CLD CMP CWD DEC DIV HLT IN INC INT IRET JMP NEG NOP NOT OR OUT POP POPF PUSH PUSHF LEA LOOP MOV MUL RCL RCR RET ROL ROR SAHF SHL SHR STC STD STI SUB TEST XCHG XOR

8086

Instructions
ADD REG, memory memory, REG REG, REG memory, immediate REG, immediate Add. C Z S O P A Algorithm: operand1 = operand1 + operand2 Example: MOV AL, 5 ; AL = 5 ADD AL, -3 ; AL = 2 RET AND REG, memory memory, REG REG, REG memory, immediate REG, immediate Logical AND between all bits of two operands. Result is stored in operand1. These rules apply: 1 1 0 0 AND AND AND AND 1 0 1 0 = = = = 1 0 0 0 C Z S O P A 0 r r 0 r X r r r r r r

Example: MOV AL, 'a' ; AL = 01100001b AND AL, 11011111b ; AL = 01000001b ('A') RET

8086

Instructions
CMP REG, memory memory, REG REG, REG memory, immediate REG, immediate operand1 - operand2 result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to result. C Z S O P A Example: r r r r r r MOV AL, 5 MOV BL, 5 CMP AL, BL ; AL = 5, ZF = 1 (so equal!) RET when operand is a byte: AL = AX / operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus) Example: MOV AX, 203 ; AX = 00CBh MOV BL, 4 DIV BL ; AL = 50 (32h), AH = 3 RET

DIV

REG memory

8086

Instructions
ADD REG, memory memory, REG REG, REG memory, immediate REG, immediate Add. C Z S O P A Algorithm: operand1 = operand1 + operand2 Example: MOV AL, 5 ; AL = 5 ADD AL, -3 ; AL = 2 RET AND REG, memory memory, REG REG, REG memory, immediate REG, immediate Logical AND between all bits of two operands. Result is stored in operand1. These rules apply: 1 1 0 0 AND AND AND AND 1 0 1 0 = = = = 1 0 0 0 C Z S O P A 0 r r 0 r X r r r r r r

Example: MOV AL, 'a' ; AL = 01100001b AND AL, 11011111b ; AL = 01000001b ('A') RET

8086

Instructions
INT immediate byte Interrupt numbered by immediate byte (0..255). Algorithm: Push to stack:
flags register CS IP

C Z S O P A I

Unchanged

IF = 0 Transfer control to interrupt procedure Example: MOV AH, 0Eh ; teletype. MOV AL, 'A' INT 10h ; BIOS interrupt. RET NEG REG memory Algorithm: Invert all bits of the operand Add 1 to inverted operand Example: MOV AL, 5 ; AL = 05h NEG AL ; AL = 0FBh (-5) NEG AL ; AL = 05h (5) RET C Z S O P A r r r r r r

8086

Instructions
MOV REG, memory memory, REG REG, REG memory, immediate REG, immediate SREG, memory memory, SREG REG, SREG SREG, REG The MOV instruction cannot: set the value of the CS and IP registers. copy value of one segment register to another segment register (should copy to general register first). copy immediate value to segment register (should copy to general register first). Algorithm: operand1 = operand2 Example: C Z S O P A Unchanged

ORG 100h MOV AX, 0B800h ; set AX = B800h (VGA memory). MOV DS, AX ; copy value of AX to DS. MOV CL, 'A' ; CL = 41h (ASCII code). MOV CH, 01011111b ; CL = color attribute. MOV BX, 15Eh ; BX = position on screen. MOV [BX], CX ; w.[0B800h:015Eh] = CX. RET ; returns to operating system.

8086

Instructions
MUL REG memory Algorithm: C Z S O P A when operand is a byte: AX = AL * operand. when operand is a word: (DX AX) = AX * operand. r ? ? r ? ?

Example: MOV AL, 200 ; AL = 0C8h MOV BL, 4 MUL BL ; AX = 0320h (800) RET CF=OF=0 when high section of the result is zero. POP REG SREG memory Algorithm: operand = SS:[SP] (top of the stack) SP = SP + 2 Example: MOV AX, 1234h PUSH AX POP DX ; DX = 1234h RET

8086

Instructions
PUSH REG SREG memory immediate Algorithm: SP = SP - 2 SS:[SP] (top of the stack) = operand Example: MOV AX, 1234h PUSH AX POP DX ; DX = 1234h RET RCL memory, immediate REG, immediate memory, CL REG, CL Algorithm: shift all bits left, the bit that goes off is set to CF and previous value of CF is inserted to the right-most position. Example: STC ; set carry (CF=1). MOV AL, 1Ch ; AL = 00011100b RCL AL, 1 ; AL = 00111001b, CF=0. RET OF=0 if first operand keeps original sign. C O r r

8086

Instructions
RCR memory, immediate REG, immediate Algorithm: shift all bits right, the bit that goes off is set to CF and previous value of CF is inserted to the Left-most position. Example: STC ; set carry (CF=1). MOV AL, 1Ch ; AL = 00011100b RCR AL, 1 ; AL = 10001110b, CF=0. RET OF=0 if first operand keeps original sign. ROL memory, immediate REG, immediate memory, CL REG, CL Algorithm: shift all bits left, the bit that goes off is set to CF and the same bit is inserted to the right-most position. Example: MOV AL, 1Ch ; AL = 00011100b ROL AL, 1 ; AL = 00111000b, CF=0. RET OF=0 if first operand keeps original sign. C O r r

memory, CL REG, CL

C O
r r

8086

Instructions
ROR memory, immediate REG, immediate Algorithm: shift all bits right, the bit that goes off is set to CF and the same bit is inserted to the left-most position. Example: MOV AL, 1Ch ROR AL, 1

memory, CL REG, CL

; AL = 00011100b ; AL = 00001110b, CF=0.

C O
r r

OF=0 if first operand keeps original sign. SAL memory, immediate REG, immediate memory, CL REG, CL Algorithm: Shift all bits left, the bit that goes off is set to CF. Zero bit is inserted to the right-most position. Example: MOV AL, 0E0h ; AL = 11100000b SAL AL, 1 ; AL = 11000000b, CF=1. RET OF=0 if first operand keeps original sign.

C O r r

8086

Instructions
SAR memory, immediate REG, immediate Algorithm: Shift all bits right, the bit that goes off is set to CF. The sign bit that is inserted to the left-most position has the same value as before shift. Example:

memory, CL REG, CL

C O
MOV AL, 0E0h SAR AL, 1 MOV BL, 4Ch SAR BL, 1 ; AL = 11100000b ; AL = 11110000b, CF=0. ; BL = 01001100b ; BL = 00100110b, CF=0. r r

OF=0 if first operand keeps original sign. SHL memory, immediate REG, immediate Algorithm: Shift all bits left, the bit that goes off is set to CF. Zero bit is inserted to the right-most position. Example: MOV AL, 11100000b SHL AL, 1 ; AL = 11000000b, CF=1. OF=0 if first operand keeps original sign. C O r r

memory, CL REG, CL

8086

Instructions
SHR memory, immediate REG, immediate Algorithm: Shift all bits right, the bit that goes off is set to CF. Zero bit is inserted to the left-most position. Example: MOV AL, 00000111b SHR AL, 1 ; AL = 00000011b, CF=1. OF=0 if first operand keeps original sign. WAIT 8086 enters the IDLE state Causes the CPU to enter wait state if the 8086 TEST pin is high While in wait state, the 8086 continues to check TEST pin for low C O If the TEST goes low, 8086 executes the next r r instruction This feature can be used to synchronize the operation of 8086 to an event in external hardware.

memory, CL REG, CL

C O
r r

8086

8086 Microprocessor
8086 microprocessors need support circuits in a microcomputer system
8086 multiplex the address and data buses on the same pins This saves pins but at a price:
Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs

8086

8086 Microprocessor
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40

MINIMUM MODE

Vcc AD15 A16,S3 A17,S4 A18,S5 A19,S6 /BHE,S7 MN,/MX /RD

Minimum Mode:
8086 is configured to support small, single processor systems using a few devices that use the system bus

Maximum Mode:
HOLD HLDA /WR IO/M DT/R /DEN ALE /INTA

8086

/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET

8086 is configured to support multi-processor systems. 8086 needs at least the following:
8288 Bus Controller, 8284A Clock Generator, 74HC373s and 74HC245s

8086 Maximum Mode

Vcc
S0# S1# S2# CLK MRDC# MWTC# AMWC# IORC# IOWC# AIOWC# INTA#

8284A Clock Generator RDY

CLK READY RESET

8288 Bus Controller

DEN DT/R# ALE

8086 CPU
MN/MX#

LE OE# BHE # AD15:AD0 A19:A16 INTR 74LS373 x3

A19:A0, BHE#

ADDR/DATA

DIR EN# 74LS245 74LS245 x2 x2

D15:D0

ADDR/Data

8086

8086 Maximum Mode

In maximum mode, the 8288 uses a set of status signals (S0, S1, S2) to rebuild the normal bus control signals of the microprocessor
MRDC#, MWTC#, IORC#, IOWC# etc Equivalent to MEMR# etc

Look at some special signals briefly

8086

RESET# Signal
The Active low RESET# signal puts the 8086 into a defined state Clears the flags register, segment registers etc. Sets the effective program address to 0FFFF0h (CS=0F000h, IP=0FFF0h) 8086 Programs always start at 0FFFF0H after Reset has been asserted and removed

Continues into latest generation CPUs

8086

BHE# Signal
The 8086 processor can address memory a byte at a time Its data bus is 16 bits wide It uses the BHE# signal and A0 (sometimes called BLE#) to address bytes using its 16b bus

8086

Use of BHE#/A0(BLE#)
Byte-Wide addressing (8088) FFFFF FFFFE FFFFD FFFFC A19..A1 ODD Addresses (8086) FFFFF FFFFD FFFFB FFFF9 A19..A1 EVEN Addresses (8086) FFFFE FFFFC FFFFA FFFF8

00002 00001 00000

00005 00003 00001

00004 00002 00000

D15:D8 BHE# A0/BLE#

D7:D0

8086

Use of BHE#/BLE#
BHE# 0 0 1 A0/BLE# 0 1 0 Selection Whole word (16-bits) High byte to/from odd address Low byte to/from even address

No selection

8086

ALE and Address/data Bus Multiplexing

8086/8 Multiplexes the Address and Data signals onto the same set of pins Need off-chip logic to separate the signals Transparent latches designed just for address demultiplexing

8086

ALE and 74HC373 Transparent Latch

Clock

Address/ Data Bus

Address Time

Data Time

ALE

Output of 74HC373

Microcomputer AddressBus

74HC373 or equivalent

Address/ Data Bus

In0:In7

Q0:Q7

System Address Bus

ALE

LE OE# TriState Control signal, OE#, shown connected to GND for simplicity

8086

Use of ALE

(Address Latch Enable)

ALE is used with an external latch (74HC373) to demultiplex the address and data lines

74HC373 is transparent when its LE input (connected to ALE) is high

When ALE goes low, the 373 holds the last data until ALE goes high again

8086

8288 Bus Controller and Bus Transceivers

8288 Bus Controller DEN# DT/R# EN# DIR DIR CPU [D15:D8] 74HC245 Buffered [D15:D8] 8288 Bus Controller also generates Direction and Enable signals for BiDirectional Transeivers Supports Buffering the System Data Bus

EN# DIR CPU [D7:D0] 74HC245 Buffered [D7:D0]

To Memory and I/O Systems

8086

8086 Read Cycle

T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6 001 or 101

T2

T3

T4

Address

Status

ALE AD0..AD15 A0..A19 DT/R DEN /MRDC or /IORC

Address float Valid Data float

Valid Address

8086

8086 Write Cycle

T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6 010 or 110

T2

T3

T4

Address

Status

ALE AD0..AD15 A0..A19 DT/R DEN /MWTC or /IOWC

Address Valid Data

Valid Address

8086

8086 Read Cycle

T1 CLK /S0, /S1, /S2 A16..A19, /BHE
S3..S6

(1 Wait State)
T2 T3 Tw T4

001 or 101

Address

Status

ALE 8284 RDY READY AD0..AD15 A0..A19 DT/R DEN /MRDC or /IORC
Address float Valid Data float

Valid Address

8086

Summary
First Generation (introduced June 1978) One of the first 16b processors on the market 16b internal registers 16/8b external data bus 20b address bus (1MB addressable) Used in 1st generation IBM PCs (1981)