ADPLL: All Digital PhaseLocked Loop Circuits

EE295 Spring 2008

G. Carpenter A. Vize

Outline
What is an ADPLL? ADPLL Advantages and Issues System Level Comparison: ADPLL vs. Analog PLL A Past Design Approach Example (<2005) A Current Design Approach Example (2006) Our Project Specifics: (Frequency, Size, etc.) Anticipated Issues Conclusion

What is ADPLL?
The All Digital Phase-Locked Loop circuit or ADPLL consists of an interacting series of entirely digital cell components which utilize digital logic structure, rather than analog voltage and current level driven devices, in order to lock to a desired frequency, given a reference frequency, within a desired frequency range in order to match the frequency and phase of a received signal.[1] (System specifications and diagrams to follow.)

ADPLL Advantages
Analog PLL -The Phase Detector produces charge up or charge down current pulses which have durations proportional to the difference in phase between the reference signal and the feedback signal. [7] ADPLL - The Phase Detector produces a digital word proportional to the difference in time between an edge of reference signal and the feedback signal. These digital words are then sent to the digital loop filter.[7]

Advantage Since the loop filter parameters are numerical, they can be changed easily by programming registers rather than changing components and there is virtually no limit on parameter size. [7] Phase Detector does not suffer from charge pump mismatch or leakage, thermal noise, aging or drift. [7]

ADPLL Advantages
All-Digital PLL design can improve system-turnaround efficiency during process changes, making it good for system on a chip applications [9] Excels at frequency translation [7] Decreased on chip area. The move to all digital eliminates the need for the isolation rings and eliminates bulky loop filter components. ~ 50% savings in chip area [9] Decreased Power Consumption Elimination of charge pump, current generators, voltage to current converters, etc. ~ 45% savings in power [9]

ADPLL Design Issues

4 GHz ADPLL performance vs. 8 GHz analog PLL speeds achieved. [5,7] The discrete nature of the phase correction can cause reference spurs. [7] It is difficult to obtain high frequency resolution while achieving wide closed loop bandwidth.

System Level PLL and ADPLL

Traditional, (Analog), PLL Architecture:[3]

Analog Blocks

System Level PLL and ADPLL

The analog blocks utilized by the traditional PLL architecture are more susceptible to Process, Voltage, and Temperature, (or PVT), variations, as these can most strongly influence factors such as threshold voltage, filter capacitance, and the operating characteristics of the Voltage Controlled Oscillator (VCO). [1]

System Level PLL and ADPLL

One example of an ADPLL Architecture:[1]

All Digital Component Blocks

More on the specifics of this system diagram later

System Level PLL and ADPLL

Two key components to the ADPLL are the Digitally Controlled Oscillator, DCO, and the Phase/Frequency Detector, or PFD, or a PD or Phase detector.[1][4] Where the PFD/PD in the analog case could be implemented either as a digital component or an analog component.

System Level PLL and ADPLL

Many of the ADPLL architectures examined also utilize a Time to Digital Converter, (TDC or T2D). This component converts difference information from the PFD/PD stage to a multi-bit control word which is used to incrementally adjust the DCO, this allows for digital control of the output frequency. [1][4] This being a major departure from the traditional PLL architecture which usually employs a VCO or voltage controlled oscillator, which is controlled by an analog voltage level.

A Past ADPLL Design Example

From: An All-Digital Phase-Locked Loop for High-Speed Clock Generation [2]

-Note the two DCOs -The Inner DCO Tracks the Reference Clock -The Output DCO Generates the Output Clock

A Past ADPLL Design Example

Fine Tune Delay Circuit Fine Tuning Resolution 5 ps [2]

Digitally Controlled Oscillator Coarse Tuning Resolution 300 ps [2]

A Past ADPLL Design Example

Phase Frequency Detector No signal sent to controller when the phase error is less than 50 ps Post Digital Pulse Amp [2]

A Past ADPLL Design Example

Digital Pulse Amplifier Increases the Phase Error between Reference and Feed Back Clocks so the D-flip-flops Can Detect It. [2]

A Recent Design Approach Example

From: A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS[5]

A Recent Design Approach Example

The PFD component allows for the initial frequency and phase comparison. This papers design, [5], utilizes what is referred to as a conventional tri-state PFD; variants of this PFD architecture appear in many of the IEEE papers related to ADPLL design.

A Recent Design Approach Example

Digital PFD schematic[5]

A Recent Design Approach Example

The next stage, the Frequency Decision Circuit, is used to output frequency up or down signals to the subsequent stage, the DCO.

A Recent Design Approach Example

Using the DEC_Clk to determine the decision period, and reset each latch at the beginning of each decision period, such that the outputs of each latch are 1 at the beginning of each updating period, if there are no Up signals from the previous stage during the updating period and only Down signals the output of the FreqDN is high when the next rising edge of the DEC_Clk arrives.[5] A similar method is used to establish the PhaseUP/DN signal, both of which are used to control the subsequent DCO stage.

A Recent Design Approach Example

One of the most important elements to an ADPLL circuit is the digitally controlled oscillator, or DCO stage; in general this stage allows for the use of a control bit word to adjust the output frequency. In the cases examined this is achieved with some form of varactor array architecture as the variable in an LC tank circuit; this specific case utilizing a controlled shift register in conjunction with the varactor array to control the output frequency.[5]

A Recent Design Approach Example

LC TANK Circuit

A Recent Design Approach Example

Achieving the desired frequency is only a part of the necessary operation however, as the phase is an equally important component of the devices operation. In order to achieve the desired control of phase at the DCO output the following phase tuning circuitry, similar to that utilized for the frequency varactor array, has been employed.[5]

A Recent Design Approach Example

This varactor based phase circuit, like that of the frequency circuit allows for the phase tuning of the output signal.[5]

Our Project
The project specifications for our project are to include: .18 Technology 1GHz Operational Frequency Transistor Level Implementation Physical Layout

Our Project
Based on the fact that we have found publications in which frequencies greater than our goal frequency have been reliably achieved, [5][4], on smaller technology, it seems possible to achieve the goals before us while potentially making gains in power efficiency, stability, or layout efficiency; however issues of control stability, parasitic effects, and other unforeseen issues may arise for which we must try to prepare.

References:
1. 2. An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications, Duo Sheng; Ching-Che Chung; Chen-Yi Lee; VLSI Design, Automation and Test, 2006 International Symposium on, April 2006, Page(s):1 - 4 An All-Digital Phase-Locked Loop for High-Speed Clock Generation, Ching-Che Chung; Chen-Yi Lee; Solid-State Circuits, IEEE Journal of Volume 38, Issue 2, Feb. 2003 Page(s):347 - 351 http://www.sugawara-systems.com/opencores/pll/pll.htm A Contribution to the Discrete Z-Domain Analysis of ADPLL, Xin Chen, Jun Yang; Xiao-ying Deng; ASIC, 2007. ASICON '07. 7th International Conference on, 22-25 Oct. 2007, Page(s):185-188 "A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS", Zhuang, Jingcheng; Du, Qingjin; Kwasniewski, Tad; Custom Integrated Circuits Conference, 2007. CICC '07. IEEE 16-19 Sept. 2007 Page(s):543 - 546 "An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications", Circuits and Systems II: Express Briefs, IEEE Transactions on,Volume: 54, Issue: 11,page(s): 954-958 Analogue or Digital in PLL Design, Paul Kern, Electronics Weekly ,2007-11-08, http://www.electronicsweekly.com/Articles/2007/11/08/42575/analogue-or-digital-in-plldesign.htm Introduction of an All Digital Phase Locked Loop, Terng-Yin Hsu, Dept of CSIE, NCTU, http://isip17.csie.nctu.edu.tw/slides/NetworkSOC/Clock%20Recover_11222004.pdf A Compact, Low-Power Low-Jitter Digital PLL, Amr M. Fahim, Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European, Publication Date: 16-18 Sept. 2003

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