IC LAYOUT ENGINEERING

Introduction to Microelectronics
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Evolution Of Microelectronics
1947: Three scientists at Bell Telephone Laboratories, William Shockley, Walter Brattain, and John Bardeen demonstrate the first transistor: 1955: Frosch and Derick at Bell Labs patent the diffusion furnace and develop SiO2 passivation layers for silicon transistors 1955: Andrus and Bond at Bell Labs pattern oxide layers with photolithography 1957: Lantrop and Nall (US Army) Pattern 200um leads to connect discrete transistors 1958: Last and Noyce develop the first step and repeat cameras for lithographic processing at Fairchild
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1957/1958: Jean Hoerni at Fairchild conceptualizes the first planer fabrication process for pn junctions using oxide barriers to protect pn junctions underneath. Allowed all of the circuitry required for transistor fabrication to be patterned on 1 side of the wafer. 1959: Fairchilds Robert Noyce patents the monolithic IC that ties transistors, capacitors, resistors together using micro lithographically patterned aluminum leads deposited on top of Heornis protective coating. 1960:Fairchild sells planer npn transistor device utilizing SiO2 barrier oxide for passivation that was patterned using a lithographic fabrication process

1960: Fairchild demonstrates the first IC with 4 transistors and 5 resistors

1961 GCA Corporation commercializes the step and repeat reduction device for optical lithography TTM Institute of Technology

Evolution Of Microelectronics (cont.)

1960: First MOS transistor 1960: Ian Ross of Bell Labs uses CVD to between the substrate and the collector to raise breakdown voltage and significantly increase the speed of the circuit 1961: Hoerni demonstrates Silicon transistor that exceeds Ge switching speeds: Computers take off!! 1963: San and Wanlass of Fairchild showed that pand nchannel MOS transistors arranged into a complementary circuit (CMOS) drew close to zero power in standby mode 1964: Standard logic IC families introduced 1964: General Microelectronics releases the first commercial MOS IC
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MOS FET Structure

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Evolution Of Microelectronics (cont.)

1965: Fairchilds Director Gordon Moore introduces Moores law which accurately predicts the exponential increase of transistor density in an IC and provides a guide for technological progression that is still in use today NSF is now preparing for the demise of Moores law reached the limits of optical lithography Single bit logic is fading to quantum computing and the qbit

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Moores Law
1965: Fairchilds Director Gordon Moore introduces Moores law which accurately predicts the exponential increase of transistor density in an IC and provides a guide for technological progression that is still in use today NSF is now preparing for the demise of Moores law reached the limits of optical lithography Single bit logic is fading to quantum computing and the qbit

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Evolution Of Microelectronics (cont.)

1964: Multichip SLT packaging technology introduced by IBM 1965: Fairchild Engineers develop Dual InLine (DIP) chip packaging 1966: Semiconductor bipolar RAM 1966/1967: Computer aided design leads to Application Specific IC (ASIC) 1967: Turnkey equipment supplies such as Applied Materials introduce commercial tooling 1969: Intel enters the scene with commercial tooling, silicon gate technology, and embedded metallic leads

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1966 : First 256K Bipolar Ram

1971 : Intels 1stMicroprocessor: i4004

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Design Of Performance Parameters

Physical : Area , Size , Weight
Power : Dissipation/Consumption Speed : Timing

Noise : Cross talk

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THE GOAL OF ASIC DESIGNER

Meet the market requirement Satisfying the customer need Beating the competition Increasing the functionality Reducing the cost Achieved by Using the next generation Silicon Technologies New Design concept and Tools High Level Integration
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THE PERFORMANCE CUBE

Delay

Power Cost

Smaller is Better
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VLSI TECHNOLOGY
Backbone for all IT advancements. A Technology solution and not a product. Packages lot of circuitry ( Millions of Gates] Miniaturisation Confidentiality Low power operation Hand held battery operated gadgets

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APPLICATIONS
High Performance computing Datacom/ Networking Telecom/MOBILE/CELL/ WIL Multimedia

Smart Cards
Remote Controls TTM Institute of Technology
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ADVANTAGES OF VLSI
REDUCTION IN Design cycle time Product Size Power Consumption Cost INCREASE IN Speed Design Security Productivity Design Flexibility
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MOORES LAW
Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com

In 1969, Gorden Moore stated that Silicon Technology will double the number of transistors per chip every 18 months!!!

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MOORES LAW
Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com

In 1969, Gorden Moore stated that Silicon Technology will double the number of transistors per chip every 18 months!!! And it is happening ! ! ! ! ! ! !!!!!!!!

Now Moores law has become self sustaning

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INTEGRATION LEVEL
Year Types gates per chip ~10 60s - SSI : small-scale integration

70s MSI: medium-scale integration ~1001K 80s- LSI: large-scale integration ~1K 10K

90s- VLSI: very large-scale integration ~10K100K

ULSI: ultra large scale integration TTM Institute of Technology ~1M10M
upwards

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Technology Definition

SSI
MSI LSI VLSI

2 - 20 GATES

: 20 - 200 GATES : 200 - 2000,000 GATES : OVER 1 MILLION GATES

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Gate & Interconnect Delays with shrinking

40 35 Gate delay Interconnect delay

30 25 20 15 10 5 0 0.65 1989

0.5 1992

0.35 1995

0.25 1998

0.18 2001

0.13 2004

0.1 2007
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Source: SIA Roadmap 1997

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Technology Directions
Year Feature size (nm) 1999 180 2002 130 2005 100 2008 70 2011 2014 50 35

Mtrans/cm2
Chip size (mm2) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power(W)

7
170 768 600 6-7 1.8 90 1.4

14-26
170-214 1024 800 7-8 1.5 130 2.0

47
235 1024 1100 8-9 1.2 160 2.4

115
269 1280 1400 9 0.9 170 2.0

284
308

701
354

1408 1472 1800 2200 9-10 0.6 174 2.2 10 0.6 183 2.4

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Over View Of VLSI DESIGN METHODOLOGY

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VLSI - OVERVIEW
Customer Specification

VLSI TECHNOLOGY
Full Custom ASIC

FPGA ASIC

Semi -Custom ASIC

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Gate Array ASIC

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Silicon Manufacturing Alternatives

Application Specific ICs

Standard Components

Fixed Application

Application Semi by ProgrammingCustom

Full Custom

Silicon Compilation

Logic Families

Hardware Programming (MASK)

Software Programming

TTL CMOS

PLA ROM

Microprocessor EPROM,EEPROM PLD

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Design Styles

Complexity of VLSI circuits Performance Size Cost Market time

Different design styles

Full custom

Standard Cell

Gate Array

FPGA

Cost ,Flexibility,Performance

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VLSI - OVERVIEW(cont)
Customer Specification

Gate Level Net List

Logic Design/ Front End

FPGA ASIC
Full Custom

ASIC

Semi -Custom ASIC

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Gate Array ASIC

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LOGIC DESIGN
Blocking assignment
always @(A1 or B1 or C1 or M1)
// blocking assignments

begin: BLOCK_COMB M1 = #3 (A1 & B1); Y1 = #1 (M1 | C1); end

A1 B1 C1 M1 Y1

behavioral

3
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VLSI - OVERVIEW
Customer Specification

Gate Level Net List Physical layout Full Custom ASIC

Logic Design/ Front End

Physical Design/ Back End

FPGA ASIC

Semi -Custom ASIC

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Gate Array ASIC

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PHYSICAL DESIGN

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Masks

FOUNDRY
Processed Wafer
ASIC processing

Si wafer

Chips

Finished ASIC Chemicals

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ASIC

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Design Summary

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Design Functional Parameters

Applications System On Chip Mobile Communications Networking Space/Automobile applications Signal Processing Remote Sensing
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ASIC Products
Examples :
SSI

: All 74 XX ,54 XX series gates

MSI: Decoders, mux, shift registers, counters etc. LSI: Memories, 8bit UPs/ UCs , Peripheral devises etc VLSI : X86 to pentium,memories,and fpgas & TTM Institute of Technology 44 ASICs

Applications Growth
.

1971 : Intel 4004 clock Ultra Sparc III 2001 : Intel P4 HP PA-8500

- 2300 transistors, 1 MHz - 16 Million transistors - 42 Million, 2 GHz clock - 140 Million transistor

Amazingly visionary million transistor/chip barrier was crossed in the 1980s

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VLSI Technology Trend

Design Characteristics
0.13M 12MHz 1.5um 1.2M 50MHz 0.8um 3.3M 200MHz 0.6um

7.5M 333MHz 0.25um

0.06M 2MHz 6um

SPICE Simulation

CAE Systems, Silicon compilation

HDLs, Synthesis

Top-Down Design, Emulation

Cycle-based simulation, Formal Verification

Key CAD Capabilities

The Challenges to sustain such an exponential growth to achieve gigascale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology. TTM Institute of Technology 46

Intel 4004 Microprocessor

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Intel Pentium (IV) Microprocessor

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The VLSI Chip in 2006

Technology Transistors Logic gates Size Clock Chip I/Os Wiring levels Voltage Power Supply current 0.1 um 200 M 40 M 520 mm2 2 - 3.5 GHz 4,000 7-8 0.9 - 1.2 160 Watts ~160 Amps

Performance Power consumption Noise immunity Area Cost Time-to-market

Tradeoffs!!!

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Design Abstraction Levels

SYSTEM

MODULE +

GATE CIRCUIT
Vin Vout

DEVICE
G S n+ D n+

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VLSI TECHNOLOGY
Encompasses different Design Domains:

Logic Design

As Code

Physical design

- As Layout

Product Fabrication - As product

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DESIGN METHODOLOGIES- Y CHART

BEHAVIORAL DOMAIN Application algorithms
programs Subroutines ,B.equations instructions Synthesis

STRUCTURAL DOMAIN

processors
ALUs , registers Logic gates

Transistors

Layout transistor Cells Chips / modules Circuit abstraction level Chips.MCM,boards

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Logic abstraction level

System abstractio level Micro architecture abstraction level 52

Physical domain

Overview Of VLSI Design Methodology

Summary :
* *
VLSI Design Methodology using Major Activity Blocks Explain the Activity in each of the above Block. A) Logic Design. B) Physical design c) Foundry

*
*

Types of libraries appended to Design Flow & its significance

Using HA Truth table derive the following a) Boolean Expression b) Behavioral Model C) Structural Model d) Physical Model e) Gate level Netlist

* With the help of Y-Chart explain Design domains and Levels of

Abstraction
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Thank You

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Technology Definition

SSI
MSI LSI VLSI

2 - 20 GATES

: 20 - 200 GATES : 200 - 2000,000 GATES : OVER 1 MILLION GATES

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Semiconductor Product Evolution (cont.)

1925 - MOSFET transistor Heil (England) 1935 - MOSFET transistor Lilienfeld (Canada) 1947 - Transistor Bardeen (Bell Labs) 1949 - Bipolar transistor Shockley 1956 - First bipolar digital logic gate by Harris 1959- First monolithic IC by Jack Kilby 1960 - First commercial IC logic gate by Fairchild
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Semiconductor Product Evolution

1960s - CMOS plagued with manufacturing problems 1960s - PMOS in (calculators) 1962 - 90 - TTL Logic gates 1974 - 80 - ECL Logic gates 1970s - NMOS in (4004, 8080) for speed 1980s - CMOS in preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K,
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Technology Evolution
YEAR ERA TECHNOLOGICAL BREAKTHROUGH

1920 -- Vacuum Tube - Vacuum Technology -- Glass to metal seal 1948 -- Transistor fabrication -- Crystal growth

1958 -- SSI - Planar technology - Digital Gates -- Photolithography 1962 -- MSI - PMOS Technology - Registers, -- Gate Oxide decoders, muxes 1968 -- LSI - NMOS Technology- Memory -- ION Implantation & CVD 1978 -- VLSI - CMOS Technology interconnect Micro processors
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-- multi layer Technology

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Evolution Of Microelectronics (cont.)

Dec. 1947: First Transistor 1960: Fairchilds first IC

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