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  • Lecture 11

    Diunggah oleh

    Sunil Kumar
    49 tayangan28 halaman
    Quiz #2 Write min-delay constraint for a pulsed latch-based sequential logic, where the pulse width is tpw, clock-to-Q delay is lower-bounded by tccq. Slave stage faster than the cross-coupled NAND during precharge, X=Xbar=1, blue TR's maintain the state. When X falls, Q and Qbar immediately (unlike cross coupled NAND) goes to high and low, respectively.

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    Quiz #2 Write min-delay constraint for a pulsed latch-based sequential logic, where the pulse width is tpw, clock-to-Q delay is lower-bounded by tccq. Slave stage faster than the cross-coupled NAND during precharge, X=Xbar=1, blue TR's maintain the state. When X falls, Q and Qbar immediately (unlike cross coupled NAND) goes to high and low, respectively.

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    Attribution Non-Commercial (BY-NC)
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    49 tayangan28 halaman

    Lecture 11

    Diunggah oleh

    Sunil Kumar
    Quiz #2 Write min-delay constraint for a pulsed latch-based sequential logic, where the pulse width is tpw, clock-to-Q delay is lower-bounded by tccq. Slave stage faster than the cross-coupled NAND during precharge, X=Xbar=1, blue TR's maintain the state. When X falls, Q and Qbar immediately (unlike cross coupled NAND) goes to high and low, respectively.

    Hak Cipta:

    Attribution Non-Commercial (BY-NC)
    Unduh sebagai PPT, PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    dari 28

    Lecture 11 (Chapter 7-3)

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-1

    Quiz #2
    Write min-delay constraint for a pulsed latch-based sequential logic, where the pulse width is tpw, clock-to-Q delay is lower-bounded by tccq. Hold time is thold and setup time is tsetup.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-2

    Homework #3 (due 4/1)


    Solve 6.23, 6.31, and 6.42

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-3

    Slave stage faster than the cross-coupled NAND

    During precharge , X=Xbar=1, blue TRs maintain the state. When X falls, Q and Qbar immediately (unlike cross coupled NAND) goes to high and low, respectively.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-4

    Differential flipflop
    When clock is low, X and Xbar are precharged. When clock goes high, Q and Qbar are evaluated according to D input. When D (and Dbar) changes During clock high, weak TR is necessary to staticize the internal nodes. High-skew inverters can be used for domino inputs in th4 next stage.
    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-5

    Differential FF used at AMD K6


    Pulsed output Self-reset (to Q=Qbar=0) Cross-coupled PMOS ; to improve noise immunity Cross-coupled inverters ; to staticize internal nodes %staticize ; to feed current to prevent a node from floating

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-6

    TSPC(True Single Phase Clock) Latch


    Not transparent during latching period P-latch followed by N-latch forms a positive edge-triggered flipflop

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-7

    Clocked CMOS (C2MOS) vs. Precharged CMOS


    Clocked CMOS ; simultaneous switching of PMOS and NMOS switches.
    -> (SP, SN) obtained by removing one switch (phase)

    Precharged CMOS;
    -> precharge is followed by evaluation by merging switch TRs into one phase, i.e., removing one phase
    -> domino or NORA (PP, PN) obtained by removing one signal transistor

    From C2MOS to four TSPC basic stages (SP, SN, PP, PN)
    1. xN or xP depending on NMOS(xN) or PMOS(xP) as middle TR 2. Standard (Sx) vs. Precharged (Px)

    TSPC latches ;
    should end with standard type stage
    1) Non-precharged type latch ; Standard + Standard
    2) Precharged type latch ; Precharged + Standard

    Split-output Latches
    1. Needs minimal (5) TRs 2. Threshold loss at one gate causing leakage problems

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-12

    Master is transparent during latching period (clock high) for high input, but slave stage is not transparent for that even during nonlatching(sampling) phase.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-13

    Split-output latch-based flipflop

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-14

    Static sequencing elements


    Flipflop
    Pulsed Latch Transparent Latch

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-15

    Clocked deracer is used in short paths


    for blocking incoming paths while receiving latch is transparent.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-16

    Long paths are not slowed by clock skewing.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-17

    WLAN receiver example


    Clock gating with packet sensing Slowing down clocks for reducing dynamic power

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-18

    Timing types : Definition of stable, valid, and qualified clock

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-19

    Latches take qualified clocks


    Phase 1(2) latch requires s1 or v1 input and produces s2 output. -> necessary condition for setup and hold time requirement. If all inputs are stable, output is stable.

    If any input is valid, output is valid.

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-20

    Rules for combining timing types

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-21

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-22

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-23

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-24

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-25

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-26

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-27

    Copyright 2005 Pearson Addison-Wesley. All rights reserved.

    7-28

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